tlb.cc (7678:f19b6a3a8cec) | tlb.cc (7741:340b6f01d69b) |
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1/* 2 * Copyright (c) 2001-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 117 unchanged lines hidden (view full) --- 126 tlb[x].used = false; 127 usedEntries--; 128 } 129 lookupTable.erase(tlb[x].range); 130 } 131 } 132 } 133 | 1/* 2 * Copyright (c) 2001-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 117 unchanged lines hidden (view full) --- 126 tlb[x].used = false; 127 usedEntries--; 128 } 129 lookupTable.erase(tlb[x].range); 130 } 131 } 132 } 133 |
134/* 135 i = lookupTable.find(tr); 136 if (i != lookupTable.end()) { 137 i->second->valid = false; 138 if (i->second->used) { 139 i->second->used = false; 140 usedEntries--; 141 } 142 freeList.push_front(i->second); 143 DPRINTF(TLB, "TLB: Found conflicting entry %#X , deleting it\n", 144 i->second); 145 lookupTable.erase(i); 146 } 147*/ 148 | |
149 if (entry != -1) { 150 assert(entry < size && entry >= 0); 151 new_entry = &tlb[entry]; 152 } else { 153 if (!freeList.empty()) { 154 new_entry = freeList.front(); 155 } else { 156 x = lastReplaced; 157 do { 158 ++x; 159 if (x == size) 160 x = 0; 161 if (x == lastReplaced) 162 goto insertAllLocked; 163 } while (tlb[x].pte.locked()); 164 lastReplaced = x; 165 new_entry = &tlb[x]; 166 } | 134 if (entry != -1) { 135 assert(entry < size && entry >= 0); 136 new_entry = &tlb[entry]; 137 } else { 138 if (!freeList.empty()) { 139 new_entry = freeList.front(); 140 } else { 141 x = lastReplaced; 142 do { 143 ++x; 144 if (x == size) 145 x = 0; 146 if (x == lastReplaced) 147 goto insertAllLocked; 148 } while (tlb[x].pte.locked()); 149 lastReplaced = x; 150 new_entry = &tlb[x]; 151 } |
167 /* 168 for (x = 0; x < size; x++) { 169 if (!tlb[x].valid || !tlb[x].used) { 170 new_entry = &tlb[x]; 171 break; 172 } 173 }*/ | |
174 } 175 176insertAllLocked: 177 // Update the last ently if their all locked 178 if (!new_entry) { 179 new_entry = &tlb[size-1]; 180 } 181 --- 455 unchanged lines hidden (view full) --- 637 context = 0; 638 } else { 639 asi = ASI_P; 640 ct = Primary; 641 context = pri_context; 642 } 643 } else { 644 // We need to check for priv level/asi priv | 152 } 153 154insertAllLocked: 155 // Update the last ently if their all locked 156 if (!new_entry) { 157 new_entry = &tlb[size-1]; 158 } 159 --- 455 unchanged lines hidden (view full) --- 615 context = 0; 616 } else { 617 asi = ASI_P; 618 ct = Primary; 619 context = pri_context; 620 } 621 } else { 622 // We need to check for priv level/asi priv |
645 if (!priv && !hpriv && !AsiIsUnPriv(asi)) { | 623 if (!priv && !hpriv && !asiIsUnPriv(asi)) { |
646 // It appears that context should be Nucleus in these cases? 647 writeSfsr(vaddr, write, Nucleus, false, IllegalAsi, asi); 648 return new PrivilegedAction; 649 } 650 | 624 // It appears that context should be Nucleus in these cases? 625 writeSfsr(vaddr, write, Nucleus, false, IllegalAsi, asi); 626 return new PrivilegedAction; 627 } 628 |
651 if (!hpriv && AsiIsHPriv(asi)) { | 629 if (!hpriv && asiIsHPriv(asi)) { |
652 writeSfsr(vaddr, write, Nucleus, false, IllegalAsi, asi); 653 return new DataAccessException; 654 } 655 | 630 writeSfsr(vaddr, write, Nucleus, false, IllegalAsi, asi); 631 return new DataAccessException; 632 } 633 |
656 if (AsiIsPrimary(asi)) { | 634 if (asiIsPrimary(asi)) { |
657 context = pri_context; 658 ct = Primary; | 635 context = pri_context; 636 ct = Primary; |
659 } else if (AsiIsSecondary(asi)) { | 637 } else if (asiIsSecondary(asi)) { |
660 context = sec_context; 661 ct = Secondary; | 638 context = sec_context; 639 ct = Secondary; |
662 } else if (AsiIsNucleus(asi)) { | 640 } else if (asiIsNucleus(asi)) { |
663 ct = Nucleus; 664 context = 0; 665 } else { // ???? 666 ct = Primary; 667 context = pri_context; 668 } 669 } 670 671 if (!implicit && asi != ASI_P && asi != ASI_S) { | 641 ct = Nucleus; 642 context = 0; 643 } else { // ???? 644 ct = Primary; 645 context = pri_context; 646 } 647 } 648 649 if (!implicit && asi != ASI_P && asi != ASI_S) { |
672 if (AsiIsLittle(asi)) | 650 if (asiIsLittle(asi)) |
673 panic("Little Endian ASIs not supported\n"); 674 675 //XXX It's unclear from looking at the documentation how a no fault | 651 panic("Little Endian ASIs not supported\n"); 652 653 //XXX It's unclear from looking at the documentation how a no fault |
676 //load differs from a regular one, other than what happens concerning 677 //nfo and e bits in the TTE 678// if (AsiIsNoFault(asi)) | 654 // load differs from a regular one, other than what happens concerning 655 // nfo and e bits in the TTE 656// if (asiIsNoFault(asi)) |
679// panic("No Fault ASIs not supported\n"); 680 | 657// panic("No Fault ASIs not supported\n"); 658 |
681 if (AsiIsPartialStore(asi)) | 659 if (asiIsPartialStore(asi)) |
682 panic("Partial Store ASIs not supported\n"); 683 | 660 panic("Partial Store ASIs not supported\n"); 661 |
684 if (AsiIsCmt(asi)) | 662 if (asiIsCmt(asi)) |
685 panic("Cmt ASI registers not implmented\n"); 686 | 663 panic("Cmt ASI registers not implmented\n"); 664 |
687 if (AsiIsInterrupt(asi)) | 665 if (asiIsInterrupt(asi)) |
688 goto handleIntRegAccess; | 666 goto handleIntRegAccess; |
689 if (AsiIsMmu(asi)) | 667 if (asiIsMmu(asi)) |
690 goto handleMmuRegAccess; | 668 goto handleMmuRegAccess; |
691 if (AsiIsScratchPad(asi)) | 669 if (asiIsScratchPad(asi)) |
692 goto handleScratchRegAccess; | 670 goto handleScratchRegAccess; |
693 if (AsiIsQueue(asi)) | 671 if (asiIsQueue(asi)) |
694 goto handleQueueRegAccess; | 672 goto handleQueueRegAccess; |
695 if (AsiIsSparcError(asi)) | 673 if (asiIsSparcError(asi)) |
696 goto handleSparcErrorRegAccess; 697 | 674 goto handleSparcErrorRegAccess; 675 |
698 if (!AsiIsReal(asi) && !AsiIsNucleus(asi) && !AsiIsAsIfUser(asi) && 699 !AsiIsTwin(asi) && !AsiIsBlock(asi) && !AsiIsNoFault(asi)) | 676 if (!asiIsReal(asi) && !asiIsNucleus(asi) && !asiIsAsIfUser(asi) && 677 !asiIsTwin(asi) && !asiIsBlock(asi) && !asiIsNoFault(asi)) |
700 panic("Accessing ASI %#X. Should we?\n", asi); 701 } 702 703 // If the asi is unaligned trap 704 if (unaligned) { 705 writeSfsr(vaddr, false, ct, false, OtherFault, asi); 706 return new MemAddressNotAligned; 707 } 708 709 if (addr_mask) 710 vaddr = vaddr & VAddrAMask; 711 712 if (!validVirtualAddress(vaddr, addr_mask)) { 713 writeSfsr(vaddr, false, ct, true, VaOutOfRange, asi); 714 return new DataAccessException; 715 } 716 | 678 panic("Accessing ASI %#X. Should we?\n", asi); 679 } 680 681 // If the asi is unaligned trap 682 if (unaligned) { 683 writeSfsr(vaddr, false, ct, false, OtherFault, asi); 684 return new MemAddressNotAligned; 685 } 686 687 if (addr_mask) 688 vaddr = vaddr & VAddrAMask; 689 690 if (!validVirtualAddress(vaddr, addr_mask)) { 691 writeSfsr(vaddr, false, ct, true, VaOutOfRange, asi); 692 return new DataAccessException; 693 } 694 |
717 if ((!lsu_dm && !hpriv && !red) || AsiIsReal(asi)) { | 695 if ((!lsu_dm && !hpriv && !red) || asiIsReal(asi)) { |
718 real = true; 719 context = 0; 720 } 721 | 696 real = true; 697 context = 0; 698 } 699 |
722 if (hpriv && (implicit || (!AsiIsAsIfUser(asi) && !AsiIsReal(asi)))) { | 700 if (hpriv && (implicit || (!asiIsAsIfUser(asi) && !asiIsReal(asi)))) { |
723 req->setPaddr(vaddr & PAddrImplMask); 724 return NoFault; 725 } 726 727 e = lookup(vaddr, part_id, real, context); 728 729 if (e == NULL || !e->valid) { 730 writeTagAccess(vaddr, context); --- 16 unchanged lines hidden (view full) --- 747 } 748 749 if (write && !e->pte.writable()) { 750 writeTagAccess(vaddr, context); 751 writeSfsr(vaddr, write, ct, e->pte.sideffect(), OtherFault, asi); 752 return new FastDataAccessProtection; 753 } 754 | 701 req->setPaddr(vaddr & PAddrImplMask); 702 return NoFault; 703 } 704 705 e = lookup(vaddr, part_id, real, context); 706 707 if (e == NULL || !e->valid) { 708 writeTagAccess(vaddr, context); --- 16 unchanged lines hidden (view full) --- 725 } 726 727 if (write && !e->pte.writable()) { 728 writeTagAccess(vaddr, context); 729 writeSfsr(vaddr, write, ct, e->pte.sideffect(), OtherFault, asi); 730 return new FastDataAccessProtection; 731 } 732 |
755 if (e->pte.nofault() && !AsiIsNoFault(asi)) { | 733 if (e->pte.nofault() && !asiIsNoFault(asi)) { |
756 writeTagAccess(vaddr, context); 757 writeSfsr(vaddr, write, ct, e->pte.sideffect(), LoadFromNfo, asi); 758 return new DataAccessException; 759 } 760 | 734 writeTagAccess(vaddr, context); 735 writeSfsr(vaddr, write, ct, e->pte.sideffect(), LoadFromNfo, asi); 736 return new DataAccessException; 737 } 738 |
761 if (e->pte.sideffect() && AsiIsNoFault(asi)) { | 739 if (e->pte.sideffect() && asiIsNoFault(asi)) { |
762 writeTagAccess(vaddr, context); 763 writeSfsr(vaddr, write, ct, e->pte.sideffect(), SideEffect, asi); 764 return new DataAccessException; 765 } 766 767 if (e->pte.sideffect() || (e->pte.paddr() >> 39) & 1) 768 req->setFlags(Request::UNCACHEABLE); 769 --- 432 unchanged lines hidden (view full) --- 1202 break; 1203 case 3: 1204 ctx_id = 0; 1205 break; 1206 default: 1207 ignore = true; 1208 } 1209 | 740 writeTagAccess(vaddr, context); 741 writeSfsr(vaddr, write, ct, e->pte.sideffect(), SideEffect, asi); 742 return new DataAccessException; 743 } 744 745 if (e->pte.sideffect() || (e->pte.paddr() >> 39) & 1) 746 req->setFlags(Request::UNCACHEABLE); 747 --- 432 unchanged lines hidden (view full) --- 1180 break; 1181 case 3: 1182 ctx_id = 0; 1183 break; 1184 default: 1185 ignore = true; 1186 } 1187 |
1210 switch(bits(va,7,6)) { | 1188 switch (bits(va,7,6)) { |
1211 case 0: // demap page 1212 if (!ignore) 1213 tc->getITBPtr()->demapPage(mbits(va,63,13), part_id, 1214 bits(va,9,9), ctx_id); 1215 break; | 1189 case 0: // demap page 1190 if (!ignore) 1191 tc->getITBPtr()->demapPage(mbits(va,63,13), part_id, 1192 bits(va,9,9), ctx_id); 1193 break; |
1216 case 1: //demap context | 1194 case 1: // demap context |
1217 if (!ignore) 1218 tc->getITBPtr()->demapContext(part_id, ctx_id); 1219 break; 1220 case 2: 1221 tc->getITBPtr()->demapAll(part_id); 1222 break; 1223 default: 1224 panic("Invalid type for IMMU demap\n"); --- 28 unchanged lines hidden (view full) --- 1253 break; 1254 case 3: 1255 ctx_id = 0; 1256 break; 1257 default: 1258 ignore = true; 1259 } 1260 | 1195 if (!ignore) 1196 tc->getITBPtr()->demapContext(part_id, ctx_id); 1197 break; 1198 case 2: 1199 tc->getITBPtr()->demapAll(part_id); 1200 break; 1201 default: 1202 panic("Invalid type for IMMU demap\n"); --- 28 unchanged lines hidden (view full) --- 1231 break; 1232 case 3: 1233 ctx_id = 0; 1234 break; 1235 default: 1236 ignore = true; 1237 } 1238 |
1261 switch(bits(va,7,6)) { | 1239 switch (bits(va,7,6)) { |
1262 case 0: // demap page 1263 if (!ignore) 1264 demapPage(mbits(va,63,13), part_id, bits(va,9,9), ctx_id); 1265 break; | 1240 case 0: // demap page 1241 if (!ignore) 1242 demapPage(mbits(va,63,13), part_id, bits(va,9,9), ctx_id); 1243 break; |
1266 case 1: //demap context | 1244 case 1: // demap context |
1267 if (!ignore) 1268 demapContext(part_id, ctx_id); 1269 break; 1270 case 2: 1271 demapAll(part_id); 1272 break; 1273 default: 1274 panic("Invalid type for IMMU demap\n"); --- 165 unchanged lines hidden --- | 1245 if (!ignore) 1246 demapContext(part_id, ctx_id); 1247 break; 1248 case 2: 1249 demapAll(part_id); 1250 break; 1251 default: 1252 panic("Invalid type for IMMU demap\n"); --- 165 unchanged lines hidden --- |