tlb.cc (6335:a08470cb53e5) tlb.cc (6428:9e35cdc95e81)
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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832 return new PrivilegedAction;
833 }
834 goto regAccessOk;
835
836
837regAccessOk:
838handleMmuRegAccess:
839 DPRINTF(TLB, "TLB: DTB Translating MM IPR access\n");
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 823 unchanged lines hidden (view full) ---

832 return new PrivilegedAction;
833 }
834 goto regAccessOk;
835
836
837regAccessOk:
838handleMmuRegAccess:
839 DPRINTF(TLB, "TLB: DTB Translating MM IPR access\n");
840 req->setMmapedIpr(true);
840 req->setFlags(Request::MMAPED_IPR);
841 req->setPaddr(req->getVaddr());
842 return NoFault;
843};
844
845Fault
846TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)
847{
848 if (mode == Execute)

--- 590 unchanged lines hidden --- 		841 req->setPaddr(req->getVaddr());
842 return NoFault;
843};
844
845Fault
846TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)
847{
848 if (mode == Execute)

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