tlb.cc (6022:410194bb3049) tlb.cc (6023:47b4fcb10c11)
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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838handleMmuRegAccess:
839 DPRINTF(TLB, "TLB: DTB Translating MM IPR access\n");
840 req->setMmapedIpr(true);
841 req->setPaddr(req->getVaddr());
842 return NoFault;
843};
844
845Fault
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 829 unchanged lines hidden (view full) ---

838handleMmuRegAccess:
839 DPRINTF(TLB, "TLB: DTB Translating MM IPR access\n");
840 req->setMmapedIpr(true);
841 req->setPaddr(req->getVaddr());
842 return NoFault;
843};
844
845Fault
846TLB::translateAtomic(RequestPtr req, ThreadContext *tc,
847 bool write, bool execute)
846TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)
848{
847{
849 if (execute)
848 if (mode == Execute)
850 return translateInst(req, tc);
851 else
849 return translateInst(req, tc);
850 else
852 return translateData(req, tc, write);
851 return translateData(req, tc, mode == Write);
853}
854
855void
856TLB::translateTiming(RequestPtr req, ThreadContext *tc,
852}
853
854void
855TLB::translateTiming(RequestPtr req, ThreadContext *tc,
857 Translation *translation, bool write, bool execute)
856 Translation *translation, Mode mode)
858{
859 assert(translation);
857{
858 assert(translation);
860 translation->finish(translateAtomic(req, tc, write, execute),
861 req, tc, write, execute);
859 translation->finish(translateAtomic(req, tc, mode), req, tc, mode);
862}
863
864#if FULL_SYSTEM
865
866Tick
867TLB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
868{
869 Addr va = pkt->getAddr();

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861
862#if FULL_SYSTEM
863
864Tick
865TLB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
866{
867 Addr va = pkt->getAddr();

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