tlb.cc (5894:8091ac99341a) tlb.cc (6022:410194bb3049)
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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62 c0_tsb_ps0 = 0;
63 c0_tsb_ps1 = 0;
64 c0_config = 0;
65 cx_tsb_ps0 = 0;
66 cx_tsb_ps1 = 0;
67 cx_config = 0;
68 sfsr = 0;
69 tag_access = 0;
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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62 c0_tsb_ps0 = 0;
63 c0_tsb_ps1 = 0;
64 c0_config = 0;
65 cx_tsb_ps0 = 0;
66 cx_tsb_ps1 = 0;
67 cx_config = 0;
68 sfsr = 0;
69 tag_access = 0;
70 sfar = 0;
71 cacheEntry[0] = NULL;
72 cacheEntry[1] = NULL;
70}
71
72void
73TLB::clearUsedBits()
74{
75 MapIter i;
76 for (i = lookupTable.begin(); i != lookupTable.end(); i++) {
77 TlbEntry *t = i->second;

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413{
414 DPRINTF(TLB, "TLB: Writing Tag Access: va: %#X ctx: %#X value: %#X\n",
415 va, context, mbits(va, 63,13) | mbits(context,12,0));
416
417 tag_access = mbits(va, 63,13) | mbits(context,12,0);
418}
419
420void
73}
74
75void
76TLB::clearUsedBits()
77{
78 MapIter i;
79 for (i = lookupTable.begin(); i != lookupTable.end(); i++) {
80 TlbEntry *t = i->second;

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416{
417 DPRINTF(TLB, "TLB: Writing Tag Access: va: %#X ctx: %#X value: %#X\n",
418 va, context, mbits(va, 63,13) | mbits(context,12,0));
419
420 tag_access = mbits(va, 63,13) | mbits(context,12,0);
421}
422
423void
421ITB::writeSfsr(bool write, ContextType ct, bool se, FaultTypes ft, int asi)
422{
423 DPRINTF(TLB, "TLB: ITB Fault: w=%d ct=%d ft=%d asi=%d\n",
424 (int)write, ct, ft, asi);
425 TLB::writeSfsr(write, ct, se, ft, asi);
426}
427
428void
429DTB::writeSfsr(Addr a, bool write, ContextType ct,
424TLB::writeSfsr(Addr a, bool write, ContextType ct,
430 bool se, FaultTypes ft, int asi)
431{
425 bool se, FaultTypes ft, int asi)
426{
432 DPRINTF(TLB, "TLB: DTB Fault: A=%#x w=%d ct=%d ft=%d asi=%d\n",
427 DPRINTF(TLB, "TLB: Fault: A=%#x w=%d ct=%d ft=%d asi=%d\n",
433 a, (int)write, ct, ft, asi);
434 TLB::writeSfsr(write, ct, se, ft, asi);
435 sfar = a;
436}
437
438Fault
428 a, (int)write, ct, ft, asi);
429 TLB::writeSfsr(write, ct, se, ft, asi);
430 sfar = a;
431}
432
433Fault
439ITB::translateAtomic(RequestPtr req, ThreadContext *tc)
434TLB::translateInst(RequestPtr req, ThreadContext *tc)
440{
441 uint64_t tlbdata = tc->readMiscRegNoEffect(MISCREG_TLB_DATA);
442
443 Addr vaddr = req->getVaddr();
444 TlbEntry *e;
445
446 assert(req->getAsi() == ASI_IMPLICIT);
447
448 DPRINTF(TLB, "TLB: ITB Request to translate va=%#x size=%d\n",
449 vaddr, req->getSize());
450
451 // Be fast if we can!
452 if (cacheValid && cacheState == tlbdata) {
435{
436 uint64_t tlbdata = tc->readMiscRegNoEffect(MISCREG_TLB_DATA);
437
438 Addr vaddr = req->getVaddr();
439 TlbEntry *e;
440
441 assert(req->getAsi() == ASI_IMPLICIT);
442
443 DPRINTF(TLB, "TLB: ITB Request to translate va=%#x size=%d\n",
444 vaddr, req->getSize());
445
446 // Be fast if we can!
447 if (cacheValid && cacheState == tlbdata) {
453 if (cacheEntry) {
454 if (cacheEntry->range.va < vaddr + sizeof(MachInst) &&
455 cacheEntry->range.va + cacheEntry->range.size >= vaddr) {
456 req->setPaddr(cacheEntry->pte.translate(vaddr));
448 if (cacheEntry[0]) {
449 if (cacheEntry[0]->range.va < vaddr + sizeof(MachInst) &&
450 cacheEntry[0]->range.va + cacheEntry[0]->range.size >= vaddr) {
451 req->setPaddr(cacheEntry[0]->pte.translate(vaddr));
457 return NoFault;
458 }
459 } else {
460 req->setPaddr(vaddr & PAddrImplMask);
461 return NoFault;
462 }
463 }
464

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487 asi = ASI_P;
488 ct = Primary;
489 context = pri_context;
490 }
491
492 if ( hpriv || red ) {
493 cacheValid = true;
494 cacheState = tlbdata;
452 return NoFault;
453 }
454 } else {
455 req->setPaddr(vaddr & PAddrImplMask);
456 return NoFault;
457 }
458 }
459

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482 asi = ASI_P;
483 ct = Primary;
484 context = pri_context;
485 }
486
487 if ( hpriv || red ) {
488 cacheValid = true;
489 cacheState = tlbdata;
495 cacheEntry = NULL;
490 cacheEntry[0] = NULL;
496 req->setPaddr(vaddr & PAddrImplMask);
497 return NoFault;
498 }
499
500 // If the access is unaligned trap
501 if (vaddr & 0x3) {
502 writeSfsr(false, ct, false, OtherFault, asi);
503 return new MemAddressNotAligned;

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536 writeTagAccess(vaddr, context);
537 writeSfsr(false, ct, false, PrivViolation, asi);
538 return new InstructionAccessException;
539 }
540
541 // cache translation date for next translation
542 cacheValid = true;
543 cacheState = tlbdata;
491 req->setPaddr(vaddr & PAddrImplMask);
492 return NoFault;
493 }
494
495 // If the access is unaligned trap
496 if (vaddr & 0x3) {
497 writeSfsr(false, ct, false, OtherFault, asi);
498 return new MemAddressNotAligned;

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531 writeTagAccess(vaddr, context);
532 writeSfsr(false, ct, false, PrivViolation, asi);
533 return new InstructionAccessException;
534 }
535
536 // cache translation date for next translation
537 cacheValid = true;
538 cacheState = tlbdata;
544 cacheEntry = e;
539 cacheEntry[0] = e;
545
546 req->setPaddr(e->pte.translate(vaddr));
547 DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr());
548 return NoFault;
549}
550
540
541 req->setPaddr(e->pte.translate(vaddr));
542 DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr());
543 return NoFault;
544}
545
551void
552ITB::translateTiming(RequestPtr req, ThreadContext *tc,
553 Translation *translation)
554{
555 assert(translation);
556 translation->finish(translateAtomic(req, tc), req, tc, false);
557}
558
559Fault
546Fault
560DTB::translateAtomic(RequestPtr req, ThreadContext *tc, bool write)
547TLB::translateData(RequestPtr req, ThreadContext *tc, bool write)
561{
562 /*
563 * @todo this could really use some profiling and fixing to make
564 * it faster!
565 */
566 uint64_t tlbdata = tc->readMiscRegNoEffect(MISCREG_TLB_DATA);
567 Addr vaddr = req->getVaddr();
568 Addr size = req->getSize();

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850regAccessOk:
851handleMmuRegAccess:
852 DPRINTF(TLB, "TLB: DTB Translating MM IPR access\n");
853 req->setMmapedIpr(true);
854 req->setPaddr(req->getVaddr());
855 return NoFault;
856};
857
548{
549 /*
550 * @todo this could really use some profiling and fixing to make
551 * it faster!
552 */
553 uint64_t tlbdata = tc->readMiscRegNoEffect(MISCREG_TLB_DATA);
554 Addr vaddr = req->getVaddr();
555 Addr size = req->getSize();

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837regAccessOk:
838handleMmuRegAccess:
839 DPRINTF(TLB, "TLB: DTB Translating MM IPR access\n");
840 req->setMmapedIpr(true);
841 req->setPaddr(req->getVaddr());
842 return NoFault;
843};
844
845Fault
846TLB::translateAtomic(RequestPtr req, ThreadContext *tc,
847 bool write, bool execute)
848{
849 if (execute)
850 return translateInst(req, tc);
851 else
852 return translateData(req, tc, write);
853}
854
858void
855void
859DTB::translateTiming(RequestPtr req, ThreadContext *tc,
860 Translation *translation, bool write)
856TLB::translateTiming(RequestPtr req, ThreadContext *tc,
857 Translation *translation, bool write, bool execute)
861{
862 assert(translation);
858{
859 assert(translation);
863 translation->finish(translateAtomic(req, tc, write), req, tc, write);
860 translation->finish(translateAtomic(req, tc, write, execute),
861 req, tc, write, execute);
864}
865
866#if FULL_SYSTEM
867
868Tick
862}
863
864#if FULL_SYSTEM
865
866Tick
869DTB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
867TLB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
870{
871 Addr va = pkt->getAddr();
872 ASI asi = (ASI)pkt->req->getAsi();
873 uint64_t temp;
874
875 DPRINTF(IPR, "Memory Mapped IPR Read: asi=%#X a=%#x\n",
876 (uint32_t)pkt->req->getAsi(), pkt->getAddr());
877
868{
869 Addr va = pkt->getAddr();
870 ASI asi = (ASI)pkt->req->getAsi();
871 uint64_t temp;
872
873 DPRINTF(IPR, "Memory Mapped IPR Read: asi=%#X a=%#x\n",
874 (uint32_t)pkt->req->getAsi(), pkt->getAddr());
875
878 ITB *itb = tc->getITBPtr();
876 TLB *itb = tc->getITBPtr();
879
880 switch (asi) {
881 case ASI_LSU_CONTROL_REG:
882 assert(va == 0);
883 pkt->set(tc->readMiscReg(MISCREG_MMU_LSU_CTRL));
884 break;
885 case ASI_MMU:
886 switch (va) {

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1046 panic("need to impl DTB::doMmuRegRead() got asi=%#x, va=%#x\n",
1047 (uint32_t)asi, va);
1048 }
1049 pkt->makeAtomicResponse();
1050 return tc->getCpuPtr()->ticks(1);
1051}
1052
1053Tick
877
878 switch (asi) {
879 case ASI_LSU_CONTROL_REG:
880 assert(va == 0);
881 pkt->set(tc->readMiscReg(MISCREG_MMU_LSU_CTRL));
882 break;
883 case ASI_MMU:
884 switch (va) {

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1044 panic("need to impl DTB::doMmuRegRead() got asi=%#x, va=%#x\n",
1045 (uint32_t)asi, va);
1046 }
1047 pkt->makeAtomicResponse();
1048 return tc->getCpuPtr()->ticks(1);
1049}
1050
1051Tick
1054DTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
1052TLB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
1055{
1056 uint64_t data = gtoh(pkt->get<uint64_t>());
1057 Addr va = pkt->getAddr();
1058 ASI asi = (ASI)pkt->req->getAsi();
1059
1060 Addr ta_insert;
1061 Addr va_insert;
1062 Addr ct_insert;
1063 int part_insert;
1064 int entry_insert = -1;
1065 bool real_insert;
1066 bool ignore;
1067 int part_id;
1068 int ctx_id;
1069 PageTableEntry pte;
1070
1071 DPRINTF(IPR, "Memory Mapped IPR Write: asi=%#X a=%#x d=%#X\n",
1072 (uint32_t)asi, va, data);
1073
1053{
1054 uint64_t data = gtoh(pkt->get<uint64_t>());
1055 Addr va = pkt->getAddr();
1056 ASI asi = (ASI)pkt->req->getAsi();
1057
1058 Addr ta_insert;
1059 Addr va_insert;
1060 Addr ct_insert;
1061 int part_insert;
1062 int entry_insert = -1;
1063 bool real_insert;
1064 bool ignore;
1065 int part_id;
1066 int ctx_id;
1067 PageTableEntry pte;
1068
1069 DPRINTF(IPR, "Memory Mapped IPR Write: asi=%#X a=%#x d=%#X\n",
1070 (uint32_t)asi, va, data);
1071
1074 ITB *itb = tc->getITBPtr();
1072 TLB *itb = tc->getITBPtr();
1075
1076 switch (asi) {
1077 case ASI_LSU_CONTROL_REG:
1078 assert(va == 0);
1079 tc->setMiscReg(MISCREG_MMU_LSU_CTRL, data);
1080 break;
1081 case ASI_MMU:
1082 switch (va) {

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1301 }
1302 pkt->makeAtomicResponse();
1303 return tc->getCpuPtr()->ticks(1);
1304}
1305
1306#endif
1307
1308void
1073
1074 switch (asi) {
1075 case ASI_LSU_CONTROL_REG:
1076 assert(va == 0);
1077 tc->setMiscReg(MISCREG_MMU_LSU_CTRL, data);
1078 break;
1079 case ASI_MMU:
1080 switch (va) {

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1299 }
1300 pkt->makeAtomicResponse();
1301 return tc->getCpuPtr()->ticks(1);
1302}
1303
1304#endif
1305
1306void
1309DTB::GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs)
1307TLB::GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs)
1310{
1311 uint64_t tag_access = mbits(addr,63,13) | mbits(ctx,12,0);
1308{
1309 uint64_t tag_access = mbits(addr,63,13) | mbits(ctx,12,0);
1312 ITB * itb = tc->getITBPtr();
1310 TLB * itb = tc->getITBPtr();
1313 ptrs[0] = MakeTsbPtr(Ps0, tag_access,
1314 c0_tsb_ps0,
1315 c0_config,
1316 cx_tsb_ps0,
1317 cx_config);
1318 ptrs[1] = MakeTsbPtr(Ps1, tag_access,
1319 c0_tsb_ps1,
1320 c0_config,

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1328 ptrs[3] = MakeTsbPtr(Ps1, tag_access,
1329 itb->c0_tsb_ps1,
1330 itb->c0_config,
1331 itb->cx_tsb_ps1,
1332 itb->cx_config);
1333}
1334
1335uint64_t
1311 ptrs[0] = MakeTsbPtr(Ps0, tag_access,
1312 c0_tsb_ps0,
1313 c0_config,
1314 cx_tsb_ps0,
1315 cx_config);
1316 ptrs[1] = MakeTsbPtr(Ps1, tag_access,
1317 c0_tsb_ps1,
1318 c0_config,

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1326 ptrs[3] = MakeTsbPtr(Ps1, tag_access,
1327 itb->c0_tsb_ps1,
1328 itb->c0_config,
1329 itb->cx_tsb_ps1,
1330 itb->cx_config);
1331}
1332
1333uint64_t
1336DTB::MakeTsbPtr(TsbPageSize ps, uint64_t tag_access, uint64_t c0_tsb,
1334TLB::MakeTsbPtr(TsbPageSize ps, uint64_t tag_access, uint64_t c0_tsb,
1337 uint64_t c0_config, uint64_t cX_tsb, uint64_t cX_config)
1338{
1339 uint64_t tsb;
1340 uint64_t config;
1341
1342 if (bits(tag_access, 12,0) == 0) {
1343 tsb = c0_tsb;
1344 config = c0_config;

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1386 SERIALIZE_SCALAR(cx_config);
1387 SERIALIZE_SCALAR(sfsr);
1388 SERIALIZE_SCALAR(tag_access);
1389
1390 for (int x = 0; x < size; x++) {
1391 nameOut(os, csprintf("%s.PTE%d", name(), x));
1392 tlb[x].serialize(os);
1393 }
1335 uint64_t c0_config, uint64_t cX_tsb, uint64_t cX_config)
1336{
1337 uint64_t tsb;
1338 uint64_t config;
1339
1340 if (bits(tag_access, 12,0) == 0) {
1341 tsb = c0_tsb;
1342 config = c0_config;

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1384 SERIALIZE_SCALAR(cx_config);
1385 SERIALIZE_SCALAR(sfsr);
1386 SERIALIZE_SCALAR(tag_access);
1387
1388 for (int x = 0; x < size; x++) {
1389 nameOut(os, csprintf("%s.PTE%d", name(), x));
1390 tlb[x].serialize(os);
1391 }
1392 SERIALIZE_SCALAR(sfar);
1394}
1395
1396void
1397TLB::unserialize(Checkpoint *cp, const std::string &section)
1398{
1399 int oldSize;
1400
1401 paramIn(cp, section, "size", oldSize);

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1424
1425 lookupTable.clear();
1426 for (int x = 0; x < size; x++) {
1427 tlb[x].unserialize(cp, csprintf("%s.PTE%d", section, x));
1428 if (tlb[x].valid)
1429 lookupTable.insert(tlb[x].range, &tlb[x]);
1430
1431 }
1393}
1394
1395void
1396TLB::unserialize(Checkpoint *cp, const std::string &section)
1397{
1398 int oldSize;
1399
1400 paramIn(cp, section, "size", oldSize);

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1423
1424 lookupTable.clear();
1425 for (int x = 0; x < size; x++) {
1426 tlb[x].unserialize(cp, csprintf("%s.PTE%d", section, x));
1427 if (tlb[x].valid)
1428 lookupTable.insert(tlb[x].range, &tlb[x]);
1429
1430 }
1432}
1433
1434void
1435DTB::serialize(std::ostream &os)
1436{
1437 TLB::serialize(os);
1438 SERIALIZE_SCALAR(sfar);
1439}
1440
1441void
1442DTB::unserialize(Checkpoint *cp, const std::string &section)
1443{
1444 TLB::unserialize(cp, section);
1445 UNSERIALIZE_SCALAR(sfar);
1446}
1447
1448/* end namespace SparcISA */ }
1449
1431 UNSERIALIZE_SCALAR(sfar);
1432}
1433
1434/* end namespace SparcISA */ }
1435
1450SparcISA::ITB *
1451SparcITBParams::create()
1436SparcISA::TLB *
1437SparcTLBParams::create()
1452{
1438{
1453 return new SparcISA::ITB(this);
1439 return new SparcISA::TLB(this);
1454}
1440}
1455
1456SparcISA::DTB *
1457SparcDTBParams::create()
1458{
1459 return new SparcISA::DTB(this);
1460}