tlb.cc (5891:73084c6bb183) tlb.cc (5894:8091ac99341a)
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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431{
432 DPRINTF(TLB, "TLB: DTB Fault: A=%#x w=%d ct=%d ft=%d asi=%d\n",
433 a, (int)write, ct, ft, asi);
434 TLB::writeSfsr(write, ct, se, ft, asi);
435 sfar = a;
436}
437
438Fault
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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431{
432 DPRINTF(TLB, "TLB: DTB Fault: A=%#x w=%d ct=%d ft=%d asi=%d\n",
433 a, (int)write, ct, ft, asi);
434 TLB::writeSfsr(write, ct, se, ft, asi);
435 sfar = a;
436}
437
438Fault
439ITB::translateAtomic(RequestPtr &req, ThreadContext *tc)
439ITB::translateAtomic(RequestPtr req, ThreadContext *tc)
440{
441 uint64_t tlbdata = tc->readMiscRegNoEffect(MISCREG_TLB_DATA);
442
443 Addr vaddr = req->getVaddr();
444 TlbEntry *e;
445
446 assert(req->getAsi() == ASI_IMPLICIT);
447

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543 cacheState = tlbdata;
544 cacheEntry = e;
545
546 req->setPaddr(e->pte.translate(vaddr));
547 DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr());
548 return NoFault;
549}
550
440{
441 uint64_t tlbdata = tc->readMiscRegNoEffect(MISCREG_TLB_DATA);
442
443 Addr vaddr = req->getVaddr();
444 TlbEntry *e;
445
446 assert(req->getAsi() == ASI_IMPLICIT);
447

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543 cacheState = tlbdata;
544 cacheEntry = e;
545
546 req->setPaddr(e->pte.translate(vaddr));
547 DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr());
548 return NoFault;
549}
550
551void
552ITB::translateTiming(RequestPtr req, ThreadContext *tc,
553 Translation *translation)
554{
555 assert(translation);
556 translation->finish(translateAtomic(req, tc), req, tc, false);
557}
558
551Fault
559Fault
552DTB::translateAtomic(RequestPtr &req, ThreadContext *tc, bool write)
560DTB::translateAtomic(RequestPtr req, ThreadContext *tc, bool write)
553{
554 /*
555 * @todo this could really use some profiling and fixing to make
556 * it faster!
557 */
558 uint64_t tlbdata = tc->readMiscRegNoEffect(MISCREG_TLB_DATA);
559 Addr vaddr = req->getVaddr();
560 Addr size = req->getSize();

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842regAccessOk:
843handleMmuRegAccess:
844 DPRINTF(TLB, "TLB: DTB Translating MM IPR access\n");
845 req->setMmapedIpr(true);
846 req->setPaddr(req->getVaddr());
847 return NoFault;
848};
849
561{
562 /*
563 * @todo this could really use some profiling and fixing to make
564 * it faster!
565 */
566 uint64_t tlbdata = tc->readMiscRegNoEffect(MISCREG_TLB_DATA);
567 Addr vaddr = req->getVaddr();
568 Addr size = req->getSize();

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850regAccessOk:
851handleMmuRegAccess:
852 DPRINTF(TLB, "TLB: DTB Translating MM IPR access\n");
853 req->setMmapedIpr(true);
854 req->setPaddr(req->getVaddr());
855 return NoFault;
856};
857
858void
859DTB::translateTiming(RequestPtr req, ThreadContext *tc,
860 Translation *translation, bool write)
861{
862 assert(translation);
863 translation->finish(translateAtomic(req, tc, write), req, tc, write);
864}
865
850#if FULL_SYSTEM
851
852Tick
853DTB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
854{
855 Addr va = pkt->getAddr();
856 ASI asi = (ASI)pkt->req->getAsi();
857 uint64_t temp;

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867
868Tick
869DTB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
870{
871 Addr va = pkt->getAddr();
872 ASI asi = (ASI)pkt->req->getAsi();
873 uint64_t temp;

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