tlb.cc (5823:9f7efe90084e) | tlb.cc (5891:73084c6bb183) |
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1/* 2 * Copyright (c) 2001-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 422 unchanged lines hidden (view full) --- 431{ 432 DPRINTF(TLB, "TLB: DTB Fault: A=%#x w=%d ct=%d ft=%d asi=%d\n", 433 a, (int)write, ct, ft, asi); 434 TLB::writeSfsr(write, ct, se, ft, asi); 435 sfar = a; 436} 437 438Fault | 1/* 2 * Copyright (c) 2001-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 422 unchanged lines hidden (view full) --- 431{ 432 DPRINTF(TLB, "TLB: DTB Fault: A=%#x w=%d ct=%d ft=%d asi=%d\n", 433 a, (int)write, ct, ft, asi); 434 TLB::writeSfsr(write, ct, se, ft, asi); 435 sfar = a; 436} 437 438Fault |
439ITB::translate(RequestPtr &req, ThreadContext *tc) | 439ITB::translateAtomic(RequestPtr &req, ThreadContext *tc) |
440{ 441 uint64_t tlbdata = tc->readMiscRegNoEffect(MISCREG_TLB_DATA); 442 443 Addr vaddr = req->getVaddr(); 444 TlbEntry *e; 445 446 assert(req->getAsi() == ASI_IMPLICIT); 447 --- 96 unchanged lines hidden (view full) --- 544 cacheEntry = e; 545 546 req->setPaddr(e->pte.translate(vaddr)); 547 DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr()); 548 return NoFault; 549} 550 551Fault | 440{ 441 uint64_t tlbdata = tc->readMiscRegNoEffect(MISCREG_TLB_DATA); 442 443 Addr vaddr = req->getVaddr(); 444 TlbEntry *e; 445 446 assert(req->getAsi() == ASI_IMPLICIT); 447 --- 96 unchanged lines hidden (view full) --- 544 cacheEntry = e; 545 546 req->setPaddr(e->pte.translate(vaddr)); 547 DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr()); 548 return NoFault; 549} 550 551Fault |
552DTB::translate(RequestPtr &req, ThreadContext *tc, bool write) | 552DTB::translateAtomic(RequestPtr &req, ThreadContext *tc, bool write) |
553{ 554 /* 555 * @todo this could really use some profiling and fixing to make 556 * it faster! 557 */ 558 uint64_t tlbdata = tc->readMiscRegNoEffect(MISCREG_TLB_DATA); 559 Addr vaddr = req->getVaddr(); 560 Addr size = req->getSize(); --- 884 unchanged lines hidden --- | 553{ 554 /* 555 * @todo this could really use some profiling and fixing to make 556 * it faster! 557 */ 558 uint64_t tlbdata = tc->readMiscRegNoEffect(MISCREG_TLB_DATA); 559 Addr vaddr = req->getVaddr(); 560 Addr size = req->getSize(); --- 884 unchanged lines hidden --- |