tlb.cc (5736:426510e758ad) tlb.cc (5823:9f7efe90084e)
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 1115 unchanged lines hidden (view full) ---

1124 itb->cx_tsb_ps1 = data;
1125 break;
1126 case ASI_IMMU_CTXT_NONZERO_CONFIG:
1127 assert(va == 0);
1128 itb->cx_config = data;
1129 break;
1130 case ASI_SPARC_ERROR_EN_REG:
1131 case ASI_SPARC_ERROR_STATUS_REG:
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 1115 unchanged lines hidden (view full) ---

1124 itb->cx_tsb_ps1 = data;
1125 break;
1126 case ASI_IMMU_CTXT_NONZERO_CONFIG:
1127 assert(va == 0);
1128 itb->cx_config = data;
1129 break;
1130 case ASI_SPARC_ERROR_EN_REG:
1131 case ASI_SPARC_ERROR_STATUS_REG:
1132 warn("Ignoring write to SPARC ERROR regsiter\n");
1132 inform("Ignoring write to SPARC ERROR regsiter\n");
1133 break;
1134 case ASI_HYP_SCRATCHPAD:
1135 case ASI_SCRATCHPAD:
1136 tc->setMiscReg(MISCREG_SCRATCHPAD_R0 + (va >> 3), data);
1137 break;
1138 case ASI_IMMU:
1139 switch (va) {
1140 case 0x18:

--- 304 unchanged lines hidden --- 		1133 break;
1134 case ASI_HYP_SCRATCHPAD:
1135 case ASI_SCRATCHPAD:
1136 tc->setMiscReg(MISCREG_SCRATCHPAD_R0 + (va >> 3), data);
1137 break;
1138 case ASI_IMMU:
1139 switch (va) {
1140 case 0x18:

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