tlb.cc (5704:98224505352a) tlb.cc (5736:426510e758ad)
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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589 if (cacheEntry[0]) {
590 TlbEntry *ce = cacheEntry[0];
591 Addr ce_va = ce->range.va;
592 if (cacheAsi[0] == asi &&
593 ce_va < vaddr + size && ce_va + ce->range.size > vaddr &&
594 (!write || ce->pte.writable())) {
595 req->setPaddr(ce->pte.translate(vaddr));
596 if (ce->pte.sideffect() || (ce->pte.paddr() >> 39) & 1)
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 580 unchanged lines hidden (view full) ---

589 if (cacheEntry[0]) {
590 TlbEntry *ce = cacheEntry[0];
591 Addr ce_va = ce->range.va;
592 if (cacheAsi[0] == asi &&
593 ce_va < vaddr + size && ce_va + ce->range.size > vaddr &&
594 (!write || ce->pte.writable())) {
595 req->setPaddr(ce->pte.translate(vaddr));
596 if (ce->pte.sideffect() || (ce->pte.paddr() >> 39) & 1)
597 req->setFlags(req->getFlags() | UNCACHEABLE);
597 req->setFlags(Request::UNCACHEABLE);
598 DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr());
599 return NoFault;
600 } // if matched
601 } // if cache entry valid
602 if (cacheEntry[1]) {
603 TlbEntry *ce = cacheEntry[1];
604 Addr ce_va = ce->range.va;
605 if (cacheAsi[1] == asi &&
606 ce_va < vaddr + size && ce_va + ce->range.size > vaddr &&
607 (!write || ce->pte.writable())) {
608 req->setPaddr(ce->pte.translate(vaddr));
609 if (ce->pte.sideffect() || (ce->pte.paddr() >> 39) & 1)
598 DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr());
599 return NoFault;
600 } // if matched
601 } // if cache entry valid
602 if (cacheEntry[1]) {
603 TlbEntry *ce = cacheEntry[1];
604 Addr ce_va = ce->range.va;
605 if (cacheAsi[1] == asi &&
606 ce_va < vaddr + size && ce_va + ce->range.size > vaddr &&
607 (!write || ce->pte.writable())) {
608 req->setPaddr(ce->pte.translate(vaddr));
609 if (ce->pte.sideffect() || (ce->pte.paddr() >> 39) & 1)
610 req->setFlags(req->getFlags() | UNCACHEABLE);
610 req->setFlags(Request::UNCACHEABLE);
611 DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr());
612 return NoFault;
613 } // if matched
614 } // if cache entry valid
615 }
616 }
617
618 bool red = bits(tlbdata,1,1);

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764
765 if (e->pte.sideffect() && AsiIsNoFault(asi)) {
766 writeTagAccess(vaddr, context);
767 writeSfsr(vaddr, write, ct, e->pte.sideffect(), SideEffect, asi);
768 return new DataAccessException;
769 }
770
771 if (e->pte.sideffect() || (e->pte.paddr() >> 39) & 1)
611 DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr());
612 return NoFault;
613 } // if matched
614 } // if cache entry valid
615 }
616 }
617
618 bool red = bits(tlbdata,1,1);

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764
765 if (e->pte.sideffect() && AsiIsNoFault(asi)) {
766 writeTagAccess(vaddr, context);
767 writeSfsr(vaddr, write, ct, e->pte.sideffect(), SideEffect, asi);
768 return new DataAccessException;
769 }
770
771 if (e->pte.sideffect() || (e->pte.paddr() >> 39) & 1)
772 req->setFlags(req->getFlags() | UNCACHEABLE);
772 req->setFlags(Request::UNCACHEABLE);
773
774 // cache translation date for next translation
775 cacheState = tlbdata;
776 if (!cacheValid) {
777 cacheEntry[1] = NULL;
778 cacheEntry[0] = NULL;
779 }
780

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774 // cache translation date for next translation
775 cacheState = tlbdata;
776 if (!cacheValid) {
777 cacheEntry[1] = NULL;
778 cacheEntry[0] = NULL;
779 }
780

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