tlb.cc (5646:0a488a147fb8) tlb.cc (5704:98224505352a)
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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1016 }
1017 break;
1018 case ASI_SWVR_UDB_INTR_R:
1019 {
1020 SparcISA::Interrupts * interrupts =
1021 dynamic_cast<SparcISA::Interrupts *>(
1022 tc->getCpuPtr()->getInterruptController());
1023 temp = findMsbSet(interrupts->get_vec(IT_INT_VEC));
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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1016 }
1017 break;
1018 case ASI_SWVR_UDB_INTR_R:
1019 {
1020 SparcISA::Interrupts * interrupts =
1021 dynamic_cast<SparcISA::Interrupts *>(
1022 tc->getCpuPtr()->getInterruptController());
1023 temp = findMsbSet(interrupts->get_vec(IT_INT_VEC));
1024 tc->getCpuPtr()->clear_interrupt(IT_INT_VEC, temp);
1024 tc->getCpuPtr()->clearInterrupt(IT_INT_VEC, temp);
1025 pkt->set(temp);
1026 }
1027 break;
1028 default:
1029doMmuReadError:
1030 panic("need to impl DTB::doMmuRegRead() got asi=%#x, va=%#x\n",
1031 (uint32_t)asi, va);
1032 }

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1263 break;
1264 case ASI_SWVR_INTR_RECEIVE:
1265 {
1266 int msb;
1267 // clear all the interrupts that aren't set in the write
1268 SparcISA::Interrupts * interrupts =
1269 dynamic_cast<SparcISA::Interrupts *>(
1270 tc->getCpuPtr()->getInterruptController());
1025 pkt->set(temp);
1026 }
1027 break;
1028 default:
1029doMmuReadError:
1030 panic("need to impl DTB::doMmuRegRead() got asi=%#x, va=%#x\n",
1031 (uint32_t)asi, va);
1032 }

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1263 break;
1264 case ASI_SWVR_INTR_RECEIVE:
1265 {
1266 int msb;
1267 // clear all the interrupts that aren't set in the write
1268 SparcISA::Interrupts * interrupts =
1269 dynamic_cast<SparcISA::Interrupts *>(
1270 tc->getCpuPtr()->getInterruptController());
1271 while(interrupts->get_vec(IT_INT_VEC) & data) {
1271 while (interrupts->get_vec(IT_INT_VEC) & data) {
1272 msb = findMsbSet(interrupts->get_vec(IT_INT_VEC) & data);
1272 msb = findMsbSet(interrupts->get_vec(IT_INT_VEC) & data);
1273 tc->getCpuPtr()->clear_interrupt(IT_INT_VEC, msb);
1273 tc->getCpuPtr()->clearInterrupt(IT_INT_VEC, msb);
1274 }
1275 }
1276 break;
1277 case ASI_SWVR_UDB_INTR_W:
1278 tc->getSystemPtr()->threadContexts[bits(data,12,8)]->getCpuPtr()->
1274 }
1275 }
1276 break;
1277 case ASI_SWVR_UDB_INTR_W:
1278 tc->getSystemPtr()->threadContexts[bits(data,12,8)]->getCpuPtr()->
1279 post_interrupt(bits(data,5,0),0);
1279 postInterrupt(bits(data, 5, 0), 0);
1280 break;
1281 default:
1282doMmuWriteError:
1283 panic("need to impl DTB::doMmuRegWrite() got asi=%#x, va=%#x d=%#x\n",
1284 (uint32_t)pkt->req->getAsi(), pkt->getAddr(), data);
1285 }
1286 pkt->makeAtomicResponse();
1287 return tc->getCpuPtr()->ticks(1);

--- 157 unchanged lines hidden --- 		1280 break;
1281 default:
1282doMmuWriteError:
1283 panic("need to impl DTB::doMmuRegWrite() got asi=%#x, va=%#x d=%#x\n",
1284 (uint32_t)pkt->req->getAsi(), pkt->getAddr(), data);
1285 }
1286 pkt->makeAtomicResponse();
1287 return tc->getCpuPtr()->ticks(1);

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