tlb.cc (5570:13592d41f290) tlb.cc (5646:0a488a147fb8)
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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1003 pkt->set(MakeTsbPtr(Ps1,
1004 itb->tag_access,
1005 itb->c0_tsb_ps1,
1006 itb->c0_config,
1007 itb->cx_tsb_ps1,
1008 itb->cx_config));
1009 break;
1010 case ASI_SWVR_INTR_RECEIVE:
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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1003 pkt->set(MakeTsbPtr(Ps1,
1004 itb->tag_access,
1005 itb->c0_tsb_ps1,
1006 itb->c0_config,
1007 itb->cx_tsb_ps1,
1008 itb->cx_config));
1009 break;
1010 case ASI_SWVR_INTR_RECEIVE:
1011 pkt->set(tc->getCpuPtr()->get_interrupts(IT_INT_VEC));
1011 {
1012 SparcISA::Interrupts * interrupts =
1013 dynamic_cast<SparcISA::Interrupts *>(
1014 tc->getCpuPtr()->getInterruptController());
1015 pkt->set(interrupts->get_vec(IT_INT_VEC));
1016 }
1012 break;
1013 case ASI_SWVR_UDB_INTR_R:
1017 break;
1018 case ASI_SWVR_UDB_INTR_R:
1014 temp = findMsbSet(tc->getCpuPtr()->get_interrupts(IT_INT_VEC));
1015 tc->getCpuPtr()->clear_interrupt(IT_INT_VEC, temp);
1016 pkt->set(temp);
1019 {
1020 SparcISA::Interrupts * interrupts =
1021 dynamic_cast<SparcISA::Interrupts *>(
1022 tc->getCpuPtr()->getInterruptController());
1023 temp = findMsbSet(interrupts->get_vec(IT_INT_VEC));
1024 tc->getCpuPtr()->clear_interrupt(IT_INT_VEC, temp);
1025 pkt->set(temp);
1026 }
1017 break;
1018 default:
1019doMmuReadError:
1020 panic("need to impl DTB::doMmuRegRead() got asi=%#x, va=%#x\n",
1021 (uint32_t)asi, va);
1022 }
1023 pkt->makeAtomicResponse();
1024 return tc->getCpuPtr()->ticks(1);

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1247 case 2:
1248 demapAll(part_id);
1249 break;
1250 default:
1251 panic("Invalid type for IMMU demap\n");
1252 }
1253 break;
1254 case ASI_SWVR_INTR_RECEIVE:
1027 break;
1028 default:
1029doMmuReadError:
1030 panic("need to impl DTB::doMmuRegRead() got asi=%#x, va=%#x\n",
1031 (uint32_t)asi, va);
1032 }
1033 pkt->makeAtomicResponse();
1034 return tc->getCpuPtr()->ticks(1);

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1257 case 2:
1258 demapAll(part_id);
1259 break;
1260 default:
1261 panic("Invalid type for IMMU demap\n");
1262 }
1263 break;
1264 case ASI_SWVR_INTR_RECEIVE:
1255 int msb;
1256 // clear all the interrupts that aren't set in the write
1257 while(tc->getCpuPtr()->get_interrupts(IT_INT_VEC) & data) {
1258 msb = findMsbSet(tc->getCpuPtr()->get_interrupts(IT_INT_VEC) & data);
1259 tc->getCpuPtr()->clear_interrupt(IT_INT_VEC, msb);
1265 {
1266 int msb;
1267 // clear all the interrupts that aren't set in the write
1268 SparcISA::Interrupts * interrupts =
1269 dynamic_cast<SparcISA::Interrupts *>(
1270 tc->getCpuPtr()->getInterruptController());
1271 while(interrupts->get_vec(IT_INT_VEC) & data) {
1272 msb = findMsbSet(interrupts->get_vec(IT_INT_VEC) & data);
1273 tc->getCpuPtr()->clear_interrupt(IT_INT_VEC, msb);
1274 }
1260 }
1261 break;
1262 case ASI_SWVR_UDB_INTR_W:
1263 tc->getSystemPtr()->threadContexts[bits(data,12,8)]->getCpuPtr()->
1264 post_interrupt(bits(data,5,0),0);
1265 break;
1266 default:
1267doMmuWriteError:

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1276 break;
1277 case ASI_SWVR_UDB_INTR_W:
1278 tc->getSystemPtr()->threadContexts[bits(data,12,8)]->getCpuPtr()->
1279 post_interrupt(bits(data,5,0),0);
1280 break;
1281 default:
1282doMmuWriteError:

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