tlb.cc (5312:1dc4440797b6) tlb.cc (5358:e9acb84bbafb)
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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41#include "mem/request.hh"
42#include "sim/system.hh"
43
44/* @todo remove some of the magic constants. -- ali
45 * */
46namespace SparcISA {
47
48TLB::TLB(const Params *p)
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 32 unchanged lines hidden (view full) ---

41#include "mem/request.hh"
42#include "sim/system.hh"
43
44/* @todo remove some of the magic constants. -- ali
45 * */
46namespace SparcISA {
47
48TLB::TLB(const Params *p)
49 : SimObject(p), size(p->size), usedEntries(0), lastReplaced(0),
49 : BaseTLB(p), size(p->size), usedEntries(0), lastReplaced(0),
50 cacheValid(false)
51{
52 // To make this work you'll have to change the hypervisor and OS
53 if (size > 64)
54 fatal("SPARC T1 TLB registers don't support more than 64 TLB entries.");
55
56 tlb = new TlbEntry[size];
57 std::memset(tlb, 0, sizeof(TlbEntry) * size);

--- 1386 unchanged lines hidden --- 		50 cacheValid(false)
51{
52 // To make this work you'll have to change the hypervisor and OS
53 if (size > 64)
54 fatal("SPARC T1 TLB registers don't support more than 64 TLB entries.");
55
56 tlb = new TlbEntry[size];
57 std::memset(tlb, 0, sizeof(TlbEntry) * size);

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