tlb.cc (5034:6186ef720dd4) tlb.cc (5100:7a0180040755)
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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1028 pkt->set(temp);
1029 break;
1030 default:
1031doMmuReadError:
1032 panic("need to impl DTB::doMmuRegRead() got asi=%#x, va=%#x\n",
1033 (uint32_t)asi, va);
1034 }
1035 pkt->makeAtomicResponse();
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 1019 unchanged lines hidden (view full) ---

1028 pkt->set(temp);
1029 break;
1030 default:
1031doMmuReadError:
1032 panic("need to impl DTB::doMmuRegRead() got asi=%#x, va=%#x\n",
1033 (uint32_t)asi, va);
1034 }
1035 pkt->makeAtomicResponse();
1036 return tc->getCpuPtr()->cycles(1);
1036 return tc->getCpuPtr()->ticks(1);
1037}
1038
1039Tick
1040DTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
1041{
1042 uint64_t data = gtoh(pkt->get<uint64_t>());
1043 Addr va = pkt->getAddr();
1044 ASI asi = (ASI)pkt->req->getAsi();

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1275 post_interrupt(bits(data,5,0),0);
1276 break;
1277 default:
1278doMmuWriteError:
1279 panic("need to impl DTB::doMmuRegWrite() got asi=%#x, va=%#x d=%#x\n",
1280 (uint32_t)pkt->req->getAsi(), pkt->getAddr(), data);
1281 }
1282 pkt->makeAtomicResponse();
1037}
1038
1039Tick
1040DTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
1041{
1042 uint64_t data = gtoh(pkt->get<uint64_t>());
1043 Addr va = pkt->getAddr();
1044 ASI asi = (ASI)pkt->req->getAsi();

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1275 post_interrupt(bits(data,5,0),0);
1276 break;
1277 default:
1278doMmuWriteError:
1279 panic("need to impl DTB::doMmuRegWrite() got asi=%#x, va=%#x d=%#x\n",
1280 (uint32_t)pkt->req->getAsi(), pkt->getAddr(), data);
1281 }
1282 pkt->makeAtomicResponse();
1283 return tc->getCpuPtr()->cycles(1);
1283 return tc->getCpuPtr()->ticks(1);
1284}
1285
1286#endif
1287
1288void
1289DTB::GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs)
1290{
1291 uint64_t tag_access = mbits(addr,63,13) | mbits(ctx,12,0);

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1285
1286#endif
1287
1288void
1289DTB::GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs)
1290{
1291 uint64_t tag_access = mbits(addr,63,13) | mbits(ctx,12,0);

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