tlb.cc (4996:e827e57a01f9) tlb.cc (4997:e7380529bd2d)
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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530 e = lookup(vaddr, part_id, false, context);
531 }
532
533 if (e == NULL || !e->valid) {
534 writeTagAccess(vaddr, context);
535 if (real)
536 return new InstructionRealTranslationMiss;
537 else
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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530 e = lookup(vaddr, part_id, false, context);
531 }
532
533 if (e == NULL || !e->valid) {
534 writeTagAccess(vaddr, context);
535 if (real)
536 return new InstructionRealTranslationMiss;
537 else
538#if FULL_SYSTEM
538 return new FastInstructionAccessMMUMiss;
539 return new FastInstructionAccessMMUMiss;
540#else
541 return new FastInstructionAccessMMUMiss(req->getVaddr());
542#endif
539 }
540
541 // were not priviledged accesing priv page
542 if (!priv && e->pte.priv()) {
543 writeTagAccess(vaddr, context);
544 writeSfsr(false, ct, false, PrivViolation, asi);
545 return new InstructionAccessException;
546 }

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739 e = lookup(vaddr, part_id, real, context);
740
741 if (e == NULL || !e->valid) {
742 writeTagAccess(vaddr, context);
743 DPRINTF(TLB, "TLB: DTB Failed to find matching TLB entry\n");
744 if (real)
745 return new DataRealTranslationMiss;
746 else
543 }
544
545 // were not priviledged accesing priv page
546 if (!priv && e->pte.priv()) {
547 writeTagAccess(vaddr, context);
548 writeSfsr(false, ct, false, PrivViolation, asi);
549 return new InstructionAccessException;
550 }

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743 e = lookup(vaddr, part_id, real, context);
744
745 if (e == NULL || !e->valid) {
746 writeTagAccess(vaddr, context);
747 DPRINTF(TLB, "TLB: DTB Failed to find matching TLB entry\n");
748 if (real)
749 return new DataRealTranslationMiss;
750 else
751#if FULL_SYSTEM
747 return new FastDataAccessMMUMiss;
752 return new FastDataAccessMMUMiss;
753#else
754 return new FastDataAccessMMUMiss(req->getVaddr());
755#endif
748
749 }
750
751 if (!priv && e->pte.priv()) {
752 writeTagAccess(vaddr, context);
753 writeSfsr(vaddr, write, ct, e->pte.sideffect(), PrivViolation, asi);
754 return new DataAccessException;
755 }

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848regAccessOk:
849handleMmuRegAccess:
850 DPRINTF(TLB, "TLB: DTB Translating MM IPR access\n");
851 req->setMmapedIpr(true);
852 req->setPaddr(req->getVaddr());
853 return NoFault;
854};
855
756
757 }
758
759 if (!priv && e->pte.priv()) {
760 writeTagAccess(vaddr, context);
761 writeSfsr(vaddr, write, ct, e->pte.sideffect(), PrivViolation, asi);
762 return new DataAccessException;
763 }

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856regAccessOk:
857handleMmuRegAccess:
858 DPRINTF(TLB, "TLB: DTB Translating MM IPR access\n");
859 req->setMmapedIpr(true);
860 req->setPaddr(req->getVaddr());
861 return NoFault;
862};
863
864#if FULL_SYSTEM
865
856Tick
857DTB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
858{
859 Addr va = pkt->getAddr();
860 ASI asi = (ASI)pkt->req->getAsi();
861 uint64_t temp;
862
863 DPRINTF(IPR, "Memory Mapped IPR Read: asi=%#X a=%#x\n",

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1270doMmuWriteError:
1271 panic("need to impl DTB::doMmuRegWrite() got asi=%#x, va=%#x d=%#x\n",
1272 (uint32_t)pkt->req->getAsi(), pkt->getAddr(), data);
1273 }
1274 pkt->makeAtomicResponse();
1275 return tc->getCpuPtr()->cycles(1);
1276}
1277
866Tick
867DTB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
868{
869 Addr va = pkt->getAddr();
870 ASI asi = (ASI)pkt->req->getAsi();
871 uint64_t temp;
872
873 DPRINTF(IPR, "Memory Mapped IPR Read: asi=%#X a=%#x\n",

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1280doMmuWriteError:
1281 panic("need to impl DTB::doMmuRegWrite() got asi=%#x, va=%#x d=%#x\n",
1282 (uint32_t)pkt->req->getAsi(), pkt->getAddr(), data);
1283 }
1284 pkt->makeAtomicResponse();
1285 return tc->getCpuPtr()->cycles(1);
1286}
1287
1288#endif
1289
1278void
1279DTB::GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs)
1280{
1281 uint64_t tag_access = mbits(addr,63,13) | mbits(ctx,12,0);
1282 ITB * itb = tc->getITBPtr();
1283 ptrs[0] = MakeTsbPtr(Ps0, tag_access,
1284 c0_tsb_ps0,
1285 c0_config,

--- 150 unchanged lines hidden --- 		1290void
1291DTB::GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs)
1292{
1293 uint64_t tag_access = mbits(addr,63,13) | mbits(ctx,12,0);
1294 ITB * itb = tc->getITBPtr();
1295 ptrs[0] = MakeTsbPtr(Ps0, tag_access,
1296 c0_tsb_ps0,
1297 c0_config,

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