tlb.cc (4990:38d74405ddac) tlb.cc (4996:e827e57a01f9)
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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564 /* @todo this could really use some profiling and fixing to make it faster! */
565 uint64_t tlbdata = tc->readMiscRegNoEffect(MISCREG_TLB_DATA);
566 Addr vaddr = req->getVaddr();
567 Addr size = req->getSize();
568 ASI asi;
569 asi = (ASI)req->getAsi();
570 bool implicit = false;
571 bool hpriv = bits(tlbdata,0,0);
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 555 unchanged lines hidden (view full) ---

564 /* @todo this could really use some profiling and fixing to make it faster! */
565 uint64_t tlbdata = tc->readMiscRegNoEffect(MISCREG_TLB_DATA);
566 Addr vaddr = req->getVaddr();
567 Addr size = req->getSize();
568 ASI asi;
569 asi = (ASI)req->getAsi();
570 bool implicit = false;
571 bool hpriv = bits(tlbdata,0,0);
572 bool unaligned = (vaddr & size-1);
572
573 DPRINTF(TLB, "TLB: DTB Request to translate va=%#x size=%d asi=%#x\n",
574 vaddr, size, asi);
575
576 if (lookupTable.size() != 64 - freeList.size())
577 panic("Lookup table size: %d tlb size: %d\n", lookupTable.size(),
578 freeList.size());
579 if (asi == ASI_IMPLICIT)
580 implicit = true;
581
573
574 DPRINTF(TLB, "TLB: DTB Request to translate va=%#x size=%d asi=%#x\n",
575 vaddr, size, asi);
576
577 if (lookupTable.size() != 64 - freeList.size())
578 panic("Lookup table size: %d tlb size: %d\n", lookupTable.size(),
579 freeList.size());
580 if (asi == ASI_IMPLICIT)
581 implicit = true;
582
582 if (hpriv && implicit) {
583 req->setPaddr(vaddr & PAddrImplMask);
584 return NoFault;
585 }
583 // Only use the fast path here if there doesn't need to be an unaligned
584 // trap later
585 if (!unaligned) {
586 if (hpriv && implicit) {
587 req->setPaddr(vaddr & PAddrImplMask);
588 return NoFault;
589 }
586
590
587 // Be fast if we can!
588 if (cacheValid && cacheState == tlbdata) {
591 // Be fast if we can!
592 if (cacheValid && cacheState == tlbdata) {
589
590
591
593
594
595
592 if (cacheEntry[0]) {
593 TlbEntry *ce = cacheEntry[0];
594 Addr ce_va = ce->range.va;
595 if (cacheAsi[0] == asi &&
596 ce_va < vaddr + size && ce_va + ce->range.size > vaddr &&
597 (!write || ce->pte.writable())) {
598 req->setPaddr(ce->pte.paddrMask() | vaddr & ce->pte.sizeMask());
599 if (ce->pte.sideffect() || (ce->pte.paddr() >> 39) & 1)
600 req->setFlags(req->getFlags() | UNCACHEABLE);
601 DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr());
602 return NoFault;
603 } // if matched
604 } // if cache entry valid
605 if (cacheEntry[1]) {
606 TlbEntry *ce = cacheEntry[1];
607 Addr ce_va = ce->range.va;
608 if (cacheAsi[1] == asi &&
609 ce_va < vaddr + size && ce_va + ce->range.size > vaddr &&
610 (!write || ce->pte.writable())) {
611 req->setPaddr(ce->pte.paddrMask() | vaddr & ce->pte.sizeMask());
612 if (ce->pte.sideffect() || (ce->pte.paddr() >> 39) & 1)
613 req->setFlags(req->getFlags() | UNCACHEABLE);
614 DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr());
615 return NoFault;
616 } // if matched
617 } // if cache entry valid
618 }
596 if (cacheEntry[0]) {
597 TlbEntry *ce = cacheEntry[0];
598 Addr ce_va = ce->range.va;
599 if (cacheAsi[0] == asi &&
600 ce_va < vaddr + size && ce_va + ce->range.size > vaddr &&
601 (!write || ce->pte.writable())) {
602 req->setPaddr(ce->pte.paddrMask() | vaddr & ce->pte.sizeMask());
603 if (ce->pte.sideffect() || (ce->pte.paddr() >> 39) & 1)
604 req->setFlags(req->getFlags() | UNCACHEABLE);
605 DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr());
606 return NoFault;
607 } // if matched
608 } // if cache entry valid
609 if (cacheEntry[1]) {
610 TlbEntry *ce = cacheEntry[1];
611 Addr ce_va = ce->range.va;
612 if (cacheAsi[1] == asi &&
613 ce_va < vaddr + size && ce_va + ce->range.size > vaddr &&
614 (!write || ce->pte.writable())) {
615 req->setPaddr(ce->pte.paddrMask() | vaddr & ce->pte.sizeMask());
616 if (ce->pte.sideffect() || (ce->pte.paddr() >> 39) & 1)
617 req->setFlags(req->getFlags() | UNCACHEABLE);
618 DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr());
619 return NoFault;
620 } // if matched
621 } // if cache entry valid
622 }
623 }
619
620 bool red = bits(tlbdata,1,1);
621 bool priv = bits(tlbdata,2,2);
622 bool addr_mask = bits(tlbdata,3,3);
623 bool lsu_dm = bits(tlbdata,5,5);
624
625 int part_id = bits(tlbdata,15,8);
626 int tl = bits(tlbdata,18,16);

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702 goto handleSparcErrorRegAccess;
703
704 if (!AsiIsReal(asi) && !AsiIsNucleus(asi) && !AsiIsAsIfUser(asi) &&
705 !AsiIsTwin(asi) && !AsiIsBlock(asi) && !AsiIsNoFault(asi))
706 panic("Accessing ASI %#X. Should we?\n", asi);
707 }
708
709 // If the asi is unaligned trap
624
625 bool red = bits(tlbdata,1,1);
626 bool priv = bits(tlbdata,2,2);
627 bool addr_mask = bits(tlbdata,3,3);
628 bool lsu_dm = bits(tlbdata,5,5);
629
630 int part_id = bits(tlbdata,15,8);
631 int tl = bits(tlbdata,18,16);

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707 goto handleSparcErrorRegAccess;
708
709 if (!AsiIsReal(asi) && !AsiIsNucleus(asi) && !AsiIsAsIfUser(asi) &&
710 !AsiIsTwin(asi) && !AsiIsBlock(asi) && !AsiIsNoFault(asi))
711 panic("Accessing ASI %#X. Should we?\n", asi);
712 }
713
714 // If the asi is unaligned trap
710 if (vaddr & size-1) {
715 if (unaligned) {
711 writeSfsr(vaddr, false, ct, false, OtherFault, asi);
712 return new MemAddressNotAligned;
713 }
714
715 if (addr_mask)
716 vaddr = vaddr & VAddrAMask;
717
718 if (!validVirtualAddress(vaddr, addr_mask)) {

--- 712 unchanged lines hidden --- 		716 writeSfsr(vaddr, false, ct, false, OtherFault, asi);
717 return new MemAddressNotAligned;
718 }
719
720 if (addr_mask)
721 vaddr = vaddr & VAddrAMask;
722
723 if (!validVirtualAddress(vaddr, addr_mask)) {

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