tlb.cc (4989:3e9d532cf998) | tlb.cc (4990:38d74405ddac) |
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1/* 2 * Copyright (c) 2001-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 46 unchanged lines hidden (view full) --- 55 if (size > 64) 56 fatal("SPARC T1 TLB registers don't support more than 64 TLB entries."); 57 58 tlb = new TlbEntry[size]; 59 std::memset(tlb, 0, sizeof(TlbEntry) * size); 60 61 for (int x = 0; x < size; x++) 62 freeList.push_back(&tlb[x]); | 1/* 2 * Copyright (c) 2001-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 46 unchanged lines hidden (view full) --- 55 if (size > 64) 56 fatal("SPARC T1 TLB registers don't support more than 64 TLB entries."); 57 58 tlb = new TlbEntry[size]; 59 std::memset(tlb, 0, sizeof(TlbEntry) * size); 60 61 for (int x = 0; x < size; x++) 62 freeList.push_back(&tlb[x]); |
63 64 c0_tsb_ps0 = 0; 65 c0_tsb_ps1 = 0; 66 c0_config = 0; 67 cx_tsb_ps0 = 0; 68 cx_tsb_ps1 = 0; 69 cx_config = 0; 70 sfsr = 0; 71 tag_access = 0; |
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63} 64 65void 66TLB::clearUsedBits() 67{ 68 MapIter i; 69 for (i = lookupTable.begin(); i != lookupTable.end(); i++) { 70 TlbEntry *t = i->second; --- 317 unchanged lines hidden (view full) --- 388 if (am) 389 return true; 390 if (va >= StartVAddrHole && va <= EndVAddrHole) 391 return false; 392 return true; 393} 394 395void | 72} 73 74void 75TLB::clearUsedBits() 76{ 77 MapIter i; 78 for (i = lookupTable.begin(); i != lookupTable.end(); i++) { 79 TlbEntry *t = i->second; --- 317 unchanged lines hidden (view full) --- 397 if (am) 398 return true; 399 if (va >= StartVAddrHole && va <= EndVAddrHole) 400 return false; 401 return true; 402} 403 404void |
396TLB::writeSfsr(ThreadContext *tc, int reg, bool write, ContextType ct, 397 bool se, FaultTypes ft, int asi) | 405TLB::writeSfsr(bool write, ContextType ct, bool se, FaultTypes ft, int asi) |
398{ | 406{ |
399 uint64_t sfsr; 400 sfsr = tc->readMiscRegNoEffect(reg); 401 | |
402 if (sfsr & 0x1) 403 sfsr = 0x3; 404 else 405 sfsr = 1; 406 407 if (write) 408 sfsr |= 1 << 2; 409 sfsr |= ct << 4; 410 if (se) 411 sfsr |= 1 << 6; 412 sfsr |= ft << 7; 413 sfsr |= asi << 16; | 407 if (sfsr & 0x1) 408 sfsr = 0x3; 409 else 410 sfsr = 1; 411 412 if (write) 413 sfsr |= 1 << 2; 414 sfsr |= ct << 4; 415 if (se) 416 sfsr |= 1 << 6; 417 sfsr |= ft << 7; 418 sfsr |= asi << 16; |
414 tc->setMiscReg(reg, sfsr); | |
415} 416 417void | 419} 420 421void |
418TLB::writeTagAccess(ThreadContext *tc, int reg, Addr va, int context) | 422TLB::writeTagAccess(Addr va, int context) |
419{ 420 DPRINTF(TLB, "TLB: Writing Tag Access: va: %#X ctx: %#X value: %#X\n", 421 va, context, mbits(va, 63,13) | mbits(context,12,0)); 422 | 423{ 424 DPRINTF(TLB, "TLB: Writing Tag Access: va: %#X ctx: %#X value: %#X\n", 425 va, context, mbits(va, 63,13) | mbits(context,12,0)); 426 |
423 tc->setMiscReg(reg, mbits(va, 63,13) | mbits(context,12,0)); | 427 tag_access = mbits(va, 63,13) | mbits(context,12,0); |
424} 425 426void | 428} 429 430void |
427ITB::writeSfsr(ThreadContext *tc, bool write, ContextType ct, 428 bool se, FaultTypes ft, int asi) | 431ITB::writeSfsr(bool write, ContextType ct, bool se, FaultTypes ft, int asi) |
429{ 430 DPRINTF(TLB, "TLB: ITB Fault: w=%d ct=%d ft=%d asi=%d\n", 431 (int)write, ct, ft, asi); | 432{ 433 DPRINTF(TLB, "TLB: ITB Fault: w=%d ct=%d ft=%d asi=%d\n", 434 (int)write, ct, ft, asi); |
432 TLB::writeSfsr(tc, MISCREG_MMU_ITLB_SFSR, write, ct, se, ft, asi); | 435 TLB::writeSfsr(write, ct, se, ft, asi); |
433} 434 435void | 436} 437 438void |
436ITB::writeTagAccess(ThreadContext *tc, Addr va, int context) 437{ 438 TLB::writeTagAccess(tc, MISCREG_MMU_ITLB_TAG_ACCESS, va, context); 439} 440 441void 442DTB::writeSfr(ThreadContext *tc, Addr a, bool write, ContextType ct, | 439DTB::writeSfsr(Addr a, bool write, ContextType ct, |
443 bool se, FaultTypes ft, int asi) 444{ 445 DPRINTF(TLB, "TLB: DTB Fault: A=%#x w=%d ct=%d ft=%d asi=%d\n", 446 a, (int)write, ct, ft, asi); | 440 bool se, FaultTypes ft, int asi) 441{ 442 DPRINTF(TLB, "TLB: DTB Fault: A=%#x w=%d ct=%d ft=%d asi=%d\n", 443 a, (int)write, ct, ft, asi); |
447 TLB::writeSfsr(tc, MISCREG_MMU_DTLB_SFSR, write, ct, se, ft, asi); 448 tc->setMiscReg(MISCREG_MMU_DTLB_SFAR, a); | 444 TLB::writeSfsr(write, ct, se, ft, asi); 445 sfar = a; |
449} 450 | 446} 447 |
451void 452DTB::writeTagAccess(ThreadContext *tc, Addr va, int context) 453{ 454 TLB::writeTagAccess(tc, MISCREG_MMU_DTLB_TAG_ACCESS, va, context); 455} 456 457 458 | |
459Fault 460ITB::translate(RequestPtr &req, ThreadContext *tc) 461{ 462 uint64_t tlbdata = tc->readMiscRegNoEffect(MISCREG_TLB_DATA); 463 464 Addr vaddr = req->getVaddr(); 465 TlbEntry *e; 466 --- 49 unchanged lines hidden (view full) --- 516 cacheState = tlbdata; 517 cacheEntry = NULL; 518 req->setPaddr(vaddr & PAddrImplMask); 519 return NoFault; 520 } 521 522 // If the access is unaligned trap 523 if (vaddr & 0x3) { | 448Fault 449ITB::translate(RequestPtr &req, ThreadContext *tc) 450{ 451 uint64_t tlbdata = tc->readMiscRegNoEffect(MISCREG_TLB_DATA); 452 453 Addr vaddr = req->getVaddr(); 454 TlbEntry *e; 455 --- 49 unchanged lines hidden (view full) --- 505 cacheState = tlbdata; 506 cacheEntry = NULL; 507 req->setPaddr(vaddr & PAddrImplMask); 508 return NoFault; 509 } 510 511 // If the access is unaligned trap 512 if (vaddr & 0x3) { |
524 writeSfsr(tc, false, ct, false, OtherFault, asi); | 513 writeSfsr(false, ct, false, OtherFault, asi); |
525 return new MemAddressNotAligned; 526 } 527 528 if (addr_mask) 529 vaddr = vaddr & VAddrAMask; 530 531 if (!validVirtualAddress(vaddr, addr_mask)) { | 514 return new MemAddressNotAligned; 515 } 516 517 if (addr_mask) 518 vaddr = vaddr & VAddrAMask; 519 520 if (!validVirtualAddress(vaddr, addr_mask)) { |
532 writeSfsr(tc, false, ct, false, VaOutOfRange, asi); | 521 writeSfsr(false, ct, false, VaOutOfRange, asi); |
533 return new InstructionAccessException; 534 } 535 536 if (!lsu_im) { 537 e = lookup(vaddr, part_id, true); 538 real = true; 539 context = 0; 540 } else { 541 e = lookup(vaddr, part_id, false, context); 542 } 543 544 if (e == NULL || !e->valid) { | 522 return new InstructionAccessException; 523 } 524 525 if (!lsu_im) { 526 e = lookup(vaddr, part_id, true); 527 real = true; 528 context = 0; 529 } else { 530 e = lookup(vaddr, part_id, false, context); 531 } 532 533 if (e == NULL || !e->valid) { |
545 writeTagAccess(tc, vaddr, context); | 534 writeTagAccess(vaddr, context); |
546 if (real) 547 return new InstructionRealTranslationMiss; 548 else 549 return new FastInstructionAccessMMUMiss; 550 } 551 552 // were not priviledged accesing priv page 553 if (!priv && e->pte.priv()) { | 535 if (real) 536 return new InstructionRealTranslationMiss; 537 else 538 return new FastInstructionAccessMMUMiss; 539 } 540 541 // were not priviledged accesing priv page 542 if (!priv && e->pte.priv()) { |
554 writeTagAccess(tc, vaddr, context); 555 writeSfsr(tc, false, ct, false, PrivViolation, asi); | 543 writeTagAccess(vaddr, context); 544 writeSfsr(false, ct, false, PrivViolation, asi); |
556 return new InstructionAccessException; 557 } 558 559 // cache translation date for next translation 560 cacheValid = true; 561 cacheState = tlbdata; 562 cacheEntry = e; 563 --- 92 unchanged lines hidden (view full) --- 656 asi = ASI_P; 657 ct = Primary; 658 context = pri_context; 659 } 660 } else { 661 // We need to check for priv level/asi priv 662 if (!priv && !hpriv && !AsiIsUnPriv(asi)) { 663 // It appears that context should be Nucleus in these cases? | 545 return new InstructionAccessException; 546 } 547 548 // cache translation date for next translation 549 cacheValid = true; 550 cacheState = tlbdata; 551 cacheEntry = e; 552 --- 92 unchanged lines hidden (view full) --- 645 asi = ASI_P; 646 ct = Primary; 647 context = pri_context; 648 } 649 } else { 650 // We need to check for priv level/asi priv 651 if (!priv && !hpriv && !AsiIsUnPriv(asi)) { 652 // It appears that context should be Nucleus in these cases? |
664 writeSfr(tc, vaddr, write, Nucleus, false, IllegalAsi, asi); | 653 writeSfsr(vaddr, write, Nucleus, false, IllegalAsi, asi); |
665 return new PrivilegedAction; 666 } 667 668 if (!hpriv && AsiIsHPriv(asi)) { | 654 return new PrivilegedAction; 655 } 656 657 if (!hpriv && AsiIsHPriv(asi)) { |
669 writeSfr(tc, vaddr, write, Nucleus, false, IllegalAsi, asi); | 658 writeSfsr(vaddr, write, Nucleus, false, IllegalAsi, asi); |
670 return new DataAccessException; 671 } 672 673 if (AsiIsPrimary(asi)) { 674 context = pri_context; 675 ct = Primary; 676 } else if (AsiIsSecondary(asi)) { 677 context = sec_context; --- 36 unchanged lines hidden (view full) --- 714 715 if (!AsiIsReal(asi) && !AsiIsNucleus(asi) && !AsiIsAsIfUser(asi) && 716 !AsiIsTwin(asi) && !AsiIsBlock(asi) && !AsiIsNoFault(asi)) 717 panic("Accessing ASI %#X. Should we?\n", asi); 718 } 719 720 // If the asi is unaligned trap 721 if (vaddr & size-1) { | 659 return new DataAccessException; 660 } 661 662 if (AsiIsPrimary(asi)) { 663 context = pri_context; 664 ct = Primary; 665 } else if (AsiIsSecondary(asi)) { 666 context = sec_context; --- 36 unchanged lines hidden (view full) --- 703 704 if (!AsiIsReal(asi) && !AsiIsNucleus(asi) && !AsiIsAsIfUser(asi) && 705 !AsiIsTwin(asi) && !AsiIsBlock(asi) && !AsiIsNoFault(asi)) 706 panic("Accessing ASI %#X. Should we?\n", asi); 707 } 708 709 // If the asi is unaligned trap 710 if (vaddr & size-1) { |
722 writeSfr(tc, vaddr, false, ct, false, OtherFault, asi); | 711 writeSfsr(vaddr, false, ct, false, OtherFault, asi); |
723 return new MemAddressNotAligned; 724 } 725 726 if (addr_mask) 727 vaddr = vaddr & VAddrAMask; 728 729 if (!validVirtualAddress(vaddr, addr_mask)) { | 712 return new MemAddressNotAligned; 713 } 714 715 if (addr_mask) 716 vaddr = vaddr & VAddrAMask; 717 718 if (!validVirtualAddress(vaddr, addr_mask)) { |
730 writeSfr(tc, vaddr, false, ct, true, VaOutOfRange, asi); | 719 writeSfsr(vaddr, false, ct, true, VaOutOfRange, asi); |
731 return new DataAccessException; 732 } 733 734 735 if ((!lsu_dm && !hpriv && !red) || AsiIsReal(asi)) { 736 real = true; 737 context = 0; 738 }; 739 740 if (hpriv && (implicit || (!AsiIsAsIfUser(asi) && !AsiIsReal(asi)))) { 741 req->setPaddr(vaddr & PAddrImplMask); 742 return NoFault; 743 } 744 745 e = lookup(vaddr, part_id, real, context); 746 747 if (e == NULL || !e->valid) { | 720 return new DataAccessException; 721 } 722 723 724 if ((!lsu_dm && !hpriv && !red) || AsiIsReal(asi)) { 725 real = true; 726 context = 0; 727 }; 728 729 if (hpriv && (implicit || (!AsiIsAsIfUser(asi) && !AsiIsReal(asi)))) { 730 req->setPaddr(vaddr & PAddrImplMask); 731 return NoFault; 732 } 733 734 e = lookup(vaddr, part_id, real, context); 735 736 if (e == NULL || !e->valid) { |
748 writeTagAccess(tc, vaddr, context); | 737 writeTagAccess(vaddr, context); |
749 DPRINTF(TLB, "TLB: DTB Failed to find matching TLB entry\n"); 750 if (real) 751 return new DataRealTranslationMiss; 752 else 753 return new FastDataAccessMMUMiss; 754 755 } 756 757 if (!priv && e->pte.priv()) { | 738 DPRINTF(TLB, "TLB: DTB Failed to find matching TLB entry\n"); 739 if (real) 740 return new DataRealTranslationMiss; 741 else 742 return new FastDataAccessMMUMiss; 743 744 } 745 746 if (!priv && e->pte.priv()) { |
758 writeTagAccess(tc, vaddr, context); 759 writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), PrivViolation, asi); | 747 writeTagAccess(vaddr, context); 748 writeSfsr(vaddr, write, ct, e->pte.sideffect(), PrivViolation, asi); |
760 return new DataAccessException; 761 } 762 763 if (write && !e->pte.writable()) { | 749 return new DataAccessException; 750 } 751 752 if (write && !e->pte.writable()) { |
764 writeTagAccess(tc, vaddr, context); 765 writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), OtherFault, asi); | 753 writeTagAccess(vaddr, context); 754 writeSfsr(vaddr, write, ct, e->pte.sideffect(), OtherFault, asi); |
766 return new FastDataAccessProtection; 767 } 768 769 if (e->pte.nofault() && !AsiIsNoFault(asi)) { | 755 return new FastDataAccessProtection; 756 } 757 758 if (e->pte.nofault() && !AsiIsNoFault(asi)) { |
770 writeTagAccess(tc, vaddr, context); 771 writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), LoadFromNfo, asi); | 759 writeTagAccess(vaddr, context); 760 writeSfsr(vaddr, write, ct, e->pte.sideffect(), LoadFromNfo, asi); |
772 return new DataAccessException; 773 } 774 775 if (e->pte.sideffect() && AsiIsNoFault(asi)) { | 761 return new DataAccessException; 762 } 763 764 if (e->pte.sideffect() && AsiIsNoFault(asi)) { |
776 writeTagAccess(tc, vaddr, context); 777 writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), SideEffect, asi); | 765 writeTagAccess(vaddr, context); 766 writeSfsr(vaddr, write, ct, e->pte.sideffect(), SideEffect, asi); |
778 return new DataAccessException; 779 } 780 781 782 if (e->pte.sideffect() || (e->pte.paddr() >> 39) & 1) 783 req->setFlags(req->getFlags() | UNCACHEABLE); 784 785 // cache translation date for next translation --- 15 unchanged lines hidden (view full) --- 801 req->setPaddr(e->pte.paddr() & ~(e->pte.size()-1) | 802 vaddr & e->pte.size()-1); 803 DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr()); 804 return NoFault; 805 806 /** Normal flow ends here. */ 807handleIntRegAccess: 808 if (!hpriv) { | 767 return new DataAccessException; 768 } 769 770 771 if (e->pte.sideffect() || (e->pte.paddr() >> 39) & 1) 772 req->setFlags(req->getFlags() | UNCACHEABLE); 773 774 // cache translation date for next translation --- 15 unchanged lines hidden (view full) --- 790 req->setPaddr(e->pte.paddr() & ~(e->pte.size()-1) | 791 vaddr & e->pte.size()-1); 792 DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr()); 793 return NoFault; 794 795 /** Normal flow ends here. */ 796handleIntRegAccess: 797 if (!hpriv) { |
809 writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi); | 798 writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi); |
810 if (priv) 811 return new DataAccessException; 812 else 813 return new PrivilegedAction; 814 } 815 816 if (asi == ASI_SWVR_UDB_INTR_W && !write || 817 asi == ASI_SWVR_UDB_INTR_R && write) { | 799 if (priv) 800 return new DataAccessException; 801 else 802 return new PrivilegedAction; 803 } 804 805 if (asi == ASI_SWVR_UDB_INTR_W && !write || 806 asi == ASI_SWVR_UDB_INTR_R && write) { |
818 writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi); | 807 writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi); |
819 return new DataAccessException; 820 } 821 822 goto regAccessOk; 823 824 825handleScratchRegAccess: 826 if (vaddr > 0x38 || (vaddr >= 0x20 && vaddr < 0x30 && !hpriv)) { | 808 return new DataAccessException; 809 } 810 811 goto regAccessOk; 812 813 814handleScratchRegAccess: 815 if (vaddr > 0x38 || (vaddr >= 0x20 && vaddr < 0x30 && !hpriv)) { |
827 writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi); | 816 writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi); |
828 return new DataAccessException; 829 } 830 goto regAccessOk; 831 832handleQueueRegAccess: 833 if (!priv && !hpriv) { | 817 return new DataAccessException; 818 } 819 goto regAccessOk; 820 821handleQueueRegAccess: 822 if (!priv && !hpriv) { |
834 writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi); | 823 writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi); |
835 return new PrivilegedAction; 836 } 837 if (!hpriv && vaddr & 0xF || vaddr > 0x3f8 || vaddr < 0x3c0) { | 824 return new PrivilegedAction; 825 } 826 if (!hpriv && vaddr & 0xF || vaddr > 0x3f8 || vaddr < 0x3c0) { |
838 writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi); | 827 writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi); |
839 return new DataAccessException; 840 } 841 goto regAccessOk; 842 843handleSparcErrorRegAccess: 844 if (!hpriv) { | 828 return new DataAccessException; 829 } 830 goto regAccessOk; 831 832handleSparcErrorRegAccess: 833 if (!hpriv) { |
845 writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi); | 834 writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi); |
846 if (priv) 847 return new DataAccessException; 848 else 849 return new PrivilegedAction; 850 } 851 goto regAccessOk; 852 853 --- 10 unchanged lines hidden (view full) --- 864{ 865 Addr va = pkt->getAddr(); 866 ASI asi = (ASI)pkt->req->getAsi(); 867 uint64_t temp; 868 869 DPRINTF(IPR, "Memory Mapped IPR Read: asi=%#X a=%#x\n", 870 (uint32_t)pkt->req->getAsi(), pkt->getAddr()); 871 | 835 if (priv) 836 return new DataAccessException; 837 else 838 return new PrivilegedAction; 839 } 840 goto regAccessOk; 841 842 --- 10 unchanged lines hidden (view full) --- 853{ 854 Addr va = pkt->getAddr(); 855 ASI asi = (ASI)pkt->req->getAsi(); 856 uint64_t temp; 857 858 DPRINTF(IPR, "Memory Mapped IPR Read: asi=%#X a=%#x\n", 859 (uint32_t)pkt->req->getAsi(), pkt->getAddr()); 860 |
861 ITB * itb = tc->getITBPtr(); 862 |
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872 switch (asi) { 873 case ASI_LSU_CONTROL_REG: 874 assert(va == 0); 875 pkt->set(tc->readMiscReg(MISCREG_MMU_LSU_CTRL)); 876 break; 877 case ASI_MMU: 878 switch (va) { 879 case 0x8: --- 7 unchanged lines hidden (view full) --- 887 } 888 break; 889 case ASI_QUEUE: 890 pkt->set(tc->readMiscReg(MISCREG_QUEUE_CPU_MONDO_HEAD + 891 (va >> 4) - 0x3c)); 892 break; 893 case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0: 894 assert(va == 0); | 863 switch (asi) { 864 case ASI_LSU_CONTROL_REG: 865 assert(va == 0); 866 pkt->set(tc->readMiscReg(MISCREG_MMU_LSU_CTRL)); 867 break; 868 case ASI_MMU: 869 switch (va) { 870 case 0x8: --- 7 unchanged lines hidden (view full) --- 878 } 879 break; 880 case ASI_QUEUE: 881 pkt->set(tc->readMiscReg(MISCREG_QUEUE_CPU_MONDO_HEAD + 882 (va >> 4) - 0x3c)); 883 break; 884 case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0: 885 assert(va == 0); |
895 pkt->set(tc->readMiscReg(MISCREG_MMU_DTLB_C0_TSB_PS0)); | 886 pkt->set(c0_tsb_ps0); |
896 break; 897 case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1: 898 assert(va == 0); | 887 break; 888 case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1: 889 assert(va == 0); |
899 pkt->set(tc->readMiscReg(MISCREG_MMU_DTLB_C0_TSB_PS1)); | 890 pkt->set(c0_tsb_ps1); |
900 break; 901 case ASI_DMMU_CTXT_ZERO_CONFIG: 902 assert(va == 0); | 891 break; 892 case ASI_DMMU_CTXT_ZERO_CONFIG: 893 assert(va == 0); |
903 pkt->set(tc->readMiscReg(MISCREG_MMU_DTLB_C0_CONFIG)); | 894 pkt->set(c0_config); |
904 break; 905 case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0: 906 assert(va == 0); | 895 break; 896 case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0: 897 assert(va == 0); |
907 pkt->set(tc->readMiscReg(MISCREG_MMU_ITLB_C0_TSB_PS0)); | 898 pkt->set(itb->c0_tsb_ps0); |
908 break; 909 case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1: 910 assert(va == 0); | 899 break; 900 case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1: 901 assert(va == 0); |
911 pkt->set(tc->readMiscReg(MISCREG_MMU_ITLB_C0_TSB_PS1)); | 902 pkt->set(itb->c0_tsb_ps1); |
912 break; 913 case ASI_IMMU_CTXT_ZERO_CONFIG: 914 assert(va == 0); | 903 break; 904 case ASI_IMMU_CTXT_ZERO_CONFIG: 905 assert(va == 0); |
915 pkt->set(tc->readMiscReg(MISCREG_MMU_ITLB_C0_CONFIG)); | 906 pkt->set(itb->c0_config); |
916 break; 917 case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0: 918 assert(va == 0); | 907 break; 908 case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0: 909 assert(va == 0); |
919 pkt->set(tc->readMiscReg(MISCREG_MMU_DTLB_CX_TSB_PS0)); | 910 pkt->set(cx_tsb_ps0); |
920 break; 921 case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1: 922 assert(va == 0); | 911 break; 912 case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1: 913 assert(va == 0); |
923 pkt->set(tc->readMiscReg(MISCREG_MMU_DTLB_CX_TSB_PS1)); | 914 pkt->set(cx_tsb_ps1); |
924 break; 925 case ASI_DMMU_CTXT_NONZERO_CONFIG: 926 assert(va == 0); | 915 break; 916 case ASI_DMMU_CTXT_NONZERO_CONFIG: 917 assert(va == 0); |
927 pkt->set(tc->readMiscReg(MISCREG_MMU_DTLB_CX_CONFIG)); | 918 pkt->set(cx_config); |
928 break; 929 case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0: 930 assert(va == 0); | 919 break; 920 case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0: 921 assert(va == 0); |
931 pkt->set(tc->readMiscReg(MISCREG_MMU_ITLB_CX_TSB_PS0)); | 922 pkt->set(itb->cx_tsb_ps0); |
932 break; 933 case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1: 934 assert(va == 0); | 923 break; 924 case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1: 925 assert(va == 0); |
935 pkt->set(tc->readMiscReg(MISCREG_MMU_ITLB_CX_TSB_PS1)); | 926 pkt->set(itb->cx_tsb_ps1); |
936 break; 937 case ASI_IMMU_CTXT_NONZERO_CONFIG: 938 assert(va == 0); | 927 break; 928 case ASI_IMMU_CTXT_NONZERO_CONFIG: 929 assert(va == 0); |
939 pkt->set(tc->readMiscReg(MISCREG_MMU_ITLB_CX_CONFIG)); | 930 pkt->set(itb->cx_config); |
940 break; 941 case ASI_SPARC_ERROR_STATUS_REG: 942 pkt->set((uint64_t)0); 943 break; 944 case ASI_HYP_SCRATCHPAD: 945 case ASI_SCRATCHPAD: 946 pkt->set(tc->readMiscReg(MISCREG_SCRATCHPAD_R0 + (va >> 3))); 947 break; 948 case ASI_IMMU: 949 switch (va) { 950 case 0x0: | 931 break; 932 case ASI_SPARC_ERROR_STATUS_REG: 933 pkt->set((uint64_t)0); 934 break; 935 case ASI_HYP_SCRATCHPAD: 936 case ASI_SCRATCHPAD: 937 pkt->set(tc->readMiscReg(MISCREG_SCRATCHPAD_R0 + (va >> 3))); 938 break; 939 case ASI_IMMU: 940 switch (va) { 941 case 0x0: |
951 temp = tc->readMiscReg(MISCREG_MMU_ITLB_TAG_ACCESS); | 942 temp = itb->tag_access; |
952 pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48); 953 break; 954 case 0x18: | 943 pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48); 944 break; 945 case 0x18: |
955 pkt->set(tc->readMiscReg(MISCREG_MMU_ITLB_SFSR)); | 946 pkt->set(itb->sfsr); |
956 break; 957 case 0x30: | 947 break; 948 case 0x30: |
958 pkt->set(tc->readMiscReg(MISCREG_MMU_ITLB_TAG_ACCESS)); | 949 pkt->set(itb->tag_access); |
959 break; 960 default: 961 goto doMmuReadError; 962 } 963 break; 964 case ASI_DMMU: 965 switch (va) { 966 case 0x0: | 950 break; 951 default: 952 goto doMmuReadError; 953 } 954 break; 955 case ASI_DMMU: 956 switch (va) { 957 case 0x0: |
967 temp = tc->readMiscReg(MISCREG_MMU_DTLB_TAG_ACCESS); | 958 temp = tag_access; |
968 pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48); 969 break; 970 case 0x18: | 959 pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48); 960 break; 961 case 0x18: |
971 pkt->set(tc->readMiscReg(MISCREG_MMU_DTLB_SFSR)); | 962 pkt->set(sfsr); |
972 break; 973 case 0x20: | 963 break; 964 case 0x20: |
974 pkt->set(tc->readMiscReg(MISCREG_MMU_DTLB_SFAR)); | 965 pkt->set(sfar); |
975 break; 976 case 0x30: | 966 break; 967 case 0x30: |
977 pkt->set(tc->readMiscReg(MISCREG_MMU_DTLB_TAG_ACCESS)); | 968 pkt->set(tag_access); |
978 break; 979 case 0x80: 980 pkt->set(tc->readMiscReg(MISCREG_MMU_PART_ID)); 981 break; 982 default: 983 goto doMmuReadError; 984 } 985 break; 986 case ASI_DMMU_TSB_PS0_PTR_REG: 987 pkt->set(MakeTsbPtr(Ps0, | 969 break; 970 case 0x80: 971 pkt->set(tc->readMiscReg(MISCREG_MMU_PART_ID)); 972 break; 973 default: 974 goto doMmuReadError; 975 } 976 break; 977 case ASI_DMMU_TSB_PS0_PTR_REG: 978 pkt->set(MakeTsbPtr(Ps0, |
988 tc->readMiscReg(MISCREG_MMU_DTLB_TAG_ACCESS), 989 tc->readMiscReg(MISCREG_MMU_DTLB_C0_TSB_PS0), 990 tc->readMiscReg(MISCREG_MMU_DTLB_C0_CONFIG), 991 tc->readMiscReg(MISCREG_MMU_DTLB_CX_TSB_PS0), 992 tc->readMiscReg(MISCREG_MMU_DTLB_CX_CONFIG))); | 979 tag_access, 980 c0_tsb_ps0, 981 c0_config, 982 cx_tsb_ps0, 983 cx_config)); |
993 break; 994 case ASI_DMMU_TSB_PS1_PTR_REG: 995 pkt->set(MakeTsbPtr(Ps1, | 984 break; 985 case ASI_DMMU_TSB_PS1_PTR_REG: 986 pkt->set(MakeTsbPtr(Ps1, |
996 tc->readMiscReg(MISCREG_MMU_DTLB_TAG_ACCESS), 997 tc->readMiscReg(MISCREG_MMU_DTLB_C0_TSB_PS1), 998 tc->readMiscReg(MISCREG_MMU_DTLB_C0_CONFIG), 999 tc->readMiscReg(MISCREG_MMU_DTLB_CX_TSB_PS1), 1000 tc->readMiscReg(MISCREG_MMU_DTLB_CX_CONFIG))); | 987 tag_access, 988 c0_tsb_ps1, 989 c0_config, 990 cx_tsb_ps1, 991 cx_config)); |
1001 break; 1002 case ASI_IMMU_TSB_PS0_PTR_REG: 1003 pkt->set(MakeTsbPtr(Ps0, | 992 break; 993 case ASI_IMMU_TSB_PS0_PTR_REG: 994 pkt->set(MakeTsbPtr(Ps0, |
1004 tc->readMiscReg(MISCREG_MMU_ITLB_TAG_ACCESS), 1005 tc->readMiscReg(MISCREG_MMU_ITLB_C0_TSB_PS0), 1006 tc->readMiscReg(MISCREG_MMU_ITLB_C0_CONFIG), 1007 tc->readMiscReg(MISCREG_MMU_ITLB_CX_TSB_PS0), 1008 tc->readMiscReg(MISCREG_MMU_ITLB_CX_CONFIG))); | 995 itb->tag_access, 996 itb->c0_tsb_ps0, 997 itb->c0_config, 998 itb->cx_tsb_ps0, 999 itb->cx_config)); |
1009 break; 1010 case ASI_IMMU_TSB_PS1_PTR_REG: 1011 pkt->set(MakeTsbPtr(Ps1, | 1000 break; 1001 case ASI_IMMU_TSB_PS1_PTR_REG: 1002 pkt->set(MakeTsbPtr(Ps1, |
1012 tc->readMiscReg(MISCREG_MMU_ITLB_TAG_ACCESS), 1013 tc->readMiscReg(MISCREG_MMU_ITLB_C0_TSB_PS1), 1014 tc->readMiscReg(MISCREG_MMU_ITLB_C0_CONFIG), 1015 tc->readMiscReg(MISCREG_MMU_ITLB_CX_TSB_PS1), 1016 tc->readMiscReg(MISCREG_MMU_ITLB_CX_CONFIG))); | 1003 itb->tag_access, 1004 itb->c0_tsb_ps1, 1005 itb->c0_config, 1006 itb->cx_tsb_ps1, 1007 itb->cx_config)); |
1017 break; 1018 case ASI_SWVR_INTR_RECEIVE: 1019 pkt->set(tc->getCpuPtr()->get_interrupts(IT_INT_VEC)); 1020 break; 1021 case ASI_SWVR_UDB_INTR_R: 1022 temp = findMsbSet(tc->getCpuPtr()->get_interrupts(IT_INT_VEC)); 1023 tc->getCpuPtr()->clear_interrupt(IT_INT_VEC, temp); 1024 pkt->set(temp); --- 23 unchanged lines hidden (view full) --- 1048 bool ignore; 1049 int part_id; 1050 int ctx_id; 1051 PageTableEntry pte; 1052 1053 DPRINTF(IPR, "Memory Mapped IPR Write: asi=%#X a=%#x d=%#X\n", 1054 (uint32_t)asi, va, data); 1055 | 1008 break; 1009 case ASI_SWVR_INTR_RECEIVE: 1010 pkt->set(tc->getCpuPtr()->get_interrupts(IT_INT_VEC)); 1011 break; 1012 case ASI_SWVR_UDB_INTR_R: 1013 temp = findMsbSet(tc->getCpuPtr()->get_interrupts(IT_INT_VEC)); 1014 tc->getCpuPtr()->clear_interrupt(IT_INT_VEC, temp); 1015 pkt->set(temp); --- 23 unchanged lines hidden (view full) --- 1039 bool ignore; 1040 int part_id; 1041 int ctx_id; 1042 PageTableEntry pte; 1043 1044 DPRINTF(IPR, "Memory Mapped IPR Write: asi=%#X a=%#x d=%#X\n", 1045 (uint32_t)asi, va, data); 1046 |
1047 ITB * itb = tc->getITBPtr(); 1048 |
|
1056 switch (asi) { 1057 case ASI_LSU_CONTROL_REG: 1058 assert(va == 0); 1059 tc->setMiscReg(MISCREG_MMU_LSU_CTRL, data); 1060 break; 1061 case ASI_MMU: 1062 switch (va) { 1063 case 0x8: --- 8 unchanged lines hidden (view full) --- 1072 break; 1073 case ASI_QUEUE: 1074 assert(mbits(data,13,6) == data); 1075 tc->setMiscReg(MISCREG_QUEUE_CPU_MONDO_HEAD + 1076 (va >> 4) - 0x3c, data); 1077 break; 1078 case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0: 1079 assert(va == 0); | 1049 switch (asi) { 1050 case ASI_LSU_CONTROL_REG: 1051 assert(va == 0); 1052 tc->setMiscReg(MISCREG_MMU_LSU_CTRL, data); 1053 break; 1054 case ASI_MMU: 1055 switch (va) { 1056 case 0x8: --- 8 unchanged lines hidden (view full) --- 1065 break; 1066 case ASI_QUEUE: 1067 assert(mbits(data,13,6) == data); 1068 tc->setMiscReg(MISCREG_QUEUE_CPU_MONDO_HEAD + 1069 (va >> 4) - 0x3c, data); 1070 break; 1071 case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0: 1072 assert(va == 0); |
1080 tc->setMiscReg(MISCREG_MMU_DTLB_C0_TSB_PS0, data); | 1073 c0_tsb_ps0 = data; |
1081 break; 1082 case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1: 1083 assert(va == 0); | 1074 break; 1075 case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1: 1076 assert(va == 0); |
1084 tc->setMiscReg(MISCREG_MMU_DTLB_C0_TSB_PS1, data); | 1077 c0_tsb_ps1 = data; |
1085 break; 1086 case ASI_DMMU_CTXT_ZERO_CONFIG: 1087 assert(va == 0); | 1078 break; 1079 case ASI_DMMU_CTXT_ZERO_CONFIG: 1080 assert(va == 0); |
1088 tc->setMiscReg(MISCREG_MMU_DTLB_C0_CONFIG, data); | 1081 c0_config = data; |
1089 break; 1090 case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0: 1091 assert(va == 0); | 1082 break; 1083 case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0: 1084 assert(va == 0); |
1092 tc->setMiscReg(MISCREG_MMU_ITLB_C0_TSB_PS0, data); | 1085 itb->c0_tsb_ps0 = data; |
1093 break; 1094 case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1: 1095 assert(va == 0); | 1086 break; 1087 case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1: 1088 assert(va == 0); |
1096 tc->setMiscReg(MISCREG_MMU_ITLB_C0_TSB_PS1, data); | 1089 itb->c0_tsb_ps1 = data; |
1097 break; 1098 case ASI_IMMU_CTXT_ZERO_CONFIG: 1099 assert(va == 0); | 1090 break; 1091 case ASI_IMMU_CTXT_ZERO_CONFIG: 1092 assert(va == 0); |
1100 tc->setMiscReg(MISCREG_MMU_ITLB_C0_CONFIG, data); | 1093 itb->c0_config = data; |
1101 break; 1102 case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0: 1103 assert(va == 0); | 1094 break; 1095 case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0: 1096 assert(va == 0); |
1104 tc->setMiscReg(MISCREG_MMU_DTLB_CX_TSB_PS0, data); | 1097 cx_tsb_ps0 = data; |
1105 break; 1106 case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1: 1107 assert(va == 0); | 1098 break; 1099 case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1: 1100 assert(va == 0); |
1108 tc->setMiscReg(MISCREG_MMU_DTLB_CX_TSB_PS1, data); | 1101 cx_tsb_ps1 = data; |
1109 break; 1110 case ASI_DMMU_CTXT_NONZERO_CONFIG: 1111 assert(va == 0); | 1102 break; 1103 case ASI_DMMU_CTXT_NONZERO_CONFIG: 1104 assert(va == 0); |
1112 tc->setMiscReg(MISCREG_MMU_DTLB_CX_CONFIG, data); | 1105 cx_config = data; |
1113 break; 1114 case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0: 1115 assert(va == 0); | 1106 break; 1107 case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0: 1108 assert(va == 0); |
1116 tc->setMiscReg(MISCREG_MMU_ITLB_CX_TSB_PS0, data); | 1109 itb->cx_tsb_ps0 = data; |
1117 break; 1118 case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1: 1119 assert(va == 0); | 1110 break; 1111 case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1: 1112 assert(va == 0); |
1120 tc->setMiscReg(MISCREG_MMU_ITLB_CX_TSB_PS1, data); | 1113 itb->cx_tsb_ps1 = data; |
1121 break; 1122 case ASI_IMMU_CTXT_NONZERO_CONFIG: 1123 assert(va == 0); | 1114 break; 1115 case ASI_IMMU_CTXT_NONZERO_CONFIG: 1116 assert(va == 0); |
1124 tc->setMiscReg(MISCREG_MMU_ITLB_CX_CONFIG, data); | 1117 itb->cx_config = data; |
1125 break; 1126 case ASI_SPARC_ERROR_EN_REG: 1127 case ASI_SPARC_ERROR_STATUS_REG: 1128 warn("Ignoring write to SPARC ERROR regsiter\n"); 1129 break; 1130 case ASI_HYP_SCRATCHPAD: 1131 case ASI_SCRATCHPAD: 1132 tc->setMiscReg(MISCREG_SCRATCHPAD_R0 + (va >> 3), data); 1133 break; 1134 case ASI_IMMU: 1135 switch (va) { 1136 case 0x18: | 1118 break; 1119 case ASI_SPARC_ERROR_EN_REG: 1120 case ASI_SPARC_ERROR_STATUS_REG: 1121 warn("Ignoring write to SPARC ERROR regsiter\n"); 1122 break; 1123 case ASI_HYP_SCRATCHPAD: 1124 case ASI_SCRATCHPAD: 1125 tc->setMiscReg(MISCREG_SCRATCHPAD_R0 + (va >> 3), data); 1126 break; 1127 case ASI_IMMU: 1128 switch (va) { 1129 case 0x18: |
1137 tc->setMiscReg(MISCREG_MMU_ITLB_SFSR, data); | 1130 itb->sfsr = data; |
1138 break; 1139 case 0x30: 1140 sext<59>(bits(data, 59,0)); | 1131 break; 1132 case 0x30: 1133 sext<59>(bits(data, 59,0)); |
1141 tc->setMiscReg(MISCREG_MMU_ITLB_TAG_ACCESS, data); | 1134 itb->tag_access = data; |
1142 break; 1143 default: 1144 goto doMmuWriteError; 1145 } 1146 break; 1147 case ASI_ITLB_DATA_ACCESS_REG: 1148 entry_insert = bits(va, 8,3); 1149 case ASI_ITLB_DATA_IN_REG: 1150 assert(entry_insert != -1 || mbits(va,10,9) == va); | 1135 break; 1136 default: 1137 goto doMmuWriteError; 1138 } 1139 break; 1140 case ASI_ITLB_DATA_ACCESS_REG: 1141 entry_insert = bits(va, 8,3); 1142 case ASI_ITLB_DATA_IN_REG: 1143 assert(entry_insert != -1 || mbits(va,10,9) == va); |
1151 ta_insert = tc->readMiscReg(MISCREG_MMU_ITLB_TAG_ACCESS); | 1144 ta_insert = itb->tag_access; |
1152 va_insert = mbits(ta_insert, 63,13); 1153 ct_insert = mbits(ta_insert, 12,0); 1154 part_insert = tc->readMiscReg(MISCREG_MMU_PART_ID); 1155 real_insert = bits(va, 9,9); 1156 pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v : 1157 PageTableEntry::sun4u); 1158 tc->getITBPtr()->insert(va_insert, part_insert, ct_insert, real_insert, 1159 pte, entry_insert); 1160 break; 1161 case ASI_DTLB_DATA_ACCESS_REG: 1162 entry_insert = bits(va, 8,3); 1163 case ASI_DTLB_DATA_IN_REG: 1164 assert(entry_insert != -1 || mbits(va,10,9) == va); | 1145 va_insert = mbits(ta_insert, 63,13); 1146 ct_insert = mbits(ta_insert, 12,0); 1147 part_insert = tc->readMiscReg(MISCREG_MMU_PART_ID); 1148 real_insert = bits(va, 9,9); 1149 pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v : 1150 PageTableEntry::sun4u); 1151 tc->getITBPtr()->insert(va_insert, part_insert, ct_insert, real_insert, 1152 pte, entry_insert); 1153 break; 1154 case ASI_DTLB_DATA_ACCESS_REG: 1155 entry_insert = bits(va, 8,3); 1156 case ASI_DTLB_DATA_IN_REG: 1157 assert(entry_insert != -1 || mbits(va,10,9) == va); |
1165 ta_insert = tc->readMiscReg(MISCREG_MMU_DTLB_TAG_ACCESS); | 1158 ta_insert = tag_access; |
1166 va_insert = mbits(ta_insert, 63,13); 1167 ct_insert = mbits(ta_insert, 12,0); 1168 part_insert = tc->readMiscReg(MISCREG_MMU_PART_ID); 1169 real_insert = bits(va, 9,9); 1170 pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v : 1171 PageTableEntry::sun4u); 1172 insert(va_insert, part_insert, ct_insert, real_insert, pte, entry_insert); 1173 break; --- 30 unchanged lines hidden (view full) --- 1204 break; 1205 default: 1206 panic("Invalid type for IMMU demap\n"); 1207 } 1208 break; 1209 case ASI_DMMU: 1210 switch (va) { 1211 case 0x18: | 1159 va_insert = mbits(ta_insert, 63,13); 1160 ct_insert = mbits(ta_insert, 12,0); 1161 part_insert = tc->readMiscReg(MISCREG_MMU_PART_ID); 1162 real_insert = bits(va, 9,9); 1163 pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v : 1164 PageTableEntry::sun4u); 1165 insert(va_insert, part_insert, ct_insert, real_insert, pte, entry_insert); 1166 break; --- 30 unchanged lines hidden (view full) --- 1197 break; 1198 default: 1199 panic("Invalid type for IMMU demap\n"); 1200 } 1201 break; 1202 case ASI_DMMU: 1203 switch (va) { 1204 case 0x18: |
1212 tc->setMiscReg(MISCREG_MMU_DTLB_SFSR, data); | 1205 sfsr = data; |
1213 break; 1214 case 0x30: 1215 sext<59>(bits(data, 59,0)); | 1206 break; 1207 case 0x30: 1208 sext<59>(bits(data, 59,0)); |
1216 tc->setMiscReg(MISCREG_MMU_DTLB_TAG_ACCESS, data); | 1209 tag_access = data; |
1217 break; 1218 case 0x80: 1219 tc->setMiscReg(MISCREG_MMU_PART_ID, data); 1220 break; 1221 default: 1222 goto doMmuWriteError; 1223 } 1224 break; --- 51 unchanged lines hidden (view full) --- 1276 pkt->makeAtomicResponse(); 1277 return tc->getCpuPtr()->cycles(1); 1278} 1279 1280void 1281DTB::GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs) 1282{ 1283 uint64_t tag_access = mbits(addr,63,13) | mbits(ctx,12,0); | 1210 break; 1211 case 0x80: 1212 tc->setMiscReg(MISCREG_MMU_PART_ID, data); 1213 break; 1214 default: 1215 goto doMmuWriteError; 1216 } 1217 break; --- 51 unchanged lines hidden (view full) --- 1269 pkt->makeAtomicResponse(); 1270 return tc->getCpuPtr()->cycles(1); 1271} 1272 1273void 1274DTB::GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs) 1275{ 1276 uint64_t tag_access = mbits(addr,63,13) | mbits(ctx,12,0); |
1277 ITB * itb = tc->getITBPtr(); |
|
1284 ptrs[0] = MakeTsbPtr(Ps0, tag_access, | 1278 ptrs[0] = MakeTsbPtr(Ps0, tag_access, |
1285 tc->readMiscReg(MISCREG_MMU_DTLB_C0_TSB_PS0), 1286 tc->readMiscReg(MISCREG_MMU_DTLB_C0_CONFIG), 1287 tc->readMiscReg(MISCREG_MMU_DTLB_CX_TSB_PS0), 1288 tc->readMiscReg(MISCREG_MMU_DTLB_CX_CONFIG)); | 1279 c0_tsb_ps0, 1280 c0_config, 1281 cx_tsb_ps0, 1282 cx_config); |
1289 ptrs[1] = MakeTsbPtr(Ps1, tag_access, | 1283 ptrs[1] = MakeTsbPtr(Ps1, tag_access, |
1290 tc->readMiscReg(MISCREG_MMU_DTLB_C0_TSB_PS1), 1291 tc->readMiscReg(MISCREG_MMU_DTLB_C0_CONFIG), 1292 tc->readMiscReg(MISCREG_MMU_DTLB_CX_TSB_PS1), 1293 tc->readMiscReg(MISCREG_MMU_DTLB_CX_CONFIG)); | 1284 c0_tsb_ps1, 1285 c0_config, 1286 cx_tsb_ps1, 1287 cx_config); |
1294 ptrs[2] = MakeTsbPtr(Ps0, tag_access, | 1288 ptrs[2] = MakeTsbPtr(Ps0, tag_access, |
1295 tc->readMiscReg(MISCREG_MMU_ITLB_C0_TSB_PS0), 1296 tc->readMiscReg(MISCREG_MMU_ITLB_C0_CONFIG), 1297 tc->readMiscReg(MISCREG_MMU_ITLB_CX_TSB_PS0), 1298 tc->readMiscReg(MISCREG_MMU_ITLB_CX_CONFIG)); | 1289 itb->c0_tsb_ps0, 1290 itb->c0_config, 1291 itb->cx_tsb_ps0, 1292 itb->cx_config); |
1299 ptrs[3] = MakeTsbPtr(Ps1, tag_access, | 1293 ptrs[3] = MakeTsbPtr(Ps1, tag_access, |
1300 tc->readMiscReg(MISCREG_MMU_ITLB_C0_TSB_PS1), 1301 tc->readMiscReg(MISCREG_MMU_ITLB_C0_CONFIG), 1302 tc->readMiscReg(MISCREG_MMU_ITLB_CX_TSB_PS1), 1303 tc->readMiscReg(MISCREG_MMU_ITLB_CX_CONFIG)); | 1294 itb->c0_tsb_ps1, 1295 itb->c0_config, 1296 itb->cx_tsb_ps1, 1297 itb->cx_config); |
1304} 1305 1306 1307 1308 1309 1310uint64_t 1311DTB::MakeTsbPtr(TsbPageSize ps, uint64_t tag_access, uint64_t c0_tsb, --- 41 unchanged lines hidden (view full) --- 1353 } 1354 SERIALIZE_SCALAR(cntr); 1355 SERIALIZE_ARRAY(free_list, cntr); 1356 1357 for (int x = 0; x < size; x++) { 1358 nameOut(os, csprintf("%s.PTE%d", name(), x)); 1359 tlb[x].serialize(os); 1360 } | 1298} 1299 1300 1301 1302 1303 1304uint64_t 1305DTB::MakeTsbPtr(TsbPageSize ps, uint64_t tag_access, uint64_t c0_tsb, --- 41 unchanged lines hidden (view full) --- 1347 } 1348 SERIALIZE_SCALAR(cntr); 1349 SERIALIZE_ARRAY(free_list, cntr); 1350 1351 for (int x = 0; x < size; x++) { 1352 nameOut(os, csprintf("%s.PTE%d", name(), x)); 1353 tlb[x].serialize(os); 1354 } |
1355 1356 SERIALIZE_SCALAR(c0_tsb_ps0); 1357 SERIALIZE_SCALAR(c0_tsb_ps1); 1358 SERIALIZE_SCALAR(c0_config); 1359 SERIALIZE_SCALAR(cx_tsb_ps0); 1360 SERIALIZE_SCALAR(cx_tsb_ps1); 1361 SERIALIZE_SCALAR(cx_config); 1362 SERIALIZE_SCALAR(sfsr); 1363 SERIALIZE_SCALAR(tag_access); |
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1361} 1362 1363void 1364TLB::unserialize(Checkpoint *cp, const std::string §ion) 1365{ 1366 int oldSize; 1367 1368 paramIn(cp, section, "size", oldSize); --- 13 unchanged lines hidden (view full) --- 1382 1383 lookupTable.clear(); 1384 for (int x = 0; x < size; x++) { 1385 tlb[x].unserialize(cp, csprintf("%s.PTE%d", section, x)); 1386 if (tlb[x].valid) 1387 lookupTable.insert(tlb[x].range, &tlb[x]); 1388 1389 } | 1364} 1365 1366void 1367TLB::unserialize(Checkpoint *cp, const std::string §ion) 1368{ 1369 int oldSize; 1370 1371 paramIn(cp, section, "size", oldSize); --- 13 unchanged lines hidden (view full) --- 1385 1386 lookupTable.clear(); 1387 for (int x = 0; x < size; x++) { 1388 tlb[x].unserialize(cp, csprintf("%s.PTE%d", section, x)); 1389 if (tlb[x].valid) 1390 lookupTable.insert(tlb[x].range, &tlb[x]); 1391 1392 } |
1393 1394 UNSERIALIZE_SCALAR(c0_tsb_ps0); 1395 UNSERIALIZE_SCALAR(c0_tsb_ps1); 1396 UNSERIALIZE_SCALAR(c0_config); 1397 UNSERIALIZE_SCALAR(cx_tsb_ps0); 1398 UNSERIALIZE_SCALAR(cx_tsb_ps1); 1399 UNSERIALIZE_SCALAR(cx_config); 1400 UNSERIALIZE_SCALAR(sfsr); 1401 UNSERIALIZE_SCALAR(tag_access); |
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1390} 1391 | 1402} 1403 |
1404void 1405DTB::serialize(std::ostream &os) 1406{ 1407 TLB::serialize(os); 1408 SERIALIZE_SCALAR(sfar); 1409} 1410 1411void 1412DTB::unserialize(Checkpoint *cp, const std::string §ion) 1413{ 1414 TLB::unserialize(cp, section); 1415 UNSERIALIZE_SCALAR(sfar); 1416} 1417 |
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1392/* end namespace SparcISA */ } 1393 1394SparcISA::ITB * 1395SparcITBParams::create() 1396{ 1397 return new SparcISA::ITB(name, size); 1398} 1399 1400SparcISA::DTB * 1401SparcDTBParams::create() 1402{ 1403 return new SparcISA::DTB(name, size); 1404} | 1418/* end namespace SparcISA */ } 1419 1420SparcISA::ITB * 1421SparcITBParams::create() 1422{ 1423 return new SparcISA::ITB(name, size); 1424} 1425 1426SparcISA::DTB * 1427SparcDTBParams::create() 1428{ 1429 return new SparcISA::DTB(name, size); 1430} |