tlb.cc (4762:c94e103c83ad) tlb.cc (4870:fcc39d001154)
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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34#include "arch/sparc/miscregfile.hh"
35#include "arch/sparc/tlb.hh"
36#include "base/bitfield.hh"
37#include "base/trace.hh"
38#include "cpu/thread_context.hh"
39#include "cpu/base.hh"
40#include "mem/packet_access.hh"
41#include "mem/request.hh"
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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34#include "arch/sparc/miscregfile.hh"
35#include "arch/sparc/tlb.hh"
36#include "base/bitfield.hh"
37#include "base/trace.hh"
38#include "cpu/thread_context.hh"
39#include "cpu/base.hh"
40#include "mem/packet_access.hh"
41#include "mem/request.hh"
42#include "params/SparcDTB.hh"
43#include "params/SparcITB.hh"
42#include "sim/builder.hh"
44#include "sim/system.hh"
45
46/* @todo remove some of the magic constants. -- ali
47 * */
48namespace SparcISA {
49
50TLB::TLB(const std::string &name, int s)
51 : SimObject(name), size(s), usedEntries(0), lastReplaced(0),

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1019 tc->getCpuPtr()->clear_interrupt(IT_INT_VEC, temp);
1020 pkt->set(temp);
1021 break;
1022 default:
1023doMmuReadError:
1024 panic("need to impl DTB::doMmuRegRead() got asi=%#x, va=%#x\n",
1025 (uint32_t)asi, va);
1026 }
43#include "sim/system.hh"
44
45/* @todo remove some of the magic constants. -- ali
46 * */
47namespace SparcISA {
48
49TLB::TLB(const std::string &name, int s)
50 : SimObject(name), size(s), usedEntries(0), lastReplaced(0),

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1018 tc->getCpuPtr()->clear_interrupt(IT_INT_VEC, temp);
1019 pkt->set(temp);
1020 break;
1021 default:
1022doMmuReadError:
1023 panic("need to impl DTB::doMmuRegRead() got asi=%#x, va=%#x\n",
1024 (uint32_t)asi, va);
1025 }
1027 pkt->result = Packet::Success;
1026 pkt->makeAtomicResponse();
1028 return tc->getCpuPtr()->cycles(1);
1029}
1030
1031Tick
1032DTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
1033{
1034 uint64_t data = gtoh(pkt->get<uint64_t>());
1035 Addr va = pkt->getAddr();

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1264 tc->getSystemPtr()->threadContexts[bits(data,12,8)]->getCpuPtr()->
1265 post_interrupt(bits(data,5,0),0);
1266 break;
1267 default:
1268doMmuWriteError:
1269 panic("need to impl DTB::doMmuRegWrite() got asi=%#x, va=%#x d=%#x\n",
1270 (uint32_t)pkt->req->getAsi(), pkt->getAddr(), data);
1271 }
1027 return tc->getCpuPtr()->cycles(1);
1028}
1029
1030Tick
1031DTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
1032{
1033 uint64_t data = gtoh(pkt->get<uint64_t>());
1034 Addr va = pkt->getAddr();

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1263 tc->getSystemPtr()->threadContexts[bits(data,12,8)]->getCpuPtr()->
1264 post_interrupt(bits(data,5,0),0);
1265 break;
1266 default:
1267doMmuWriteError:
1268 panic("need to impl DTB::doMmuRegWrite() got asi=%#x, va=%#x d=%#x\n",
1269 (uint32_t)pkt->req->getAsi(), pkt->getAddr(), data);
1270 }
1272 pkt->result = Packet::Success;
1271 pkt->makeAtomicResponse();
1273 return tc->getCpuPtr()->cycles(1);
1274}
1275
1276void
1277DTB::GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs)
1278{
1279 uint64_t tag_access = mbits(addr,63,13) | mbits(ctx,12,0);
1280 ptrs[0] = MakeTsbPtr(Ps0, tag_access,

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1382 if (tlb[x].valid)
1383 lookupTable.insert(tlb[x].range, &tlb[x]);
1384
1385 }
1386}
1387
1388/* end namespace SparcISA */ }
1389
1272 return tc->getCpuPtr()->cycles(1);
1273}
1274
1275void
1276DTB::GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs)
1277{
1278 uint64_t tag_access = mbits(addr,63,13) | mbits(ctx,12,0);
1279 ptrs[0] = MakeTsbPtr(Ps0, tag_access,

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1381 if (tlb[x].valid)
1382 lookupTable.insert(tlb[x].range, &tlb[x]);
1383
1384 }
1385}
1386
1387/* end namespace SparcISA */ }
1388
1390SparcISA::ITB *
1391SparcITBParams::create()
1389using namespace SparcISA;
1390
1391DEFINE_SIM_OBJECT_CLASS_NAME("SparcTLB", TLB)
1392
1393BEGIN_DECLARE_SIM_OBJECT_PARAMS(ITB)
1394
1395 Param<int> size;
1396
1397END_DECLARE_SIM_OBJECT_PARAMS(ITB)
1398
1399BEGIN_INIT_SIM_OBJECT_PARAMS(ITB)
1400
1401 INIT_PARAM_DFLT(size, "TLB size", 48)
1402
1403END_INIT_SIM_OBJECT_PARAMS(ITB)
1404
1405
1406CREATE_SIM_OBJECT(ITB)
1392{
1407{
1393 return new SparcISA::ITB(name, size);
1408 return new ITB(getInstanceName(), size);
1394}
1395
1409}
1410
1396SparcISA::DTB *
1397SparcDTBParams::create()
1411REGISTER_SIM_OBJECT("SparcITB", ITB)
1412
1413BEGIN_DECLARE_SIM_OBJECT_PARAMS(DTB)
1414
1415 Param<int> size;
1416
1417END_DECLARE_SIM_OBJECT_PARAMS(DTB)
1418
1419BEGIN_INIT_SIM_OBJECT_PARAMS(DTB)
1420
1421 INIT_PARAM_DFLT(size, "TLB size", 64)
1422
1423END_INIT_SIM_OBJECT_PARAMS(DTB)
1424
1425
1426CREATE_SIM_OBJECT(DTB)
1398{
1427{
1399 return new SparcISA::DTB(name, size);
1428 return new DTB(getInstanceName(), size);
1400}
1429}
1430
1431REGISTER_SIM_OBJECT("SparcDTB", DTB)