tlb.cc (4103:785279436bdd) tlb.cc (4172:141705d83494)
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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391 return true;
392}
393
394void
395TLB::writeSfsr(ThreadContext *tc, int reg, bool write, ContextType ct,
396 bool se, FaultTypes ft, int asi)
397{
398 uint64_t sfsr;
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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391 return true;
392}
393
394void
395TLB::writeSfsr(ThreadContext *tc, int reg, bool write, ContextType ct,
396 bool se, FaultTypes ft, int asi)
397{
398 uint64_t sfsr;
399 sfsr = tc->readMiscReg(reg);
399 sfsr = tc->readMiscRegNoEffect(reg);
400
401 if (sfsr & 0x1)
402 sfsr = 0x3;
403 else
404 sfsr = 1;
405
406 if (write)
407 sfsr |= 1 << 2;
408 sfsr |= ct << 4;
409 if (se)
410 sfsr |= 1 << 6;
411 sfsr |= ft << 7;
412 sfsr |= asi << 16;
400
401 if (sfsr & 0x1)
402 sfsr = 0x3;
403 else
404 sfsr = 1;
405
406 if (write)
407 sfsr |= 1 << 2;
408 sfsr |= ct << 4;
409 if (se)
410 sfsr |= 1 << 6;
411 sfsr |= ft << 7;
412 sfsr |= asi << 16;
413 tc->setMiscRegWithEffect(reg, sfsr);
413 tc->setMiscReg(reg, sfsr);
414}
415
416void
417TLB::writeTagAccess(ThreadContext *tc, int reg, Addr va, int context)
418{
419 DPRINTF(TLB, "TLB: Writing Tag Access: va: %#X ctx: %#X value: %#X\n",
420 va, context, mbits(va, 63,13) | mbits(context,12,0));
421
414}
415
416void
417TLB::writeTagAccess(ThreadContext *tc, int reg, Addr va, int context)
418{
419 DPRINTF(TLB, "TLB: Writing Tag Access: va: %#X ctx: %#X value: %#X\n",
420 va, context, mbits(va, 63,13) | mbits(context,12,0));
421
422 tc->setMiscRegWithEffect(reg, mbits(va, 63,13) | mbits(context,12,0));
422 tc->setMiscReg(reg, mbits(va, 63,13) | mbits(context,12,0));
423}
424
425void
426ITB::writeSfsr(ThreadContext *tc, bool write, ContextType ct,
427 bool se, FaultTypes ft, int asi)
428{
429 DPRINTF(TLB, "TLB: ITB Fault: w=%d ct=%d ft=%d asi=%d\n",
430 (int)write, ct, ft, asi);

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439
440void
441DTB::writeSfr(ThreadContext *tc, Addr a, bool write, ContextType ct,
442 bool se, FaultTypes ft, int asi)
443{
444 DPRINTF(TLB, "TLB: DTB Fault: A=%#x w=%d ct=%d ft=%d asi=%d\n",
445 a, (int)write, ct, ft, asi);
446 TLB::writeSfsr(tc, MISCREG_MMU_DTLB_SFSR, write, ct, se, ft, asi);
423}
424
425void
426ITB::writeSfsr(ThreadContext *tc, bool write, ContextType ct,
427 bool se, FaultTypes ft, int asi)
428{
429 DPRINTF(TLB, "TLB: ITB Fault: w=%d ct=%d ft=%d asi=%d\n",
430 (int)write, ct, ft, asi);

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439
440void
441DTB::writeSfr(ThreadContext *tc, Addr a, bool write, ContextType ct,
442 bool se, FaultTypes ft, int asi)
443{
444 DPRINTF(TLB, "TLB: DTB Fault: A=%#x w=%d ct=%d ft=%d asi=%d\n",
445 a, (int)write, ct, ft, asi);
446 TLB::writeSfsr(tc, MISCREG_MMU_DTLB_SFSR, write, ct, se, ft, asi);
447 tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_SFAR, a);
447 tc->setMiscReg(MISCREG_MMU_DTLB_SFAR, a);
448}
449
450void
451DTB::writeTagAccess(ThreadContext *tc, Addr va, int context)
452{
453 TLB::writeTagAccess(tc, MISCREG_MMU_DTLB_TAG_ACCESS, va, context);
454}
455
456
457
458Fault
459ITB::translate(RequestPtr &req, ThreadContext *tc)
460{
448}
449
450void
451DTB::writeTagAccess(ThreadContext *tc, Addr va, int context)
452{
453 TLB::writeTagAccess(tc, MISCREG_MMU_DTLB_TAG_ACCESS, va, context);
454}
455
456
457
458Fault
459ITB::translate(RequestPtr &req, ThreadContext *tc)
460{
461 uint64_t tlbdata = tc->readMiscReg(MISCREG_TLB_DATA);
461 uint64_t tlbdata = tc->readMiscRegNoEffect(MISCREG_TLB_DATA);
462
463 Addr vaddr = req->getVaddr();
464 TlbEntry *e;
465
466 assert(req->getAsi() == ASI_IMPLICIT);
467
468 DPRINTF(TLB, "TLB: ITB Request to translate va=%#x size=%d\n",
469 vaddr, req->getSize());

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567}
568
569
570
571Fault
572DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
573{
574 /* @todo this could really use some profiling and fixing to make it faster! */
462
463 Addr vaddr = req->getVaddr();
464 TlbEntry *e;
465
466 assert(req->getAsi() == ASI_IMPLICIT);
467
468 DPRINTF(TLB, "TLB: ITB Request to translate va=%#x size=%d\n",
469 vaddr, req->getSize());

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567}
568
569
570
571Fault
572DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
573{
574 /* @todo this could really use some profiling and fixing to make it faster! */
575 uint64_t tlbdata = tc->readMiscReg(MISCREG_TLB_DATA);
575 uint64_t tlbdata = tc->readMiscRegNoEffect(MISCREG_TLB_DATA);
576 Addr vaddr = req->getVaddr();
577 Addr size = req->getSize();
578 ASI asi;
579 asi = (ASI)req->getAsi();
580 bool implicit = false;
581 bool hpriv = bits(tlbdata,0,0);
582
583 DPRINTF(TLB, "TLB: DTB Request to translate va=%#x size=%d asi=%#x\n",

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859 uint64_t temp;
860
861 DPRINTF(IPR, "Memory Mapped IPR Read: asi=%#X a=%#x\n",
862 (uint32_t)pkt->req->getAsi(), pkt->getAddr());
863
864 switch (asi) {
865 case ASI_LSU_CONTROL_REG:
866 assert(va == 0);
576 Addr vaddr = req->getVaddr();
577 Addr size = req->getSize();
578 ASI asi;
579 asi = (ASI)req->getAsi();
580 bool implicit = false;
581 bool hpriv = bits(tlbdata,0,0);
582
583 DPRINTF(TLB, "TLB: DTB Request to translate va=%#x size=%d asi=%#x\n",

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859 uint64_t temp;
860
861 DPRINTF(IPR, "Memory Mapped IPR Read: asi=%#X a=%#x\n",
862 (uint32_t)pkt->req->getAsi(), pkt->getAddr());
863
864 switch (asi) {
865 case ASI_LSU_CONTROL_REG:
866 assert(va == 0);
867 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_LSU_CTRL));
867 pkt->set(tc->readMiscReg(MISCREG_MMU_LSU_CTRL));
868 break;
869 case ASI_MMU:
870 switch (va) {
871 case 0x8:
868 break;
869 case ASI_MMU:
870 switch (va) {
871 case 0x8:
872 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_P_CONTEXT));
872 pkt->set(tc->readMiscReg(MISCREG_MMU_P_CONTEXT));
873 break;
874 case 0x10:
873 break;
874 case 0x10:
875 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_S_CONTEXT));
875 pkt->set(tc->readMiscReg(MISCREG_MMU_S_CONTEXT));
876 break;
877 default:
878 goto doMmuReadError;
879 }
880 break;
881 case ASI_QUEUE:
876 break;
877 default:
878 goto doMmuReadError;
879 }
880 break;
881 case ASI_QUEUE:
882 pkt->set(tc->readMiscRegWithEffect(MISCREG_QUEUE_CPU_MONDO_HEAD +
882 pkt->set(tc->readMiscReg(MISCREG_QUEUE_CPU_MONDO_HEAD +
883 (va >> 4) - 0x3c));
884 break;
885 case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0:
886 assert(va == 0);
883 (va >> 4) - 0x3c));
884 break;
885 case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0:
886 assert(va == 0);
887 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS0));
887 pkt->set(tc->readMiscReg(MISCREG_MMU_DTLB_C0_TSB_PS0));
888 break;
889 case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1:
890 assert(va == 0);
888 break;
889 case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1:
890 assert(va == 0);
891 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS1));
891 pkt->set(tc->readMiscReg(MISCREG_MMU_DTLB_C0_TSB_PS1));
892 break;
893 case ASI_DMMU_CTXT_ZERO_CONFIG:
894 assert(va == 0);
892 break;
893 case ASI_DMMU_CTXT_ZERO_CONFIG:
894 assert(va == 0);
895 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG));
895 pkt->set(tc->readMiscReg(MISCREG_MMU_DTLB_C0_CONFIG));
896 break;
897 case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0:
898 assert(va == 0);
896 break;
897 case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0:
898 assert(va == 0);
899 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS0));
899 pkt->set(tc->readMiscReg(MISCREG_MMU_ITLB_C0_TSB_PS0));
900 break;
901 case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1:
902 assert(va == 0);
900 break;
901 case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1:
902 assert(va == 0);
903 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS1));
903 pkt->set(tc->readMiscReg(MISCREG_MMU_ITLB_C0_TSB_PS1));
904 break;
905 case ASI_IMMU_CTXT_ZERO_CONFIG:
906 assert(va == 0);
904 break;
905 case ASI_IMMU_CTXT_ZERO_CONFIG:
906 assert(va == 0);
907 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG));
907 pkt->set(tc->readMiscReg(MISCREG_MMU_ITLB_C0_CONFIG));
908 break;
909 case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0:
910 assert(va == 0);
908 break;
909 case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0:
910 assert(va == 0);
911 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS0));
911 pkt->set(tc->readMiscReg(MISCREG_MMU_DTLB_CX_TSB_PS0));
912 break;
913 case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1:
914 assert(va == 0);
912 break;
913 case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1:
914 assert(va == 0);
915 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS1));
915 pkt->set(tc->readMiscReg(MISCREG_MMU_DTLB_CX_TSB_PS1));
916 break;
917 case ASI_DMMU_CTXT_NONZERO_CONFIG:
918 assert(va == 0);
916 break;
917 case ASI_DMMU_CTXT_NONZERO_CONFIG:
918 assert(va == 0);
919 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG));
919 pkt->set(tc->readMiscReg(MISCREG_MMU_DTLB_CX_CONFIG));
920 break;
921 case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0:
922 assert(va == 0);
920 break;
921 case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0:
922 assert(va == 0);
923 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS0));
923 pkt->set(tc->readMiscReg(MISCREG_MMU_ITLB_CX_TSB_PS0));
924 break;
925 case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1:
926 assert(va == 0);
924 break;
925 case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1:
926 assert(va == 0);
927 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS1));
927 pkt->set(tc->readMiscReg(MISCREG_MMU_ITLB_CX_TSB_PS1));
928 break;
929 case ASI_IMMU_CTXT_NONZERO_CONFIG:
930 assert(va == 0);
928 break;
929 case ASI_IMMU_CTXT_NONZERO_CONFIG:
930 assert(va == 0);
931 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG));
931 pkt->set(tc->readMiscReg(MISCREG_MMU_ITLB_CX_CONFIG));
932 break;
933 case ASI_SPARC_ERROR_STATUS_REG:
934 pkt->set((uint64_t)0);
935 break;
936 case ASI_HYP_SCRATCHPAD:
937 case ASI_SCRATCHPAD:
932 break;
933 case ASI_SPARC_ERROR_STATUS_REG:
934 pkt->set((uint64_t)0);
935 break;
936 case ASI_HYP_SCRATCHPAD:
937 case ASI_SCRATCHPAD:
938 pkt->set(tc->readMiscRegWithEffect(MISCREG_SCRATCHPAD_R0 + (va >> 3)));
938 pkt->set(tc->readMiscReg(MISCREG_SCRATCHPAD_R0 + (va >> 3)));
939 break;
940 case ASI_IMMU:
941 switch (va) {
942 case 0x0:
939 break;
940 case ASI_IMMU:
941 switch (va) {
942 case 0x0:
943 temp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS);
943 temp = tc->readMiscReg(MISCREG_MMU_ITLB_TAG_ACCESS);
944 pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48);
945 break;
946 case 0x18:
944 pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48);
945 break;
946 case 0x18:
947 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_SFSR));
947 pkt->set(tc->readMiscReg(MISCREG_MMU_ITLB_SFSR));
948 break;
949 case 0x30:
948 break;
949 case 0x30:
950 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS));
950 pkt->set(tc->readMiscReg(MISCREG_MMU_ITLB_TAG_ACCESS));
951 break;
952 default:
953 goto doMmuReadError;
954 }
955 break;
956 case ASI_DMMU:
957 switch (va) {
958 case 0x0:
951 break;
952 default:
953 goto doMmuReadError;
954 }
955 break;
956 case ASI_DMMU:
957 switch (va) {
958 case 0x0:
959 temp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS);
959 temp = tc->readMiscReg(MISCREG_MMU_DTLB_TAG_ACCESS);
960 pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48);
961 break;
962 case 0x18:
960 pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48);
961 break;
962 case 0x18:
963 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_SFSR));
963 pkt->set(tc->readMiscReg(MISCREG_MMU_DTLB_SFSR));
964 break;
965 case 0x20:
964 break;
965 case 0x20:
966 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_SFAR));
966 pkt->set(tc->readMiscReg(MISCREG_MMU_DTLB_SFAR));
967 break;
968 case 0x30:
967 break;
968 case 0x30:
969 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS));
969 pkt->set(tc->readMiscReg(MISCREG_MMU_DTLB_TAG_ACCESS));
970 break;
971 case 0x80:
970 break;
971 case 0x80:
972 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID));
972 pkt->set(tc->readMiscReg(MISCREG_MMU_PART_ID));
973 break;
974 default:
975 goto doMmuReadError;
976 }
977 break;
978 case ASI_DMMU_TSB_PS0_PTR_REG:
979 pkt->set(MakeTsbPtr(Ps0,
973 break;
974 default:
975 goto doMmuReadError;
976 }
977 break;
978 case ASI_DMMU_TSB_PS0_PTR_REG:
979 pkt->set(MakeTsbPtr(Ps0,
980 tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS),
981 tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS0),
982 tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG),
983 tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS0),
984 tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG)));
980 tc->readMiscReg(MISCREG_MMU_DTLB_TAG_ACCESS),
981 tc->readMiscReg(MISCREG_MMU_DTLB_C0_TSB_PS0),
982 tc->readMiscReg(MISCREG_MMU_DTLB_C0_CONFIG),
983 tc->readMiscReg(MISCREG_MMU_DTLB_CX_TSB_PS0),
984 tc->readMiscReg(MISCREG_MMU_DTLB_CX_CONFIG)));
985 break;
986 case ASI_DMMU_TSB_PS1_PTR_REG:
987 pkt->set(MakeTsbPtr(Ps1,
985 break;
986 case ASI_DMMU_TSB_PS1_PTR_REG:
987 pkt->set(MakeTsbPtr(Ps1,
988 tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS),
989 tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS1),
990 tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG),
991 tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS1),
992 tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG)));
988 tc->readMiscReg(MISCREG_MMU_DTLB_TAG_ACCESS),
989 tc->readMiscReg(MISCREG_MMU_DTLB_C0_TSB_PS1),
990 tc->readMiscReg(MISCREG_MMU_DTLB_C0_CONFIG),
991 tc->readMiscReg(MISCREG_MMU_DTLB_CX_TSB_PS1),
992 tc->readMiscReg(MISCREG_MMU_DTLB_CX_CONFIG)));
993 break;
994 case ASI_IMMU_TSB_PS0_PTR_REG:
995 pkt->set(MakeTsbPtr(Ps0,
993 break;
994 case ASI_IMMU_TSB_PS0_PTR_REG:
995 pkt->set(MakeTsbPtr(Ps0,
996 tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS),
997 tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS0),
998 tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG),
999 tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS0),
1000 tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG)));
996 tc->readMiscReg(MISCREG_MMU_ITLB_TAG_ACCESS),
997 tc->readMiscReg(MISCREG_MMU_ITLB_C0_TSB_PS0),
998 tc->readMiscReg(MISCREG_MMU_ITLB_C0_CONFIG),
999 tc->readMiscReg(MISCREG_MMU_ITLB_CX_TSB_PS0),
1000 tc->readMiscReg(MISCREG_MMU_ITLB_CX_CONFIG)));
1001 break;
1002 case ASI_IMMU_TSB_PS1_PTR_REG:
1003 pkt->set(MakeTsbPtr(Ps1,
1001 break;
1002 case ASI_IMMU_TSB_PS1_PTR_REG:
1003 pkt->set(MakeTsbPtr(Ps1,
1004 tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS),
1005 tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS1),
1006 tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG),
1007 tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS1),
1008 tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG)));
1004 tc->readMiscReg(MISCREG_MMU_ITLB_TAG_ACCESS),
1005 tc->readMiscReg(MISCREG_MMU_ITLB_C0_TSB_PS1),
1006 tc->readMiscReg(MISCREG_MMU_ITLB_C0_CONFIG),
1007 tc->readMiscReg(MISCREG_MMU_ITLB_CX_TSB_PS1),
1008 tc->readMiscReg(MISCREG_MMU_ITLB_CX_CONFIG)));
1009 break;
1010 case ASI_SWVR_INTR_RECEIVE:
1011 pkt->set(tc->getCpuPtr()->get_interrupts(IT_INT_VEC));
1012 break;
1013 case ASI_SWVR_UDB_INTR_R:
1014 temp = findMsbSet(tc->getCpuPtr()->get_interrupts(IT_INT_VEC));
1015 tc->getCpuPtr()->clear_interrupt(IT_INT_VEC, temp);
1016 pkt->set(temp);

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1043 PageTableEntry pte;
1044
1045 DPRINTF(IPR, "Memory Mapped IPR Write: asi=%#X a=%#x d=%#X\n",
1046 (uint32_t)asi, va, data);
1047
1048 switch (asi) {
1049 case ASI_LSU_CONTROL_REG:
1050 assert(va == 0);
1009 break;
1010 case ASI_SWVR_INTR_RECEIVE:
1011 pkt->set(tc->getCpuPtr()->get_interrupts(IT_INT_VEC));
1012 break;
1013 case ASI_SWVR_UDB_INTR_R:
1014 temp = findMsbSet(tc->getCpuPtr()->get_interrupts(IT_INT_VEC));
1015 tc->getCpuPtr()->clear_interrupt(IT_INT_VEC, temp);
1016 pkt->set(temp);

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1043 PageTableEntry pte;
1044
1045 DPRINTF(IPR, "Memory Mapped IPR Write: asi=%#X a=%#x d=%#X\n",
1046 (uint32_t)asi, va, data);
1047
1048 switch (asi) {
1049 case ASI_LSU_CONTROL_REG:
1050 assert(va == 0);
1051 tc->setMiscRegWithEffect(MISCREG_MMU_LSU_CTRL, data);
1051 tc->setMiscReg(MISCREG_MMU_LSU_CTRL, data);
1052 break;
1053 case ASI_MMU:
1054 switch (va) {
1055 case 0x8:
1052 break;
1053 case ASI_MMU:
1054 switch (va) {
1055 case 0x8:
1056 tc->setMiscRegWithEffect(MISCREG_MMU_P_CONTEXT, data);
1056 tc->setMiscReg(MISCREG_MMU_P_CONTEXT, data);
1057 break;
1058 case 0x10:
1057 break;
1058 case 0x10:
1059 tc->setMiscRegWithEffect(MISCREG_MMU_S_CONTEXT, data);
1059 tc->setMiscReg(MISCREG_MMU_S_CONTEXT, data);
1060 break;
1061 default:
1062 goto doMmuWriteError;
1063 }
1064 break;
1065 case ASI_QUEUE:
1066 assert(mbits(data,13,6) == data);
1060 break;
1061 default:
1062 goto doMmuWriteError;
1063 }
1064 break;
1065 case ASI_QUEUE:
1066 assert(mbits(data,13,6) == data);
1067 tc->setMiscRegWithEffect(MISCREG_QUEUE_CPU_MONDO_HEAD +
1067 tc->setMiscReg(MISCREG_QUEUE_CPU_MONDO_HEAD +
1068 (va >> 4) - 0x3c, data);
1069 break;
1070 case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0:
1071 assert(va == 0);
1068 (va >> 4) - 0x3c, data);
1069 break;
1070 case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0:
1071 assert(va == 0);
1072 tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS0, data);
1072 tc->setMiscReg(MISCREG_MMU_DTLB_C0_TSB_PS0, data);
1073 break;
1074 case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1:
1075 assert(va == 0);
1073 break;
1074 case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1:
1075 assert(va == 0);
1076 tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS1, data);
1076 tc->setMiscReg(MISCREG_MMU_DTLB_C0_TSB_PS1, data);
1077 break;
1078 case ASI_DMMU_CTXT_ZERO_CONFIG:
1079 assert(va == 0);
1077 break;
1078 case ASI_DMMU_CTXT_ZERO_CONFIG:
1079 assert(va == 0);
1080 tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG, data);
1080 tc->setMiscReg(MISCREG_MMU_DTLB_C0_CONFIG, data);
1081 break;
1082 case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0:
1083 assert(va == 0);
1081 break;
1082 case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0:
1083 assert(va == 0);
1084 tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS0, data);
1084 tc->setMiscReg(MISCREG_MMU_ITLB_C0_TSB_PS0, data);
1085 break;
1086 case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1:
1087 assert(va == 0);
1085 break;
1086 case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1:
1087 assert(va == 0);
1088 tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS1, data);
1088 tc->setMiscReg(MISCREG_MMU_ITLB_C0_TSB_PS1, data);
1089 break;
1090 case ASI_IMMU_CTXT_ZERO_CONFIG:
1091 assert(va == 0);
1089 break;
1090 case ASI_IMMU_CTXT_ZERO_CONFIG:
1091 assert(va == 0);
1092 tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG, data);
1092 tc->setMiscReg(MISCREG_MMU_ITLB_C0_CONFIG, data);
1093 break;
1094 case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0:
1095 assert(va == 0);
1093 break;
1094 case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0:
1095 assert(va == 0);
1096 tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS0, data);
1096 tc->setMiscReg(MISCREG_MMU_DTLB_CX_TSB_PS0, data);
1097 break;
1098 case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1:
1099 assert(va == 0);
1097 break;
1098 case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1:
1099 assert(va == 0);
1100 tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS1, data);
1100 tc->setMiscReg(MISCREG_MMU_DTLB_CX_TSB_PS1, data);
1101 break;
1102 case ASI_DMMU_CTXT_NONZERO_CONFIG:
1103 assert(va == 0);
1101 break;
1102 case ASI_DMMU_CTXT_NONZERO_CONFIG:
1103 assert(va == 0);
1104 tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG, data);
1104 tc->setMiscReg(MISCREG_MMU_DTLB_CX_CONFIG, data);
1105 break;
1106 case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0:
1107 assert(va == 0);
1105 break;
1106 case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0:
1107 assert(va == 0);
1108 tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS0, data);
1108 tc->setMiscReg(MISCREG_MMU_ITLB_CX_TSB_PS0, data);
1109 break;
1110 case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1:
1111 assert(va == 0);
1109 break;
1110 case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1:
1111 assert(va == 0);
1112 tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS1, data);
1112 tc->setMiscReg(MISCREG_MMU_ITLB_CX_TSB_PS1, data);
1113 break;
1114 case ASI_IMMU_CTXT_NONZERO_CONFIG:
1115 assert(va == 0);
1113 break;
1114 case ASI_IMMU_CTXT_NONZERO_CONFIG:
1115 assert(va == 0);
1116 tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG, data);
1116 tc->setMiscReg(MISCREG_MMU_ITLB_CX_CONFIG, data);
1117 break;
1118 case ASI_SPARC_ERROR_EN_REG:
1119 case ASI_SPARC_ERROR_STATUS_REG:
1120 warn("Ignoring write to SPARC ERROR regsiter\n");
1121 break;
1122 case ASI_HYP_SCRATCHPAD:
1123 case ASI_SCRATCHPAD:
1117 break;
1118 case ASI_SPARC_ERROR_EN_REG:
1119 case ASI_SPARC_ERROR_STATUS_REG:
1120 warn("Ignoring write to SPARC ERROR regsiter\n");
1121 break;
1122 case ASI_HYP_SCRATCHPAD:
1123 case ASI_SCRATCHPAD:
1124 tc->setMiscRegWithEffect(MISCREG_SCRATCHPAD_R0 + (va >> 3), data);
1124 tc->setMiscReg(MISCREG_SCRATCHPAD_R0 + (va >> 3), data);
1125 break;
1126 case ASI_IMMU:
1127 switch (va) {
1128 case 0x18:
1125 break;
1126 case ASI_IMMU:
1127 switch (va) {
1128 case 0x18:
1129 tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_SFSR, data);
1129 tc->setMiscReg(MISCREG_MMU_ITLB_SFSR, data);
1130 break;
1131 case 0x30:
1132 sext<59>(bits(data, 59,0));
1130 break;
1131 case 0x30:
1132 sext<59>(bits(data, 59,0));
1133 tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS, data);
1133 tc->setMiscReg(MISCREG_MMU_ITLB_TAG_ACCESS, data);
1134 break;
1135 default:
1136 goto doMmuWriteError;
1137 }
1138 break;
1139 case ASI_ITLB_DATA_ACCESS_REG:
1140 entry_insert = bits(va, 8,3);
1141 case ASI_ITLB_DATA_IN_REG:
1142 assert(entry_insert != -1 || mbits(va,10,9) == va);
1134 break;
1135 default:
1136 goto doMmuWriteError;
1137 }
1138 break;
1139 case ASI_ITLB_DATA_ACCESS_REG:
1140 entry_insert = bits(va, 8,3);
1141 case ASI_ITLB_DATA_IN_REG:
1142 assert(entry_insert != -1 || mbits(va,10,9) == va);
1143 ta_insert = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS);
1143 ta_insert = tc->readMiscReg(MISCREG_MMU_ITLB_TAG_ACCESS);
1144 va_insert = mbits(ta_insert, 63,13);
1145 ct_insert = mbits(ta_insert, 12,0);
1144 va_insert = mbits(ta_insert, 63,13);
1145 ct_insert = mbits(ta_insert, 12,0);
1146 part_insert = tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID);
1146 part_insert = tc->readMiscReg(MISCREG_MMU_PART_ID);
1147 real_insert = bits(va, 9,9);
1148 pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v :
1149 PageTableEntry::sun4u);
1150 tc->getITBPtr()->insert(va_insert, part_insert, ct_insert, real_insert,
1151 pte, entry_insert);
1152 break;
1153 case ASI_DTLB_DATA_ACCESS_REG:
1154 entry_insert = bits(va, 8,3);
1155 case ASI_DTLB_DATA_IN_REG:
1156 assert(entry_insert != -1 || mbits(va,10,9) == va);
1147 real_insert = bits(va, 9,9);
1148 pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v :
1149 PageTableEntry::sun4u);
1150 tc->getITBPtr()->insert(va_insert, part_insert, ct_insert, real_insert,
1151 pte, entry_insert);
1152 break;
1153 case ASI_DTLB_DATA_ACCESS_REG:
1154 entry_insert = bits(va, 8,3);
1155 case ASI_DTLB_DATA_IN_REG:
1156 assert(entry_insert != -1 || mbits(va,10,9) == va);
1157 ta_insert = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS);
1157 ta_insert = tc->readMiscReg(MISCREG_MMU_DTLB_TAG_ACCESS);
1158 va_insert = mbits(ta_insert, 63,13);
1159 ct_insert = mbits(ta_insert, 12,0);
1158 va_insert = mbits(ta_insert, 63,13);
1159 ct_insert = mbits(ta_insert, 12,0);
1160 part_insert = tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID);
1160 part_insert = tc->readMiscReg(MISCREG_MMU_PART_ID);
1161 real_insert = bits(va, 9,9);
1162 pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v :
1163 PageTableEntry::sun4u);
1164 insert(va_insert, part_insert, ct_insert, real_insert, pte, entry_insert);
1165 break;
1166 case ASI_IMMU_DEMAP:
1167 ignore = false;
1168 ctx_id = -1;
1161 real_insert = bits(va, 9,9);
1162 pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v :
1163 PageTableEntry::sun4u);
1164 insert(va_insert, part_insert, ct_insert, real_insert, pte, entry_insert);
1165 break;
1166 case ASI_IMMU_DEMAP:
1167 ignore = false;
1168 ctx_id = -1;
1169 part_id = tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID);
1169 part_id = tc->readMiscReg(MISCREG_MMU_PART_ID);
1170 switch (bits(va,5,4)) {
1171 case 0:
1170 switch (bits(va,5,4)) {
1171 case 0:
1172 ctx_id = tc->readMiscRegWithEffect(MISCREG_MMU_P_CONTEXT);
1172 ctx_id = tc->readMiscReg(MISCREG_MMU_P_CONTEXT);
1173 break;
1174 case 1:
1175 ignore = true;
1176 break;
1177 case 3:
1178 ctx_id = 0;
1179 break;
1180 default:

--- 15 unchanged lines hidden (view full) ---

1196 break;
1197 default:
1198 panic("Invalid type for IMMU demap\n");
1199 }
1200 break;
1201 case ASI_DMMU:
1202 switch (va) {
1203 case 0x18:
1173 break;
1174 case 1:
1175 ignore = true;
1176 break;
1177 case 3:
1178 ctx_id = 0;
1179 break;
1180 default:

--- 15 unchanged lines hidden (view full) ---

1196 break;
1197 default:
1198 panic("Invalid type for IMMU demap\n");
1199 }
1200 break;
1201 case ASI_DMMU:
1202 switch (va) {
1203 case 0x18:
1204 tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_SFSR, data);
1204 tc->setMiscReg(MISCREG_MMU_DTLB_SFSR, data);
1205 break;
1206 case 0x30:
1207 sext<59>(bits(data, 59,0));
1205 break;
1206 case 0x30:
1207 sext<59>(bits(data, 59,0));
1208 tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS, data);
1208 tc->setMiscReg(MISCREG_MMU_DTLB_TAG_ACCESS, data);
1209 break;
1210 case 0x80:
1209 break;
1210 case 0x80:
1211 tc->setMiscRegWithEffect(MISCREG_MMU_PART_ID, data);
1211 tc->setMiscReg(MISCREG_MMU_PART_ID, data);
1212 break;
1213 default:
1214 goto doMmuWriteError;
1215 }
1216 break;
1217 case ASI_DMMU_DEMAP:
1218 ignore = false;
1219 ctx_id = -1;
1212 break;
1213 default:
1214 goto doMmuWriteError;
1215 }
1216 break;
1217 case ASI_DMMU_DEMAP:
1218 ignore = false;
1219 ctx_id = -1;
1220 part_id = tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID);
1220 part_id = tc->readMiscReg(MISCREG_MMU_PART_ID);
1221 switch (bits(va,5,4)) {
1222 case 0:
1221 switch (bits(va,5,4)) {
1222 case 0:
1223 ctx_id = tc->readMiscRegWithEffect(MISCREG_MMU_P_CONTEXT);
1223 ctx_id = tc->readMiscReg(MISCREG_MMU_P_CONTEXT);
1224 break;
1225 case 1:
1224 break;
1225 case 1:
1226 ctx_id = tc->readMiscRegWithEffect(MISCREG_MMU_S_CONTEXT);
1226 ctx_id = tc->readMiscReg(MISCREG_MMU_S_CONTEXT);
1227 break;
1228 case 3:
1229 ctx_id = 0;
1230 break;
1231 default:
1232 ignore = true;
1233 }
1234

--- 34 unchanged lines hidden (view full) ---

1269 return tc->getCpuPtr()->cycles(1);
1270}
1271
1272void
1273DTB::GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs)
1274{
1275 uint64_t tag_access = mbits(addr,63,13) | mbits(ctx,12,0);
1276 ptrs[0] = MakeTsbPtr(Ps0, tag_access,
1227 break;
1228 case 3:
1229 ctx_id = 0;
1230 break;
1231 default:
1232 ignore = true;
1233 }
1234

--- 34 unchanged lines hidden (view full) ---

1269 return tc->getCpuPtr()->cycles(1);
1270}
1271
1272void
1273DTB::GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs)
1274{
1275 uint64_t tag_access = mbits(addr,63,13) | mbits(ctx,12,0);
1276 ptrs[0] = MakeTsbPtr(Ps0, tag_access,
1277 tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS0),
1278 tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG),
1279 tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS0),
1280 tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG));
1277 tc->readMiscReg(MISCREG_MMU_DTLB_C0_TSB_PS0),
1278 tc->readMiscReg(MISCREG_MMU_DTLB_C0_CONFIG),
1279 tc->readMiscReg(MISCREG_MMU_DTLB_CX_TSB_PS0),
1280 tc->readMiscReg(MISCREG_MMU_DTLB_CX_CONFIG));
1281 ptrs[1] = MakeTsbPtr(Ps1, tag_access,
1281 ptrs[1] = MakeTsbPtr(Ps1, tag_access,
1282 tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS1),
1283 tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG),
1284 tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS1),
1285 tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG));
1282 tc->readMiscReg(MISCREG_MMU_DTLB_C0_TSB_PS1),
1283 tc->readMiscReg(MISCREG_MMU_DTLB_C0_CONFIG),
1284 tc->readMiscReg(MISCREG_MMU_DTLB_CX_TSB_PS1),
1285 tc->readMiscReg(MISCREG_MMU_DTLB_CX_CONFIG));
1286 ptrs[2] = MakeTsbPtr(Ps0, tag_access,
1286 ptrs[2] = MakeTsbPtr(Ps0, tag_access,
1287 tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS0),
1288 tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG),
1289 tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS0),
1290 tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG));
1287 tc->readMiscReg(MISCREG_MMU_ITLB_C0_TSB_PS0),
1288 tc->readMiscReg(MISCREG_MMU_ITLB_C0_CONFIG),
1289 tc->readMiscReg(MISCREG_MMU_ITLB_CX_TSB_PS0),
1290 tc->readMiscReg(MISCREG_MMU_ITLB_CX_CONFIG));
1291 ptrs[3] = MakeTsbPtr(Ps1, tag_access,
1291 ptrs[3] = MakeTsbPtr(Ps1, tag_access,
1292 tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS1),
1293 tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG),
1294 tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS1),
1295 tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG));
1292 tc->readMiscReg(MISCREG_MMU_ITLB_C0_TSB_PS1),
1293 tc->readMiscReg(MISCREG_MMU_ITLB_C0_CONFIG),
1294 tc->readMiscReg(MISCREG_MMU_ITLB_CX_TSB_PS1),
1295 tc->readMiscReg(MISCREG_MMU_ITLB_CX_CONFIG));
1296}
1297
1298
1299
1300
1301
1302uint64_t
1303DTB::MakeTsbPtr(TsbPageSize ps, uint64_t tag_access, uint64_t c0_tsb,

--- 125 unchanged lines hidden --- 		1296}
1297
1298
1299
1300
1301
1302uint64_t
1303DTB::MakeTsbPtr(TsbPageSize ps, uint64_t tag_access, uint64_t c0_tsb,

--- 125 unchanged lines hidden ---