tlb.cc (4070:74449a198a44) | tlb.cc (4088:a60eb44ae415) |
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1/* 2 * Copyright (c) 2001-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 29 unchanged lines hidden (view full) --- 38#include "cpu/thread_context.hh" 39#include "cpu/base.hh" 40#include "mem/packet_access.hh" 41#include "mem/request.hh" 42#include "sim/builder.hh" 43 44/* @todo remove some of the magic constants. -- ali 45 * */ | 1/* 2 * Copyright (c) 2001-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 29 unchanged lines hidden (view full) --- 38#include "cpu/thread_context.hh" 39#include "cpu/base.hh" 40#include "mem/packet_access.hh" 41#include "mem/request.hh" 42#include "sim/builder.hh" 43 44/* @todo remove some of the magic constants. -- ali 45 * */ |
46namespace SparcISA 47{ | 46namespace SparcISA { |
48 49TLB::TLB(const std::string &name, int s) 50 : SimObject(name), size(s), usedEntries(0), lastReplaced(0), 51 cacheValid(false) 52{ 53 // To make this work you'll have to change the hypervisor and OS 54 if (size > 64) 55 fatal("SPARC T1 TLB registers don't support more than 64 TLB entries."); --- 1268 unchanged lines hidden (view full) --- 1324 for (int x = 0; x < size; x++) { 1325 tlb[x].unserialize(cp, csprintf("%s.PTE%d", section, x)); 1326 if (tlb[x].valid) 1327 lookupTable.insert(tlb[x].range, &tlb[x]); 1328 1329 } 1330} 1331 | 47 48TLB::TLB(const std::string &name, int s) 49 : SimObject(name), size(s), usedEntries(0), lastReplaced(0), 50 cacheValid(false) 51{ 52 // To make this work you'll have to change the hypervisor and OS 53 if (size > 64) 54 fatal("SPARC T1 TLB registers don't support more than 64 TLB entries."); --- 1268 unchanged lines hidden (view full) --- 1323 for (int x = 0; x < size; x++) { 1324 tlb[x].unserialize(cp, csprintf("%s.PTE%d", section, x)); 1325 if (tlb[x].valid) 1326 lookupTable.insert(tlb[x].range, &tlb[x]); 1327 1328 } 1329} 1330 |
1331/* end namespace SparcISA */ } |
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1332 | 1332 |
1333using namespace SparcISA; 1334 |
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1333DEFINE_SIM_OBJECT_CLASS_NAME("SparcTLB", TLB) 1334 1335BEGIN_DECLARE_SIM_OBJECT_PARAMS(ITB) 1336 1337 Param<int> size; 1338 1339END_DECLARE_SIM_OBJECT_PARAMS(ITB) 1340 --- 25 unchanged lines hidden (view full) --- 1366 1367 1368CREATE_SIM_OBJECT(DTB) 1369{ 1370 return new DTB(getInstanceName(), size); 1371} 1372 1373REGISTER_SIM_OBJECT("SparcDTB", DTB) | 1335DEFINE_SIM_OBJECT_CLASS_NAME("SparcTLB", TLB) 1336 1337BEGIN_DECLARE_SIM_OBJECT_PARAMS(ITB) 1338 1339 Param<int> size; 1340 1341END_DECLARE_SIM_OBJECT_PARAMS(ITB) 1342 --- 25 unchanged lines hidden (view full) --- 1368 1369 1370CREATE_SIM_OBJECT(DTB) 1371{ 1372 return new DTB(getInstanceName(), size); 1373} 1374 1375REGISTER_SIM_OBJECT("SparcDTB", DTB) |
1374} | |