tlb.cc (4000:9bf49767a9e4) tlb.cc (4007:8c3bfad8bb92)
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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894 assert(va == 0);
895 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS1));
896 break;
897 case ASI_IMMU_CTXT_NONZERO_CONFIG:
898 assert(va == 0);
899 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG));
900 break;
901 case ASI_SPARC_ERROR_STATUS_REG:
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 885 unchanged lines hidden (view full) ---

894 assert(va == 0);
895 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS1));
896 break;
897 case ASI_IMMU_CTXT_NONZERO_CONFIG:
898 assert(va == 0);
899 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG));
900 break;
901 case ASI_SPARC_ERROR_STATUS_REG:
902 warn("returning 0 for SPARC ERROR regsiter read\n");
903 pkt->set((uint64_t)0);
904 break;
905 case ASI_HYP_SCRATCHPAD:
906 case ASI_SCRATCHPAD:
907 pkt->set(tc->readMiscRegWithEffect(MISCREG_SCRATCHPAD_R0 + (va >> 3)));
908 break;
909 case ASI_IMMU:
910 switch (va) {

--- 436 unchanged lines hidden --- 		902 pkt->set((uint64_t)0);
903 break;
904 case ASI_HYP_SCRATCHPAD:
905 case ASI_SCRATCHPAD:
906 pkt->set(tc->readMiscRegWithEffect(MISCREG_SCRATCHPAD_R0 + (va >> 3)));
907 break;
908 case ASI_IMMU:
909 switch (va) {

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