tlb.cc (3979:3b0b08f60cdf) tlb.cc (3980:9bcb2a2e9bb8)
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Ali Saidi
29 */
30
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 14 unchanged lines hidden (view full) ---

23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Ali Saidi
29 */
30
31#include <cstring>
32
31#include "arch/sparc/asi.hh"
32#include "arch/sparc/miscregfile.hh"
33#include "arch/sparc/tlb.hh"
34#include "base/bitfield.hh"
35#include "base/trace.hh"
36#include "cpu/thread_context.hh"
37#include "cpu/base.hh"
38#include "mem/packet_access.hh"

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48 : SimObject(name), size(s), usedEntries(0), lastReplaced(0),
49 cacheValid(false)
50{
51 // To make this work you'll have to change the hypervisor and OS
52 if (size > 64)
53 fatal("SPARC T1 TLB registers don't support more than 64 TLB entries.");
54
55 tlb = new TlbEntry[size];
33#include "arch/sparc/asi.hh"
34#include "arch/sparc/miscregfile.hh"
35#include "arch/sparc/tlb.hh"
36#include "base/bitfield.hh"
37#include "base/trace.hh"
38#include "cpu/thread_context.hh"
39#include "cpu/base.hh"
40#include "mem/packet_access.hh"

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50 : SimObject(name), size(s), usedEntries(0), lastReplaced(0),
51 cacheValid(false)
52{
53 // To make this work you'll have to change the hypervisor and OS
54 if (size > 64)
55 fatal("SPARC T1 TLB registers don't support more than 64 TLB entries.");
56
57 tlb = new TlbEntry[size];
56 memset(tlb, 0, sizeof(TlbEntry) * size);
58 std::memset(tlb, 0, sizeof(TlbEntry) * size);
57
58 for (int x = 0; x < size; x++)
59 freeList.push_back(&tlb[x]);
60}
61
62void
63TLB::clearUsedBits()
64{

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165 // Update the last ently if their all locked
166 if (!new_entry) {
167 new_entry = &tlb[size-1];
168 }
169
170 freeList.remove(new_entry);
171 if (new_entry->valid && new_entry->used)
172 usedEntries--;
59
60 for (int x = 0; x < size; x++)
61 freeList.push_back(&tlb[x]);
62}
63
64void
65TLB::clearUsedBits()
66{

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167 // Update the last ently if their all locked
168 if (!new_entry) {
169 new_entry = &tlb[size-1];
170 }
171
172 freeList.remove(new_entry);
173 if (new_entry->valid && new_entry->used)
174 usedEntries--;
175 if (new_entry->valid)
176 lookupTable.erase(new_entry->range);
173
177
174 lookupTable.erase(new_entry->range);
175
178
176
177 assert(PTE.valid());
178 new_entry->range.va = va;
179 new_entry->range.size = PTE.size() - 1;
180 new_entry->range.partitionId = partition_id;
181 new_entry->range.contextId = context_id;
182 new_entry->range.real = real;
183 new_entry->pte = PTE;
184 new_entry->used = true;;

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572 ASI asi;
573 asi = (ASI)req->getAsi();
574 bool implicit = false;
575 bool hpriv = bits(tlbdata,0,0);
576
577 DPRINTF(TLB, "TLB: DTB Request to translate va=%#x size=%d asi=%#x\n",
578 vaddr, size, asi);
579
179 assert(PTE.valid());
180 new_entry->range.va = va;
181 new_entry->range.size = PTE.size() - 1;
182 new_entry->range.partitionId = partition_id;
183 new_entry->range.contextId = context_id;
184 new_entry->range.real = real;
185 new_entry->pte = PTE;
186 new_entry->used = true;;

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574 ASI asi;
575 asi = (ASI)req->getAsi();
576 bool implicit = false;
577 bool hpriv = bits(tlbdata,0,0);
578
579 DPRINTF(TLB, "TLB: DTB Request to translate va=%#x size=%d asi=%#x\n",
580 vaddr, size, asi);
581
582 if (lookupTable.size() != 64 - freeList.size())
583 panic("Lookup table size: %d tlb size: %d\n", lookupTable.size(),
584 freeList.size());
580 if (asi == ASI_IMPLICIT)
581 implicit = true;
582
583 if (hpriv && implicit) {
584 req->setPaddr(vaddr & PAddrImplMask);
585 return NoFault;
586 }
587

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586 implicit = true;
587
588 if (hpriv && implicit) {
589 req->setPaddr(vaddr & PAddrImplMask);
590 return NoFault;
591 }
592

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