tlb.cc (3926:c57925da8d38) tlb.cc (3928:9486450f013f)
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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544 if (real)
545 return new InstructionRealTranslationMiss;
546 else
547 return new FastInstructionAccessMMUMiss;
548 }
549
550 // were not priviledged accesing priv page
551 if (!priv && e->pte.priv()) {
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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544 if (real)
545 return new InstructionRealTranslationMiss;
546 else
547 return new FastInstructionAccessMMUMiss;
548 }
549
550 // were not priviledged accesing priv page
551 if (!priv && e->pte.priv()) {
552 writeTagAccess(tc, vaddr, context);
552 writeSfsr(tc, false, ct, false, PrivViolation, asi);
553 return new InstructionAccessException;
554 }
555
556 // cache translation date for next translation
557 cacheValid = true;
558 cacheState = tlbdata;
559 cacheEntry = e;

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587 if (hpriv && implicit) {
588 req->setPaddr(vaddr & PAddrImplMask);
589 return NoFault;
590 }
591
592 // Be fast if we can!
593 if (cacheValid && cacheState == tlbdata) {
594 if (cacheEntry[0] && cacheAsi[0] == asi && cacheEntry[0]->range.va < vaddr + size &&
553 writeSfsr(tc, false, ct, false, PrivViolation, asi);
554 return new InstructionAccessException;
555 }
556
557 // cache translation date for next translation
558 cacheValid = true;
559 cacheState = tlbdata;
560 cacheEntry = e;

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588 if (hpriv && implicit) {
589 req->setPaddr(vaddr & PAddrImplMask);
590 return NoFault;
591 }
592
593 // Be fast if we can!
594 if (cacheValid && cacheState == tlbdata) {
595 if (cacheEntry[0] && cacheAsi[0] == asi && cacheEntry[0]->range.va < vaddr + size &&
595 cacheEntry[0]->range.va + cacheEntry[0]->range.size > vaddr) {
596 cacheEntry[0]->range.va + cacheEntry[0]->range.size > vaddr &&
597 (!write || cacheEntry[0]->pte.writable())) {
596 req->setPaddr(cacheEntry[0]->pte.paddr() & ~(cacheEntry[0]->pte.size()-1) |
597 vaddr & cacheEntry[0]->pte.size()-1 );
598 return NoFault;
599 }
600 if (cacheEntry[1] && cacheAsi[1] == asi && cacheEntry[1]->range.va < vaddr + size &&
598 req->setPaddr(cacheEntry[0]->pte.paddr() & ~(cacheEntry[0]->pte.size()-1) |
599 vaddr & cacheEntry[0]->pte.size()-1 );
600 return NoFault;
601 }
602 if (cacheEntry[1] && cacheAsi[1] == asi && cacheEntry[1]->range.va < vaddr + size &&
601 cacheEntry[1]->range.va + cacheEntry[1]->range.size > vaddr) {
603 cacheEntry[1]->range.va + cacheEntry[1]->range.size > vaddr &&
604 (!write || cacheEntry[1]->pte.writable())) {
602 req->setPaddr(cacheEntry[1]->pte.paddr() & ~(cacheEntry[1]->pte.size()-1) |
603 vaddr & cacheEntry[1]->pte.size()-1 );
604 return NoFault;
605 }
606 }
607
608 bool red = bits(tlbdata,1,1);
609 bool priv = bits(tlbdata,2,2);

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721 DPRINTF(TLB, "TLB: DTB Failed to find matching TLB entry\n");
722 if (real)
723 return new DataRealTranslationMiss;
724 else
725 return new FastDataAccessMMUMiss;
726
727 }
728
605 req->setPaddr(cacheEntry[1]->pte.paddr() & ~(cacheEntry[1]->pte.size()-1) |
606 vaddr & cacheEntry[1]->pte.size()-1 );
607 return NoFault;
608 }
609 }
610
611 bool red = bits(tlbdata,1,1);
612 bool priv = bits(tlbdata,2,2);

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724 DPRINTF(TLB, "TLB: DTB Failed to find matching TLB entry\n");
725 if (real)
726 return new DataRealTranslationMiss;
727 else
728 return new FastDataAccessMMUMiss;
729
730 }
731
732 if (!priv && e->pte.priv()) {
733 writeTagAccess(tc, vaddr, context);
734 writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), PrivViolation, asi);
735 return new DataAccessException;
736 }
729
730 if (write && !e->pte.writable()) {
737
738 if (write && !e->pte.writable()) {
739 writeTagAccess(tc, vaddr, context);
731 writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), OtherFault, asi);
732 return new FastDataAccessProtection;
733 }
734
735 if (e->pte.nofault() && !AsiIsNoFault(asi)) {
740 writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), OtherFault, asi);
741 return new FastDataAccessProtection;
742 }
743
744 if (e->pte.nofault() && !AsiIsNoFault(asi)) {
745 writeTagAccess(tc, vaddr, context);
736 writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), LoadFromNfo, asi);
737 return new DataAccessException;
738 }
739
746 writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), LoadFromNfo, asi);
747 return new DataAccessException;
748 }
749
740 if (e->pte.sideffect())
741 req->setFlags(req->getFlags() | UNCACHEABLE);
742
743
744 if (!priv && e->pte.priv()) {
745 writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), PrivViolation, asi);
750 if (e->pte.sideffect() && AsiIsNoFault(asi)) {
751 writeTagAccess(tc, vaddr, context);
752 writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), SideEffect, asi);
746 return new DataAccessException;
747 }
748
753 return new DataAccessException;
754 }
755
756
757 if (e->pte.sideffect())
758 req->setFlags(req->getFlags() | UNCACHEABLE);
759
749 // cache translation date for next translation
750 cacheState = tlbdata;
751 if (!cacheValid) {
752 cacheEntry[1] = NULL;
753 cacheEntry[0] = NULL;
754 }
755
756 if (cacheEntry[0] != e && cacheEntry[1] != e) {

--- 537 unchanged lines hidden --- 		760 // cache translation date for next translation
761 cacheState = tlbdata;
762 if (!cacheValid) {
763 cacheEntry[1] = NULL;
764 cacheEntry[0] = NULL;
765 }
766
767 if (cacheEntry[0] != e && cacheEntry[1] != e) {

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