tlb.cc (3918:1f9a98d198e8) tlb.cc (3926:c57925da8d38)
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 14 unchanged lines hidden (view full) ---

23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Ali Saidi
29 */
30
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 14 unchanged lines hidden (view full) ---

23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Ali Saidi
29 */
30
31#include <cstring>
32
33#include "arch/sparc/asi.hh"
34#include "arch/sparc/miscregfile.hh"
35#include "arch/sparc/tlb.hh"
36#include "base/bitfield.hh"
37#include "base/trace.hh"
38#include "cpu/thread_context.hh"
39#include "cpu/base.hh"
40#include "mem/packet_access.hh"

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50 : SimObject(name), size(s), usedEntries(0), lastReplaced(0),
51 cacheValid(false)
52{
53 // To make this work you'll have to change the hypervisor and OS
54 if (size > 64)
55 fatal("SPARC T1 TLB registers don't support more than 64 TLB entries.");
56
57 tlb = new TlbEntry[size];
31#include "arch/sparc/asi.hh"
32#include "arch/sparc/miscregfile.hh"
33#include "arch/sparc/tlb.hh"
34#include "base/bitfield.hh"
35#include "base/trace.hh"
36#include "cpu/thread_context.hh"
37#include "cpu/base.hh"
38#include "mem/packet_access.hh"

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48 : SimObject(name), size(s), usedEntries(0), lastReplaced(0),
49 cacheValid(false)
50{
51 // To make this work you'll have to change the hypervisor and OS
52 if (size > 64)
53 fatal("SPARC T1 TLB registers don't support more than 64 TLB entries.");
54
55 tlb = new TlbEntry[size];
58 std::memset(tlb, 0, sizeof(TlbEntry) * size);
56 memset(tlb, 0, sizeof(TlbEntry) * size);
59
60 for (int x = 0; x < size; x++)
61 freeList.push_back(&tlb[x]);
62}
63
64void
65TLB::clearUsedBits()
66{

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82
83
84 MapIter i;
85 TlbEntry *new_entry = NULL;
86// TlbRange tr;
87 int x;
88
89 cacheValid = false;
57
58 for (int x = 0; x < size; x++)
59 freeList.push_back(&tlb[x]);
60}
61
62void
63TLB::clearUsedBits()
64{

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80
81
82 MapIter i;
83 TlbEntry *new_entry = NULL;
84// TlbRange tr;
85 int x;
86
87 cacheValid = false;
88 va &= ~(PTE.size()-1);
90 /* tr.va = va;
91 tr.size = PTE.size() - 1;
92 tr.contextId = context_id;
93 tr.partitionId = partition_id;
94 tr.real = real;
95*/
96
97 DPRINTF(TLB, "TLB: Inserting TLB Entry; va=%#x pa=%#x pid=%d cid=%d r=%d entryid=%d\n",

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411 sfsr |= ft << 7;
412 sfsr |= asi << 16;
413 tc->setMiscRegWithEffect(reg, sfsr);
414}
415
416void
417TLB::writeTagAccess(ThreadContext *tc, int reg, Addr va, int context)
418{
89 /* tr.va = va;
90 tr.size = PTE.size() - 1;
91 tr.contextId = context_id;
92 tr.partitionId = partition_id;
93 tr.real = real;
94*/
95
96 DPRINTF(TLB, "TLB: Inserting TLB Entry; va=%#x pa=%#x pid=%d cid=%d r=%d entryid=%d\n",

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410 sfsr |= ft << 7;
411 sfsr |= asi << 16;
412 tc->setMiscRegWithEffect(reg, sfsr);
413}
414
415void
416TLB::writeTagAccess(ThreadContext *tc, int reg, Addr va, int context)
417{
418 DPRINTF(TLB, "TLB: Writing Tag Access: va: %#X ctx: %#X value: %#X\n",
419 va, context, mbits(va, 63,13) | mbits(context,12,0));
420
419 tc->setMiscRegWithEffect(reg, mbits(va, 63,13) | mbits(context,12,0));
420}
421
422void
423ITB::writeSfsr(ThreadContext *tc, bool write, ContextType ct,
424 bool se, FaultTypes ft, int asi)
425{
426 DPRINTF(TLB, "TLB: ITB Fault: w=%d ct=%d ft=%d asi=%d\n",

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533 e = lookup(vaddr, part_id, true);
534 real = true;
535 context = 0;
536 } else {
537 e = lookup(vaddr, part_id, false, context);
538 }
539
540 if (e == NULL || !e->valid) {
421 tc->setMiscRegWithEffect(reg, mbits(va, 63,13) | mbits(context,12,0));
422}
423
424void
425ITB::writeSfsr(ThreadContext *tc, bool write, ContextType ct,
426 bool se, FaultTypes ft, int asi)
427{
428 DPRINTF(TLB, "TLB: ITB Fault: w=%d ct=%d ft=%d asi=%d\n",

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535 e = lookup(vaddr, part_id, true);
536 real = true;
537 context = 0;
538 } else {
539 e = lookup(vaddr, part_id, false, context);
540 }
541
542 if (e == NULL || !e->valid) {
541 tc->setMiscReg(MISCREG_MMU_ITLB_TAG_ACCESS,
542 vaddr & ~BytesInPageMask | context);
543 writeTagAccess(tc, vaddr, context);
543 if (real)
544 return new InstructionRealTranslationMiss;
545 else
546 return new FastInstructionAccessMMUMiss;
547 }
548
549 // were not priviledged accesing priv page
550 if (!priv && e->pte.priv()) {

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607 bool red = bits(tlbdata,1,1);
608 bool priv = bits(tlbdata,2,2);
609 bool addr_mask = bits(tlbdata,3,3);
610 bool lsu_dm = bits(tlbdata,5,5);
611
612 int part_id = bits(tlbdata,15,8);
613 int tl = bits(tlbdata,18,16);
614 int pri_context = bits(tlbdata,47,32);
544 if (real)
545 return new InstructionRealTranslationMiss;
546 else
547 return new FastInstructionAccessMMUMiss;
548 }
549
550 // were not priviledged accesing priv page
551 if (!priv && e->pte.priv()) {

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608 bool red = bits(tlbdata,1,1);
609 bool priv = bits(tlbdata,2,2);
610 bool addr_mask = bits(tlbdata,3,3);
611 bool lsu_dm = bits(tlbdata,5,5);
612
613 int part_id = bits(tlbdata,15,8);
614 int tl = bits(tlbdata,18,16);
615 int pri_context = bits(tlbdata,47,32);
615 int sec_context = bits(tlbdata,47,32);
616 int sec_context = bits(tlbdata,63,48);
616
617 bool real = false;
618 ContextType ct = Primary;
619 int context = 0;
620
621 TlbEntry *e;
622
623 DPRINTF(TLB, "TLB: priv:%d hpriv:%d red:%d lsudm:%d part_id: %#X\n",

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628 asi = ASI_N;
629 ct = Nucleus;
630 context = 0;
631 } else {
632 asi = ASI_P;
633 ct = Primary;
634 context = pri_context;
635 }
617
618 bool real = false;
619 ContextType ct = Primary;
620 int context = 0;
621
622 TlbEntry *e;
623
624 DPRINTF(TLB, "TLB: priv:%d hpriv:%d red:%d lsudm:%d part_id: %#X\n",

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629 asi = ASI_N;
630 ct = Nucleus;
631 context = 0;
632 } else {
633 asi = ASI_P;
634 ct = Primary;
635 context = pri_context;
636 }
636 } else if (!hpriv && !red) {
637 if (tl > 0 || AsiIsNucleus(asi)) {
638 ct = Nucleus;
639 context = 0;
640 } else if (AsiIsSecondary(asi)) {
641 ct = Secondary;
642 context = sec_context;
643 } else {
644 context = pri_context;
645 ct = Primary; //???
646 }
647
637 } else {
648 // We need to check for priv level/asi priv
638 // We need to check for priv level/asi priv
649 if (!priv && !AsiIsUnPriv(asi)) {
639 if (!priv && !hpriv && !AsiIsUnPriv(asi)) {
650 // It appears that context should be Nucleus in these cases?
651 writeSfr(tc, vaddr, write, Nucleus, false, IllegalAsi, asi);
652 return new PrivilegedAction;
653 }
640 // It appears that context should be Nucleus in these cases?
641 writeSfr(tc, vaddr, write, Nucleus, false, IllegalAsi, asi);
642 return new PrivilegedAction;
643 }
654 if (priv && AsiIsHPriv(asi)) {
644
645 if (!hpriv && AsiIsHPriv(asi)) {
655 writeSfr(tc, vaddr, write, Nucleus, false, IllegalAsi, asi);
656 return new DataAccessException;
657 }
658
646 writeSfr(tc, vaddr, write, Nucleus, false, IllegalAsi, asi);
647 return new DataAccessException;
648 }
649
650 if (AsiIsPrimary(asi)) {
651 context = pri_context;
652 ct = Primary;
653 } else if (AsiIsSecondary(asi)) {
654 context = sec_context;
655 ct = Secondary;
656 } else if (AsiIsNucleus(asi)) {
657 ct = Nucleus;
658 context = 0;
659 } else { // ????
660 ct = Primary;
661 context = pri_context;
662 }
659 }
663 }
660 if (asi == ASI_P || asi == ASI_LDTX_P) {
661 ct = Primary;
662 context = pri_context;
663 goto continueDtbFlow;
664 }
665
664
666 if (!implicit) {
665 if (!implicit && asi != ASI_P && asi != ASI_S) {
667 if (AsiIsLittle(asi))
668 panic("Little Endian ASIs not supported\n");
669 if (AsiIsBlock(asi))
670 panic("Block ASIs not supported\n");
671 if (AsiIsNoFault(asi))
672 panic("No Fault ASIs not supported\n");
666 if (AsiIsLittle(asi))
667 panic("Little Endian ASIs not supported\n");
668 if (AsiIsBlock(asi))
669 panic("Block ASIs not supported\n");
670 if (AsiIsNoFault(asi))
671 panic("No Fault ASIs not supported\n");
673 if (!write && (asi == ASI_QUAD_LDD || asi == ASI_LDTX_REAL))
674 goto continueDtbFlow;
675
672
676 if (AsiIsTwin(asi))
677 panic("Twin ASIs not supported\n");
678 if (AsiIsPartialStore(asi))
679 panic("Partial Store ASIs not supported\n");
680 if (AsiIsInterrupt(asi))
681 panic("Interrupt ASIs not supported\n");
682
683 if (AsiIsMmu(asi))
684 goto handleMmuRegAccess;
685 if (AsiIsScratchPad(asi))
686 goto handleScratchRegAccess;
687 if (AsiIsQueue(asi))
688 goto handleQueueRegAccess;
689 if (AsiIsSparcError(asi))
690 goto handleSparcErrorRegAccess;
691
673 if (AsiIsPartialStore(asi))
674 panic("Partial Store ASIs not supported\n");
675 if (AsiIsInterrupt(asi))
676 panic("Interrupt ASIs not supported\n");
677
678 if (AsiIsMmu(asi))
679 goto handleMmuRegAccess;
680 if (AsiIsScratchPad(asi))
681 goto handleScratchRegAccess;
682 if (AsiIsQueue(asi))
683 goto handleQueueRegAccess;
684 if (AsiIsSparcError(asi))
685 goto handleSparcErrorRegAccess;
686
692 if (!AsiIsReal(asi) && !AsiIsNucleus(asi))
687 if (!AsiIsReal(asi) && !AsiIsNucleus(asi) && !AsiIsAsIfUser(asi) &&
688 !AsiIsTwin(asi))
693 panic("Accessing ASI %#X. Should we?\n", asi);
694 }
695
689 panic("Accessing ASI %#X. Should we?\n", asi);
690 }
691
696continueDtbFlow:
697 // If the asi is unaligned trap
698 if (vaddr & size-1) {
699 writeSfr(tc, vaddr, false, ct, false, OtherFault, asi);
700 return new MemAddressNotAligned;
701 }
702
703 if (addr_mask)
704 vaddr = vaddr & VAddrAMask;
705
706 if (!validVirtualAddress(vaddr, addr_mask)) {
707 writeSfr(tc, vaddr, false, ct, true, VaOutOfRange, asi);
708 return new DataAccessException;
709 }
710
711
692 // If the asi is unaligned trap
693 if (vaddr & size-1) {
694 writeSfr(tc, vaddr, false, ct, false, OtherFault, asi);
695 return new MemAddressNotAligned;
696 }
697
698 if (addr_mask)
699 vaddr = vaddr & VAddrAMask;
700
701 if (!validVirtualAddress(vaddr, addr_mask)) {
702 writeSfr(tc, vaddr, false, ct, true, VaOutOfRange, asi);
703 return new DataAccessException;
704 }
705
706
712 if ((!lsu_dm && !hpriv) || AsiIsReal(asi)) {
707 if ((!lsu_dm && !hpriv && !red) || AsiIsReal(asi)) {
713 real = true;
714 context = 0;
715 };
716
717 if (hpriv && (implicit || (!AsiIsAsIfUser(asi) && !AsiIsReal(asi)))) {
718 req->setPaddr(vaddr & PAddrImplMask);
719 return NoFault;
720 }
721
722 e = lookup(vaddr, part_id, real, context);
723
724 if (e == NULL || !e->valid) {
708 real = true;
709 context = 0;
710 };
711
712 if (hpriv && (implicit || (!AsiIsAsIfUser(asi) && !AsiIsReal(asi)))) {
713 req->setPaddr(vaddr & PAddrImplMask);
714 return NoFault;
715 }
716
717 e = lookup(vaddr, part_id, real, context);
718
719 if (e == NULL || !e->valid) {
725 tc->setMiscReg(MISCREG_MMU_DTLB_TAG_ACCESS,
726 vaddr & ~BytesInPageMask | context);
720 writeTagAccess(tc, vaddr, context);
727 DPRINTF(TLB, "TLB: DTB Failed to find matching TLB entry\n");
728 if (real)
729 return new DataRealTranslationMiss;
730 else
731 return new FastDataAccessMMUMiss;
732
733 }
734

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890 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS1));
891 break;
892 case ASI_IMMU_CTXT_NONZERO_CONFIG:
893 assert(va == 0);
894 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG));
895 break;
896 case ASI_SPARC_ERROR_STATUS_REG:
897 warn("returning 0 for SPARC ERROR regsiter read\n");
721 DPRINTF(TLB, "TLB: DTB Failed to find matching TLB entry\n");
722 if (real)
723 return new DataRealTranslationMiss;
724 else
725 return new FastDataAccessMMUMiss;
726
727 }
728

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884 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS1));
885 break;
886 case ASI_IMMU_CTXT_NONZERO_CONFIG:
887 assert(va == 0);
888 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG));
889 break;
890 case ASI_SPARC_ERROR_STATUS_REG:
891 warn("returning 0 for SPARC ERROR regsiter read\n");
898 pkt->set(0);
892 pkt->set((uint64_t)0);
899 break;
900 case ASI_HYP_SCRATCHPAD:
901 case ASI_SCRATCHPAD:
902 pkt->set(tc->readMiscRegWithEffect(MISCREG_SCRATCHPAD_R0 + (va >> 3)));
903 break;
904 case ASI_IMMU:
905 switch (va) {
906 case 0x0:

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960 cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG);
961 } else {
962 tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS1);
963 cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG);
964 }
965 data = mbits(tsbtemp,63,13);
966 if (bits(tsbtemp,12,12))
967 data |= ULL(1) << (13+bits(tsbtemp,3,0));
893 break;
894 case ASI_HYP_SCRATCHPAD:
895 case ASI_SCRATCHPAD:
896 pkt->set(tc->readMiscRegWithEffect(MISCREG_SCRATCHPAD_R0 + (va >> 3)));
897 break;
898 case ASI_IMMU:
899 switch (va) {
900 case 0x0:

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954 cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG);
955 } else {
956 tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS1);
957 cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG);
958 }
959 data = mbits(tsbtemp,63,13);
960 if (bits(tsbtemp,12,12))
961 data |= ULL(1) << (13+bits(tsbtemp,3,0));
968 data |= temp >> (9 + bits(cnftemp,2,0) * 3) &
962 data |= temp >> (9 + bits(cnftemp,10,8) * 3) &
969 mbits((uint64_t)-1ll,12+bits(tsbtemp,3,0), 4);
970 pkt->set(data);
971 break;
972 case ASI_IMMU_TSB_PS0_PTR_REG:
973 temp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS);
974 if (bits(temp,12,0) == 0) {
975 tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS0);
976 cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG);

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990 cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG);
991 } else {
992 tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS1);
993 cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG);
994 }
995 data = mbits(tsbtemp,63,13);
996 if (bits(tsbtemp,12,12))
997 data |= ULL(1) << (13+bits(tsbtemp,3,0));
963 mbits((uint64_t)-1ll,12+bits(tsbtemp,3,0), 4);
964 pkt->set(data);
965 break;
966 case ASI_IMMU_TSB_PS0_PTR_REG:
967 temp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS);
968 if (bits(temp,12,0) == 0) {
969 tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS0);
970 cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG);

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984 cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG);
985 } else {
986 tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS1);
987 cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG);
988 }
989 data = mbits(tsbtemp,63,13);
990 if (bits(tsbtemp,12,12))
991 data |= ULL(1) << (13+bits(tsbtemp,3,0));
998 data |= temp >> (9 + bits(cnftemp,2,0) * 3) &
992 data |= temp >> (9 + bits(cnftemp,10,8) * 3) &
999 mbits((uint64_t)-1ll,12+bits(tsbtemp,3,0), 4);
1000 pkt->set(data);
1001 break;
1002
1003 default:
1004doMmuReadError:
1005 panic("need to impl DTB::doMmuRegRead() got asi=%#x, va=%#x\n",
1006 (uint32_t)asi, va);

--- 102 unchanged lines hidden (view full) ---

1109 tc->setMiscRegWithEffect(MISCREG_SCRATCHPAD_R0 + (va >> 3), data);
1110 break;
1111 case ASI_IMMU:
1112 switch (va) {
1113 case 0x18:
1114 tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_SFSR, data);
1115 break;
1116 case 0x30:
993 mbits((uint64_t)-1ll,12+bits(tsbtemp,3,0), 4);
994 pkt->set(data);
995 break;
996
997 default:
998doMmuReadError:
999 panic("need to impl DTB::doMmuRegRead() got asi=%#x, va=%#x\n",
1000 (uint32_t)asi, va);

--- 102 unchanged lines hidden (view full) ---

1103 tc->setMiscRegWithEffect(MISCREG_SCRATCHPAD_R0 + (va >> 3), data);
1104 break;
1105 case ASI_IMMU:
1106 switch (va) {
1107 case 0x18:
1108 tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_SFSR, data);
1109 break;
1110 case 0x30:
1111 sext<59>(bits(data, 59,0));
1117 tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS, data);
1118 break;
1119 default:
1120 goto doMmuWriteError;
1121 }
1122 break;
1123 case ASI_ITLB_DATA_ACCESS_REG:
1124 entry_insert = bits(va, 8,3);

--- 58 unchanged lines hidden (view full) ---

1183 }
1184 break;
1185 case ASI_DMMU:
1186 switch (va) {
1187 case 0x18:
1188 tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_SFSR, data);
1189 break;
1190 case 0x30:
1112 tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS, data);
1113 break;
1114 default:
1115 goto doMmuWriteError;
1116 }
1117 break;
1118 case ASI_ITLB_DATA_ACCESS_REG:
1119 entry_insert = bits(va, 8,3);

--- 58 unchanged lines hidden (view full) ---

1178 }
1179 break;
1180 case ASI_DMMU:
1181 switch (va) {
1182 case 0x18:
1183 tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_SFSR, data);
1184 break;
1185 case 0x30:
1186 sext<59>(bits(data, 59,0));
1191 tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS, data);
1192 break;
1193 case 0x80:
1194 tc->setMiscRegWithEffect(MISCREG_MMU_PART_ID, data);
1195 break;
1196 default:
1197 goto doMmuWriteError;
1198 }

--- 99 unchanged lines hidden --- 		1187 tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS, data);
1188 break;
1189 case 0x80:
1190 tc->setMiscRegWithEffect(MISCREG_MMU_PART_ID, data);
1191 break;
1192 default:
1193 goto doMmuWriteError;
1194 }

--- 99 unchanged lines hidden ---