tlb.cc (3915:1e183d6dea0b) tlb.cc (3916:3f394f5bc533)
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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410 sfsr |= ft << 7;
411 sfsr |= asi << 16;
412 tc->setMiscRegWithEffect(reg, sfsr);
413}
414
415void
416TLB::writeTagAccess(ThreadContext *tc, int reg, Addr va, int context)
417{
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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410 sfsr |= ft << 7;
411 sfsr |= asi << 16;
412 tc->setMiscRegWithEffect(reg, sfsr);
413}
414
415void
416TLB::writeTagAccess(ThreadContext *tc, int reg, Addr va, int context)
417{
418 DPRINTF(TLB, "TLB: Writing Tag Access: va: %#X ctx: %#X value: %#X\n",
419 va, context, mbits(va, 63,13) | mbits(context,12,0));
420
418 tc->setMiscRegWithEffect(reg, mbits(va, 63,13) | mbits(context,12,0));
419}
420
421void
422ITB::writeSfsr(ThreadContext *tc, bool write, ContextType ct,
423 bool se, FaultTypes ft, int asi)
424{
425 DPRINTF(TLB, "TLB: ITB Fault: w=%d ct=%d ft=%d asi=%d\n",

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532 e = lookup(vaddr, part_id, true);
533 real = true;
534 context = 0;
535 } else {
536 e = lookup(vaddr, part_id, false, context);
537 }
538
539 if (e == NULL || !e->valid) {
421 tc->setMiscRegWithEffect(reg, mbits(va, 63,13) | mbits(context,12,0));
422}
423
424void
425ITB::writeSfsr(ThreadContext *tc, bool write, ContextType ct,
426 bool se, FaultTypes ft, int asi)
427{
428 DPRINTF(TLB, "TLB: ITB Fault: w=%d ct=%d ft=%d asi=%d\n",

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535 e = lookup(vaddr, part_id, true);
536 real = true;
537 context = 0;
538 } else {
539 e = lookup(vaddr, part_id, false, context);
540 }
541
542 if (e == NULL || !e->valid) {
540 tc->setMiscReg(MISCREG_MMU_ITLB_TAG_ACCESS,
541 vaddr & ~BytesInPageMask | context);
543 writeTagAccess(tc, vaddr, context);
542 if (real)
543 return new InstructionRealTranslationMiss;
544 else
545 return new FastInstructionAccessMMUMiss;
546 }
547
548 // were not priviledged accesing priv page
549 if (!priv && e->pte.priv()) {

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606 bool red = bits(tlbdata,1,1);
607 bool priv = bits(tlbdata,2,2);
608 bool addr_mask = bits(tlbdata,3,3);
609 bool lsu_dm = bits(tlbdata,5,5);
610
611 int part_id = bits(tlbdata,15,8);
612 int tl = bits(tlbdata,18,16);
613 int pri_context = bits(tlbdata,47,32);
544 if (real)
545 return new InstructionRealTranslationMiss;
546 else
547 return new FastInstructionAccessMMUMiss;
548 }
549
550 // were not priviledged accesing priv page
551 if (!priv && e->pte.priv()) {

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608 bool red = bits(tlbdata,1,1);
609 bool priv = bits(tlbdata,2,2);
610 bool addr_mask = bits(tlbdata,3,3);
611 bool lsu_dm = bits(tlbdata,5,5);
612
613 int part_id = bits(tlbdata,15,8);
614 int tl = bits(tlbdata,18,16);
615 int pri_context = bits(tlbdata,47,32);
614 int sec_context = bits(tlbdata,47,32);
616 int sec_context = bits(tlbdata,63,48);
615
616 bool real = false;
617 ContextType ct = Primary;
618 int context = 0;
619
620 TlbEntry *e;
621
622 DPRINTF(TLB, "TLB: priv:%d hpriv:%d red:%d lsudm:%d part_id: %#X\n",

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718 if (hpriv && (implicit || (!AsiIsAsIfUser(asi) && !AsiIsReal(asi)))) {
719 req->setPaddr(vaddr & PAddrImplMask);
720 return NoFault;
721 }
722
723 e = lookup(vaddr, part_id, real, context);
724
725 if (e == NULL || !e->valid) {
617
618 bool real = false;
619 ContextType ct = Primary;
620 int context = 0;
621
622 TlbEntry *e;
623
624 DPRINTF(TLB, "TLB: priv:%d hpriv:%d red:%d lsudm:%d part_id: %#X\n",

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720 if (hpriv && (implicit || (!AsiIsAsIfUser(asi) && !AsiIsReal(asi)))) {
721 req->setPaddr(vaddr & PAddrImplMask);
722 return NoFault;
723 }
724
725 e = lookup(vaddr, part_id, real, context);
726
727 if (e == NULL || !e->valid) {
726 tc->setMiscReg(MISCREG_MMU_DTLB_TAG_ACCESS,
727 vaddr & ~BytesInPageMask | context);
728 writeTagAccess(tc, vaddr, context);
728 DPRINTF(TLB, "TLB: DTB Failed to find matching TLB entry\n");
729 if (real)
730 return new DataRealTranslationMiss;
731 else
732 return new FastDataAccessMMUMiss;
733
734 }
735

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1110 tc->setMiscRegWithEffect(MISCREG_SCRATCHPAD_R0 + (va >> 3), data);
1111 break;
1112 case ASI_IMMU:
1113 switch (va) {
1114 case 0x18:
1115 tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_SFSR, data);
1116 break;
1117 case 0x30:
729 DPRINTF(TLB, "TLB: DTB Failed to find matching TLB entry\n");
730 if (real)
731 return new DataRealTranslationMiss;
732 else
733 return new FastDataAccessMMUMiss;
734
735 }
736

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1111 tc->setMiscRegWithEffect(MISCREG_SCRATCHPAD_R0 + (va >> 3), data);
1112 break;
1113 case ASI_IMMU:
1114 switch (va) {
1115 case 0x18:
1116 tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_SFSR, data);
1117 break;
1118 case 0x30:
1119 sext<59>(bits(data, 59,0));
1118 tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS, data);
1119 break;
1120 default:
1121 goto doMmuWriteError;
1122 }
1123 break;
1124 case ASI_ITLB_DATA_ACCESS_REG:
1125 entry_insert = bits(va, 8,3);

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1184 }
1185 break;
1186 case ASI_DMMU:
1187 switch (va) {
1188 case 0x18:
1189 tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_SFSR, data);
1190 break;
1191 case 0x30:
1120 tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS, data);
1121 break;
1122 default:
1123 goto doMmuWriteError;
1124 }
1125 break;
1126 case ASI_ITLB_DATA_ACCESS_REG:
1127 entry_insert = bits(va, 8,3);

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1186 }
1187 break;
1188 case ASI_DMMU:
1189 switch (va) {
1190 case 0x18:
1191 tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_SFSR, data);
1192 break;
1193 case 0x30:
1194 sext<59>(bits(data, 59,0));
1192 tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS, data);
1193 break;
1194 case 0x80:
1195 tc->setMiscRegWithEffect(MISCREG_MMU_PART_ID, data);
1196 break;
1197 default:
1198 goto doMmuWriteError;
1199 }

--- 99 unchanged lines hidden --- 		1195 tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS, data);
1196 break;
1197 case 0x80:
1198 tc->setMiscRegWithEffect(MISCREG_MMU_PART_ID, data);
1199 break;
1200 default:
1201 goto doMmuWriteError;
1202 }

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