tlb.cc (3902:f09fe9c1e609) tlb.cc (3906:4cf7d8d42349)
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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871 pkt->set(tc->readMiscRegWithEffect(MISCREG_SCRATCHPAD_R0 + (va >> 3)));
872 break;
873 case ASI_IMMU:
874 switch (va) {
875 case 0x0:
876 temp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS);
877 pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48);
878 break;
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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871 pkt->set(tc->readMiscRegWithEffect(MISCREG_SCRATCHPAD_R0 + (va >> 3)));
872 break;
873 case ASI_IMMU:
874 switch (va) {
875 case 0x0:
876 temp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS);
877 pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48);
878 break;
879 case 0x18:
880 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_SFSR));
881 break;
879 case 0x30:
880 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS));
881 break;
882 default:
883 goto doMmuReadError;
884 }
885 break;
886 case ASI_DMMU:
887 switch (va) {
888 case 0x0:
889 temp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS);
890 pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48);
891 break;
882 case 0x30:
883 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS));
884 break;
885 default:
886 goto doMmuReadError;
887 }
888 break;
889 case ASI_DMMU:
890 switch (va) {
891 case 0x0:
892 temp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS);
893 pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48);
894 break;
895 case 0x18:
896 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_SFSR));
897 break;
898 case 0x20:
899 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_SFAR));
900 break;
892 case 0x30:
893 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS));
894 break;
895 case 0x80:
896 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID));
897 break;
898 default:
899 goto doMmuReadError;

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1065 warn("Ignoring write to SPARC ERROR regsiter\n");
1066 break;
1067 case ASI_HYP_SCRATCHPAD:
1068 case ASI_SCRATCHPAD:
1069 tc->setMiscRegWithEffect(MISCREG_SCRATCHPAD_R0 + (va >> 3), data);
1070 break;
1071 case ASI_IMMU:
1072 switch (va) {
901 case 0x30:
902 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS));
903 break;
904 case 0x80:
905 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID));
906 break;
907 default:
908 goto doMmuReadError;

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1074 warn("Ignoring write to SPARC ERROR regsiter\n");
1075 break;
1076 case ASI_HYP_SCRATCHPAD:
1077 case ASI_SCRATCHPAD:
1078 tc->setMiscRegWithEffect(MISCREG_SCRATCHPAD_R0 + (va >> 3), data);
1079 break;
1080 case ASI_IMMU:
1081 switch (va) {
1082 case 0x18:
1083 tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_SFSR, data);
1084 break;
1073 case 0x30:
1074 tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS, data);
1075 break;
1076 default:
1077 goto doMmuWriteError;
1078 }
1079 break;
1080 case ASI_ITLB_DATA_ACCESS_REG:

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1136 tc->getITBPtr()->demapAll(part_id);
1137 break;
1138 default:
1139 panic("Invalid type for IMMU demap\n");
1140 }
1141 break;
1142 case ASI_DMMU:
1143 switch (va) {
1085 case 0x30:
1086 tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS, data);
1087 break;
1088 default:
1089 goto doMmuWriteError;
1090 }
1091 break;
1092 case ASI_ITLB_DATA_ACCESS_REG:

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1148 tc->getITBPtr()->demapAll(part_id);
1149 break;
1150 default:
1151 panic("Invalid type for IMMU demap\n");
1152 }
1153 break;
1154 case ASI_DMMU:
1155 switch (va) {
1156 case 0x18:
1157 tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_SFSR, data);
1158 break;
1144 case 0x30:
1145 tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS, data);
1146 break;
1147 case 0x80:
1148 tc->setMiscRegWithEffect(MISCREG_MMU_PART_ID, data);
1149 break;
1150 default:
1151 goto doMmuWriteError;

--- 100 unchanged lines hidden --- 		1159 case 0x30:
1160 tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS, data);
1161 break;
1162 case 0x80:
1163 tc->setMiscRegWithEffect(MISCREG_MMU_PART_ID, data);
1164 break;
1165 default:
1166 goto doMmuWriteError;

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