tlb.cc (3856:8815ad4f0661) tlb.cc (3863:adf3ddd4bcde)
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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119 if (i->second->used) {
120 i->second->used = false;
121 usedEntries--;
122 }
123 DPRINTF(TLB, "TLB: Found conflicting entry, deleting it\n");
124 lookupTable.erase(i);
125 }
126
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 110 unchanged lines hidden (view full) ---

119 if (i->second->used) {
120 i->second->used = false;
121 usedEntries--;
122 }
123 DPRINTF(TLB, "TLB: Found conflicting entry, deleting it\n");
124 lookupTable.erase(i);
125 }
126
127 lookupTable.insert(new_entry->range, new_entry);;
127 i = lookupTable.insert(new_entry->range, new_entry);
128 assert(i != lookupTable.end());
128
129 // If all entries have there used bit set, clear it on them all, but the
130 // one we just inserted
131 if (usedEntries == size) {
132 clearUsedBits();
133 new_entry->used = true;
134 usedEntries++;
135 }

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143 MapIter i;
144 TlbRange tr;
145 TlbEntry *t;
146
147 DPRINTF(TLB, "TLB: Looking up entry va=%#x pid=%d cid=%d r=%d\n",
148 va, partition_id, context_id, real);
149 // Assemble full address structure
150 tr.va = va;
129
130 // If all entries have there used bit set, clear it on them all, but the
131 // one we just inserted
132 if (usedEntries == size) {
133 clearUsedBits();
134 new_entry->used = true;
135 usedEntries++;
136 }

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144 MapIter i;
145 TlbRange tr;
146 TlbEntry *t;
147
148 DPRINTF(TLB, "TLB: Looking up entry va=%#x pid=%d cid=%d r=%d\n",
149 va, partition_id, context_id, real);
150 // Assemble full address structure
151 tr.va = va;
151 tr.size = va + MachineBytes;
152 tr.size = MachineBytes;
152 tr.contextId = context_id;
153 tr.partitionId = partition_id;
154 tr.real = real;
155
156 // Try to find the entry
157 i = lookupTable.find(tr);
158 if (i == lookupTable.end()) {
159 DPRINTF(TLB, "TLB: No valid entry found\n");

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175 }
176
177 return t;
178}
179
180void
181TLB::dumpAll()
182{
153 tr.contextId = context_id;
154 tr.partitionId = partition_id;
155 tr.real = real;
156
157 // Try to find the entry
158 i = lookupTable.find(tr);
159 if (i == lookupTable.end()) {
160 DPRINTF(TLB, "TLB: No valid entry found\n");

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176 }
177
178 return t;
179}
180
181void
182TLB::dumpAll()
183{
184 MapIter i;
183 for (int x = 0; x < size; x++) {
184 if (tlb[x].valid) {
185 DPRINTFN("%4d: %#2x:%#2x %c %#4x %#8x %#8x %#16x\n",
186 x, tlb[x].range.partitionId, tlb[x].range.contextId,
187 tlb[x].range.real ? 'R' : ' ', tlb[x].range.size,
188 tlb[x].range.va, tlb[x].pte.paddr(), tlb[x].pte());
189 }
190 }
191}
192
193void
194TLB::demapPage(Addr va, int partition_id, bool real, int context_id)
195{
196 TlbRange tr;
197 MapIter i;
198
185 for (int x = 0; x < size; x++) {
186 if (tlb[x].valid) {
187 DPRINTFN("%4d: %#2x:%#2x %c %#4x %#8x %#8x %#16x\n",
188 x, tlb[x].range.partitionId, tlb[x].range.contextId,
189 tlb[x].range.real ? 'R' : ' ', tlb[x].range.size,
190 tlb[x].range.va, tlb[x].pte.paddr(), tlb[x].pte());
191 }
192 }
193}
194
195void
196TLB::demapPage(Addr va, int partition_id, bool real, int context_id)
197{
198 TlbRange tr;
199 MapIter i;
200
201 DPRINTF(IPR, "TLB: Demapping Page va=%#x pid=%#d cid=%d r=%d\n",
202 va, partition_id, context_id, real);
203
199 cacheValid = false;
200
201 // Assemble full address structure
202 tr.va = va;
204 cacheValid = false;
205
206 // Assemble full address structure
207 tr.va = va;
203 tr.size = va + MachineBytes;
208 tr.size = MachineBytes;
204 tr.contextId = context_id;
205 tr.partitionId = partition_id;
206 tr.real = real;
207
208 // Demap any entry that conflicts
209 i = lookupTable.find(tr);
210 if (i != lookupTable.end()) {
209 tr.contextId = context_id;
210 tr.partitionId = partition_id;
211 tr.real = real;
212
213 // Demap any entry that conflicts
214 i = lookupTable.find(tr);
215 if (i != lookupTable.end()) {
216 DPRINTF(IPR, "TLB: Demapped page\n");
211 i->second->valid = false;
212 if (i->second->used) {
213 i->second->used = false;
214 usedEntries--;
215 }
216 lookupTable.erase(i);
217 }
218}
219
220void
221TLB::demapContext(int partition_id, int context_id)
222{
223 int x;
217 i->second->valid = false;
218 if (i->second->used) {
219 i->second->used = false;
220 usedEntries--;
221 }
222 lookupTable.erase(i);
223 }
224}
225
226void
227TLB::demapContext(int partition_id, int context_id)
228{
229 int x;
230 DPRINTF(IPR, "TLB: Demapping Context pid=%#d cid=%d\n",
231 partition_id, context_id);
224 cacheValid = false;
225 for (x = 0; x < size; x++) {
226 if (tlb[x].range.contextId == context_id &&
227 tlb[x].range.partitionId == partition_id) {
228 tlb[x].valid = false;
229 if (tlb[x].used) {
230 tlb[x].used = false;
231 usedEntries--;
232 }
233 lookupTable.erase(tlb[x].range);
234 }
235 }
236}
237
238void
239TLB::demapAll(int partition_id)
240{
241 int x;
232 cacheValid = false;
233 for (x = 0; x < size; x++) {
234 if (tlb[x].range.contextId == context_id &&
235 tlb[x].range.partitionId == partition_id) {
236 tlb[x].valid = false;
237 if (tlb[x].used) {
238 tlb[x].used = false;
239 usedEntries--;
240 }
241 lookupTable.erase(tlb[x].range);
242 }
243 }
244}
245
246void
247TLB::demapAll(int partition_id)
248{
249 int x;
250 DPRINTF(TLB, "TLB: Demapping All pid=%#d\n", partition_id);
242 cacheValid = false;
243 for (x = 0; x < size; x++) {
244 if (!tlb[x].pte.locked() && tlb[x].range.partitionId == partition_id) {
245 tlb[x].valid = false;
246 if (tlb[x].used) {
247 tlb[x].used = false;
248 usedEntries--;
249 }

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879 ASI asi = (ASI)pkt->req->getAsi();
880
881 Addr ta_insert;
882 Addr va_insert;
883 Addr ct_insert;
884 int part_insert;
885 int entry_insert = -1;
886 bool real_insert;
251 cacheValid = false;
252 for (x = 0; x < size; x++) {
253 if (!tlb[x].pte.locked() && tlb[x].range.partitionId == partition_id) {
254 tlb[x].valid = false;
255 if (tlb[x].used) {
256 tlb[x].used = false;
257 usedEntries--;
258 }

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888 ASI asi = (ASI)pkt->req->getAsi();
889
890 Addr ta_insert;
891 Addr va_insert;
892 Addr ct_insert;
893 int part_insert;
894 int entry_insert = -1;
895 bool real_insert;
896 bool ignore;
897 int part_id;
898 int ctx_id;
887 PageTableEntry pte;
888
889 DPRINTF(IPR, "Memory Mapped IPR Write: asi=%#X a=%#x d=%#X\n",
890 (uint32_t)asi, va, data);
891
892 switch (asi) {
893 case ASI_LSU_CONTROL_REG:
894 assert(va == 0);

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998 va_insert = mbits(ta_insert, 63,13);
999 ct_insert = mbits(ta_insert, 12,0);
1000 part_insert = tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID);
1001 real_insert = bits(va, 9,9);
1002 pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v :
1003 PageTableEntry::sun4u);
1004 insert(va_insert, part_insert, ct_insert, real_insert, pte, entry_insert);
1005 break;
899 PageTableEntry pte;
900
901 DPRINTF(IPR, "Memory Mapped IPR Write: asi=%#X a=%#x d=%#X\n",
902 (uint32_t)asi, va, data);
903
904 switch (asi) {
905 case ASI_LSU_CONTROL_REG:
906 assert(va == 0);

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1010 va_insert = mbits(ta_insert, 63,13);
1011 ct_insert = mbits(ta_insert, 12,0);
1012 part_insert = tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID);
1013 real_insert = bits(va, 9,9);
1014 pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v :
1015 PageTableEntry::sun4u);
1016 insert(va_insert, part_insert, ct_insert, real_insert, pte, entry_insert);
1017 break;
1018 case ASI_IMMU_DEMAP:
1019 ignore = false;
1020 ctx_id = -1;
1021 part_id = tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID);
1022 switch (bits(va,5,4)) {
1023 case 0:
1024 ctx_id = tc->readMiscRegWithEffect(MISCREG_MMU_P_CONTEXT);
1025 break;
1026 case 1:
1027 ignore = true;
1028 break;
1029 case 3:
1030 ctx_id = 0;
1031 break;
1032 default:
1033 ignore = true;
1034 }
1035
1036 switch(bits(va,7,6)) {
1037 case 0: // demap page
1038 if (!ignore)
1039 tc->getITBPtr()->demapPage(mbits(va,63,13), part_id,
1040 bits(va,9,9), ctx_id);
1041 break;
1042 case 1: //demap context
1043 if (!ignore)
1044 tc->getITBPtr()->demapContext(part_id, ctx_id);
1045 break;
1046 case 2:
1047 tc->getITBPtr()->demapAll(part_id);
1048 break;
1049 default:
1050 panic("Invalid type for IMMU demap\n");
1051 }
1052 break;
1006 case ASI_DMMU:
1007 switch (va) {
1008 case 0x30:
1009 tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS, data);
1010 break;
1011 case 0x80:
1012 tc->setMiscRegWithEffect(MISCREG_MMU_PART_ID, data);
1013 break;
1014 default:
1015 goto doMmuWriteError;
1016 }
1017 break;
1053 case ASI_DMMU:
1054 switch (va) {
1055 case 0x30:
1056 tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS, data);
1057 break;
1058 case 0x80:
1059 tc->setMiscRegWithEffect(MISCREG_MMU_PART_ID, data);
1060 break;
1061 default:
1062 goto doMmuWriteError;
1063 }
1064 break;
1065 case ASI_DMMU_DEMAP:
1066 ignore = false;
1067 ctx_id = -1;
1068 part_id = tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID);
1069 switch (bits(va,5,4)) {
1070 case 0:
1071 ctx_id = tc->readMiscRegWithEffect(MISCREG_MMU_P_CONTEXT);
1072 break;
1073 case 1:
1074 ctx_id = tc->readMiscRegWithEffect(MISCREG_MMU_S_CONTEXT);
1075 break;
1076 case 3:
1077 ctx_id = 0;
1078 break;
1079 default:
1080 ignore = true;
1081 }
1082
1083 switch(bits(va,7,6)) {
1084 case 0: // demap page
1085 if (!ignore)
1086 demapPage(mbits(va,63,13), part_id, bits(va,9,9), ctx_id);
1087 break;
1088 case 1: //demap context
1089 if (!ignore)
1090 demapContext(part_id, ctx_id);
1091 break;
1092 case 2:
1093 demapAll(part_id);
1094 break;
1095 default:
1096 panic("Invalid type for IMMU demap\n");
1097 }
1098 break;
1018 default:
1019doMmuWriteError:
1020 panic("need to impl DTB::doMmuRegWrite() got asi=%#x, va=%#x d=%#x\n",
1021 (uint32_t)pkt->req->getAsi(), pkt->getAddr(), data);
1022 }
1023 pkt->result = Packet::Success;
1024 return tc->getCpuPtr()->cycles(1);
1025}

--- 56 unchanged lines hidden --- 		1099 default:
1100doMmuWriteError:
1101 panic("need to impl DTB::doMmuRegWrite() got asi=%#x, va=%#x d=%#x\n",
1102 (uint32_t)pkt->req->getAsi(), pkt->getAddr(), data);
1103 }
1104 pkt->result = Packet::Success;
1105 return tc->getCpuPtr()->cycles(1);
1106}

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