tlb.cc (3826:e35adf01a285) tlb.cc (3832:49c95a73e29c)
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 432 unchanged lines hidden (view full) ---

441 bool hpriv = hpstate >> 2 & 0x1;
442 bool red = hpstate >> 5 >> 0x1;
443 bool addr_mask = pstate >> 3 & 0x1;
444 bool priv = pstate >> 2 & 0x1;
445 bool implicit = false;
446 bool real = false;
447 Addr vaddr = req->getVaddr();
448 Addr size = req->getSize();
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 432 unchanged lines hidden (view full) ---

441 bool hpriv = hpstate >> 2 & 0x1;
442 bool red = hpstate >> 5 >> 0x1;
443 bool addr_mask = pstate >> 3 & 0x1;
444 bool priv = pstate >> 2 & 0x1;
445 bool implicit = false;
446 bool real = false;
447 Addr vaddr = req->getVaddr();
448 Addr size = req->getSize();
449 ContextType ct;
450 int context;
449 ContextType ct = Primary;
450 int context = 0;
451 ASI asi;
452
453 TlbEntry *e;
454
455 asi = (ASI)req->getAsi();
456 DPRINTF(TLB, "TLB: DTB Request to translate va=%#x size=%d asi=%#x\n",
457 vaddr, size, asi);
458 DPRINTF(TLB, "TLB: pstate: %#X hpstate: %#X lsudm: %#X part_id: %#X\n",

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503
504 if (!implicit) {
505 if (AsiIsLittle(asi))
506 panic("Little Endian ASIs not supported\n");
507 if (AsiIsBlock(asi))
508 panic("Block ASIs not supported\n");
509 if (AsiIsNoFault(asi))
510 panic("No Fault ASIs not supported\n");
451 ASI asi;
452
453 TlbEntry *e;
454
455 asi = (ASI)req->getAsi();
456 DPRINTF(TLB, "TLB: DTB Request to translate va=%#x size=%d asi=%#x\n",
457 vaddr, size, asi);
458 DPRINTF(TLB, "TLB: pstate: %#X hpstate: %#X lsudm: %#X part_id: %#X\n",

--- 44 unchanged lines hidden (view full) ---

503
504 if (!implicit) {
505 if (AsiIsLittle(asi))
506 panic("Little Endian ASIs not supported\n");
507 if (AsiIsBlock(asi))
508 panic("Block ASIs not supported\n");
509 if (AsiIsNoFault(asi))
510 panic("No Fault ASIs not supported\n");
511 if (write && asi == ASI_LDTX_P)
512 // block init store (like write hint64)
513 goto continueDtbFlow;
511 if (AsiIsTwin(asi))
512 panic("Twin ASIs not supported\n");
513 if (AsiIsPartialStore(asi))
514 panic("Partial Store ASIs not supported\n");
515 if (AsiIsInterrupt(asi))
516 panic("Interrupt ASIs not supported\n");
517
518 if (AsiIsMmu(asi))

--- 440 unchanged lines hidden --- 		514 if (AsiIsTwin(asi))
515 panic("Twin ASIs not supported\n");
516 if (AsiIsPartialStore(asi))
517 panic("Partial Store ASIs not supported\n");
518 if (AsiIsInterrupt(asi))
519 panic("Interrupt ASIs not supported\n");
520
521 if (AsiIsMmu(asi))

--- 440 unchanged lines hidden ---