tlb.cc (3824:8900576818d7) | tlb.cc (3825:9b5e6c4d3ecb) |
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1/* 2 * Copyright (c) 2001-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 314 unchanged lines hidden (view full) --- 323 int context; 324 ContextType ct; 325 int asi; 326 bool real = false; 327 TlbEntry *e; 328 329 DPRINTF(TLB, "TLB: ITB Request to translate va=%#x size=%d\n", 330 vaddr, req->getSize()); | 1/* 2 * Copyright (c) 2001-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 314 unchanged lines hidden (view full) --- 323 int context; 324 ContextType ct; 325 int asi; 326 bool real = false; 327 TlbEntry *e; 328 329 DPRINTF(TLB, "TLB: ITB Request to translate va=%#x size=%d\n", 330 vaddr, req->getSize()); |
331 DPRINTF(TLB, "TLB: pstate: %#X hpstate: %#X lsudm: %#X part_id: %#X\n", 332 pstate, hpstate, lsuIm, part_id); |
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331 332 assert(req->getAsi() == ASI_IMPLICIT); 333 334 if (tl > 0) { 335 asi = ASI_N; 336 ct = Nucleus; 337 context = 0; 338 } else { --- 16 unchanged lines hidden (view full) --- 355 if (addr_mask) 356 vaddr = vaddr & VAddrAMask; 357 358 if (!validVirtualAddress(vaddr, addr_mask)) { 359 writeSfsr(tc, false, ct, false, VaOutOfRange, asi); 360 return new InstructionAccessException; 361 } 362 | 333 334 assert(req->getAsi() == ASI_IMPLICIT); 335 336 if (tl > 0) { 337 asi = ASI_N; 338 ct = Nucleus; 339 context = 0; 340 } else { --- 16 unchanged lines hidden (view full) --- 357 if (addr_mask) 358 vaddr = vaddr & VAddrAMask; 359 360 if (!validVirtualAddress(vaddr, addr_mask)) { 361 writeSfsr(tc, false, ct, false, VaOutOfRange, asi); 362 return new InstructionAccessException; 363 } 364 |
363 if (lsuIm) { | 365 if (!lsuIm) { |
364 e = lookup(req->getVaddr(), part_id, true); 365 real = true; 366 context = 0; 367 } else { 368 e = lookup(vaddr, part_id, false, context); 369 } 370 371 if (e == NULL || !e->valid) { --- 39 unchanged lines hidden (view full) --- 411 int context; 412 ASI asi; 413 414 TlbEntry *e; 415 416 asi = (ASI)req->getAsi(); 417 DPRINTF(TLB, "TLB: DTB Request to translate va=%#x size=%d asi=%#x\n", 418 vaddr, size, asi); | 366 e = lookup(req->getVaddr(), part_id, true); 367 real = true; 368 context = 0; 369 } else { 370 e = lookup(vaddr, part_id, false, context); 371 } 372 373 if (e == NULL || !e->valid) { --- 39 unchanged lines hidden (view full) --- 413 int context; 414 ASI asi; 415 416 TlbEntry *e; 417 418 asi = (ASI)req->getAsi(); 419 DPRINTF(TLB, "TLB: DTB Request to translate va=%#x size=%d asi=%#x\n", 420 vaddr, size, asi); |
419 | 421 DPRINTF(TLB, "TLB: pstate: %#X hpstate: %#X lsudm: %#X part_id: %#X\n", 422 pstate, hpstate, lsuDm, part_id); |
420 if (asi == ASI_IMPLICIT) 421 implicit = true; 422 423 if (implicit) { 424 if (tl > 0) { 425 asi = ASI_N; 426 ct = Nucleus; 427 context = 0; --- 56 unchanged lines hidden (view full) --- 484 panic("Interrupt ASIs not supported\n"); 485 486 if (AsiIsMmu(asi)) 487 goto handleMmuRegAccess; 488 if (AsiIsScratchPad(asi)) 489 goto handleScratchRegAccess; 490 if (AsiIsQueue(asi)) 491 goto handleQueueRegAccess; | 423 if (asi == ASI_IMPLICIT) 424 implicit = true; 425 426 if (implicit) { 427 if (tl > 0) { 428 asi = ASI_N; 429 ct = Nucleus; 430 context = 0; --- 56 unchanged lines hidden (view full) --- 487 panic("Interrupt ASIs not supported\n"); 488 489 if (AsiIsMmu(asi)) 490 goto handleMmuRegAccess; 491 if (AsiIsScratchPad(asi)) 492 goto handleScratchRegAccess; 493 if (AsiIsQueue(asi)) 494 goto handleQueueRegAccess; |
495 if (AsiIsSparcError(asi)) 496 goto handleSparcErrorRegAccess; |
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492 493 if (!AsiIsReal(asi) && !AsiIsNucleus(asi)) 494 panic("Accessing ASI %#X. Should we?\n", asi); 495 } 496 497 if ((!lsuDm && !hpriv) || AsiIsReal(asi)) { 498 real = true; 499 context = 0; --- 55 unchanged lines hidden (view full) --- 555 return new PrivilegedAction; 556 } 557 if (priv && vaddr & 0xF || vaddr > 0x3f8 || vaddr < 0x3c0) { 558 writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi); 559 return new DataAccessException; 560 } 561 goto regAccessOk; 562 | 497 498 if (!AsiIsReal(asi) && !AsiIsNucleus(asi)) 499 panic("Accessing ASI %#X. Should we?\n", asi); 500 } 501 502 if ((!lsuDm && !hpriv) || AsiIsReal(asi)) { 503 real = true; 504 context = 0; --- 55 unchanged lines hidden (view full) --- 560 return new PrivilegedAction; 561 } 562 if (priv && vaddr & 0xF || vaddr > 0x3f8 || vaddr < 0x3c0) { 563 writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi); 564 return new DataAccessException; 565 } 566 goto regAccessOk; 567 |
568handleSparcErrorRegAccess: 569 if (!hpriv) { 570 if (priv) { 571 writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi); 572 return new DataAccessException; 573 } else { 574 writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi); 575 return new PrivilegedAction; 576 } 577 } 578 goto regAccessOk; 579 580 |
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563regAccessOk: 564handleMmuRegAccess: 565 DPRINTF(TLB, "TLB: DTB Translating MM IPR access\n"); 566 req->setMmapedIpr(true); 567 req->setPaddr(req->getVaddr()); 568 return NoFault; 569}; 570 --- 99 unchanged lines hidden (view full) --- 670 671Tick 672DTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt) 673{ 674 uint64_t data = gtoh(pkt->get<uint64_t>()); 675 Addr va = pkt->getAddr(); 676 ASI asi = (ASI)pkt->req->getAsi(); 677 | 581regAccessOk: 582handleMmuRegAccess: 583 DPRINTF(TLB, "TLB: DTB Translating MM IPR access\n"); 584 req->setMmapedIpr(true); 585 req->setPaddr(req->getVaddr()); 586 return NoFault; 587}; 588 --- 99 unchanged lines hidden (view full) --- 688 689Tick 690DTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt) 691{ 692 uint64_t data = gtoh(pkt->get<uint64_t>()); 693 Addr va = pkt->getAddr(); 694 ASI asi = (ASI)pkt->req->getAsi(); 695 |
678 DPRINTF(IPR, "Memory Mapped IPR Write: asi=#%X a=%#x d=%#X\n", | 696 DPRINTF(IPR, "Memory Mapped IPR Write: asi=%#X a=%#x d=%#X\n", |
679 (uint32_t)asi, va, data); 680 681 switch (asi) { 682 case ASI_LSU_CONTROL_REG: 683 assert(va == 0); 684 tc->setMiscRegWithEffect(MISCREG_MMU_LSU_CTRL, data); 685 break; 686 case ASI_MMU: --- 4 unchanged lines hidden (view full) --- 691 case 0x10: 692 tc->setMiscRegWithEffect(MISCREG_MMU_S_CONTEXT, data); 693 break; 694 default: 695 goto doMmuWriteError; 696 } 697 break; 698 case ASI_QUEUE: | 697 (uint32_t)asi, va, data); 698 699 switch (asi) { 700 case ASI_LSU_CONTROL_REG: 701 assert(va == 0); 702 tc->setMiscRegWithEffect(MISCREG_MMU_LSU_CTRL, data); 703 break; 704 case ASI_MMU: --- 4 unchanged lines hidden (view full) --- 709 case 0x10: 710 tc->setMiscRegWithEffect(MISCREG_MMU_S_CONTEXT, data); 711 break; 712 default: 713 goto doMmuWriteError; 714 } 715 break; 716 case ASI_QUEUE: |
699 assert(mbits(va,13,6) == va); | 717 assert(mbits(data,13,6) == data); |
700 tc->setMiscRegWithEffect(MISCREG_QUEUE_CPU_MONDO_HEAD + 701 (va >> 4) - 0x3c, data); 702 break; 703 case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0: 704 assert(va == 0); 705 tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS0, data); 706 break; 707 case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1: --- 35 unchanged lines hidden (view full) --- 743 case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1: 744 assert(va == 0); 745 tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS1, data); 746 break; 747 case ASI_IMMU_CTXT_NONZERO_CONFIG: 748 assert(va == 0); 749 tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG, data); 750 break; | 718 tc->setMiscRegWithEffect(MISCREG_QUEUE_CPU_MONDO_HEAD + 719 (va >> 4) - 0x3c, data); 720 break; 721 case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0: 722 assert(va == 0); 723 tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS0, data); 724 break; 725 case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1: --- 35 unchanged lines hidden (view full) --- 761 case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1: 762 assert(va == 0); 763 tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS1, data); 764 break; 765 case ASI_IMMU_CTXT_NONZERO_CONFIG: 766 assert(va == 0); 767 tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG, data); 768 break; |
769 case ASI_SPARC_ERROR_EN_REG: 770 case ASI_SPARC_ERROR_STATUS_REG: 771 warn("Ignoring write to SPARC ERROR regsiter\n"); 772 break; |
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751 case ASI_HYP_SCRATCHPAD: 752 case ASI_SCRATCHPAD: 753 tc->setMiscRegWithEffect(MISCREG_SCRATCHPAD_R0 + (va >> 3), data); 754 break; 755 case ASI_DMMU: 756 switch (va) { 757 case 0x80: 758 tc->setMiscRegWithEffect(MISCREG_MMU_PART_ID, data); --- 69 unchanged lines hidden --- | 773 case ASI_HYP_SCRATCHPAD: 774 case ASI_SCRATCHPAD: 775 tc->setMiscRegWithEffect(MISCREG_SCRATCHPAD_R0 + (va >> 3), data); 776 break; 777 case ASI_DMMU: 778 switch (va) { 779 case 0x80: 780 tc->setMiscRegWithEffect(MISCREG_MMU_PART_ID, data); --- 69 unchanged lines hidden --- |