tlb.cc (3823:1c8f87aa103e) tlb.cc (3824:8900576818d7)
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Ali Saidi
29 */
30
31#include "arch/sparc/asi.hh"
32#include "arch/sparc/miscregfile.hh"
33#include "arch/sparc/tlb.hh"
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Ali Saidi
29 */
30
31#include "arch/sparc/asi.hh"
32#include "arch/sparc/miscregfile.hh"
33#include "arch/sparc/tlb.hh"
34#include "base/bitfield.hh"
34#include "base/trace.hh"
35#include "cpu/thread_context.hh"
36#include "cpu/base.hh"
37#include "mem/packet_access.hh"
38#include "mem/request.hh"
39#include "sim/builder.hh"
40
41/* @todo remove some of the magic constants. -- ali

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474 if (AsiIsBlock(asi))
475 panic("Block ASIs not supported\n");
476 if (AsiIsNoFault(asi))
477 panic("No Fault ASIs not supported\n");
478 if (AsiIsTwin(asi))
479 panic("Twin ASIs not supported\n");
480 if (AsiIsPartialStore(asi))
481 panic("Partial Store ASIs not supported\n");
35#include "base/trace.hh"
36#include "cpu/thread_context.hh"
37#include "cpu/base.hh"
38#include "mem/packet_access.hh"
39#include "mem/request.hh"
40#include "sim/builder.hh"
41
42/* @todo remove some of the magic constants. -- ali

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475 if (AsiIsBlock(asi))
476 panic("Block ASIs not supported\n");
477 if (AsiIsNoFault(asi))
478 panic("No Fault ASIs not supported\n");
479 if (AsiIsTwin(asi))
480 panic("Twin ASIs not supported\n");
481 if (AsiIsPartialStore(asi))
482 panic("Partial Store ASIs not supported\n");
483 if (AsiIsInterrupt(asi))
484 panic("Interrupt ASIs not supported\n");
482
483 if (AsiIsMmu(asi))
484 goto handleMmuRegAccess;
485 if (AsiIsScratchPad(asi))
486 goto handleScratchRegAccess;
485
486 if (AsiIsMmu(asi))
487 goto handleMmuRegAccess;
488 if (AsiIsScratchPad(asi))
489 goto handleScratchRegAccess;
490 if (AsiIsQueue(asi))
491 goto handleQueueRegAccess;
487
488 if (!AsiIsReal(asi) && !AsiIsNucleus(asi))
489 panic("Accessing ASI %#X. Should we?\n", asi);
490 }
491
492 if ((!lsuDm && !hpriv) || AsiIsReal(asi)) {
493 real = true;
494 context = 0;

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537 return NoFault;
538 /** Normal flow ends here. */
539
540handleScratchRegAccess:
541 if (vaddr > 0x38 || (vaddr >= 0x20 && vaddr < 0x30 && !hpriv)) {
542 writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi);
543 return new DataAccessException;
544 }
492
493 if (!AsiIsReal(asi) && !AsiIsNucleus(asi))
494 panic("Accessing ASI %#X. Should we?\n", asi);
495 }
496
497 if ((!lsuDm && !hpriv) || AsiIsReal(asi)) {
498 real = true;
499 context = 0;

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542 return NoFault;
543 /** Normal flow ends here. */
544
545handleScratchRegAccess:
546 if (vaddr > 0x38 || (vaddr >= 0x20 && vaddr < 0x30 && !hpriv)) {
547 writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi);
548 return new DataAccessException;
549 }
550 goto regAccessOk;
551
552handleQueueRegAccess:
553 if (!priv && !hpriv) {
554 writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi);
555 return new PrivilegedAction;
556 }
557 if (priv && vaddr & 0xF || vaddr > 0x3f8 || vaddr < 0x3c0) {
558 writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi);
559 return new DataAccessException;
560 }
561 goto regAccessOk;
562
563regAccessOk:
545handleMmuRegAccess:
546 DPRINTF(TLB, "TLB: DTB Translating MM IPR access\n");
547 req->setMmapedIpr(true);
548 req->setPaddr(req->getVaddr());
549 return NoFault;
550};
551
552Tick

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570 break;
571 case 0x10:
572 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_S_CONTEXT));
573 break;
574 default:
575 goto doMmuReadError;
576 }
577 break;
564handleMmuRegAccess:
565 DPRINTF(TLB, "TLB: DTB Translating MM IPR access\n");
566 req->setMmapedIpr(true);
567 req->setPaddr(req->getVaddr());
568 return NoFault;
569};
570
571Tick

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589 break;
590 case 0x10:
591 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_S_CONTEXT));
592 break;
593 default:
594 goto doMmuReadError;
595 }
596 break;
597 case ASI_QUEUE:
598 pkt->set(tc->readMiscRegWithEffect(MISCREG_QUEUE_CPU_MONDO_HEAD +
599 (va >> 4) - 0x3c));
600 break;
578 case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0:
579 assert(va == 0);
580 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS0));
581 break;
582 case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1:
583 assert(va == 0);
584 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS1));
585 break;

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667 break;
668 case 0x10:
669 tc->setMiscRegWithEffect(MISCREG_MMU_S_CONTEXT, data);
670 break;
671 default:
672 goto doMmuWriteError;
673 }
674 break;
601 case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0:
602 assert(va == 0);
603 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS0));
604 break;
605 case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1:
606 assert(va == 0);
607 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS1));
608 break;

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690 break;
691 case 0x10:
692 tc->setMiscRegWithEffect(MISCREG_MMU_S_CONTEXT, data);
693 break;
694 default:
695 goto doMmuWriteError;
696 }
697 break;
698 case ASI_QUEUE:
699 assert(mbits(va,13,6) == va);
700 tc->setMiscRegWithEffect(MISCREG_QUEUE_CPU_MONDO_HEAD +
701 (va >> 4) - 0x3c, data);
702 break;
675 case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0:
676 assert(va == 0);
677 tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS0, data);
678 break;
679 case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1:
680 assert(va == 0);
681 tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS1, data);
682 break;

--- 117 unchanged lines hidden --- 		703 case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0:
704 assert(va == 0);
705 tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS0, data);
706 break;
707 case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1:
708 assert(va == 0);
709 tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS1, data);
710 break;

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