tlb.cc (3811:ee71d61347f1) tlb.cc (3823:1c8f87aa103e)
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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28 * Authors: Ali Saidi
29 */
30
31#include "arch/sparc/asi.hh"
32#include "arch/sparc/miscregfile.hh"
33#include "arch/sparc/tlb.hh"
34#include "base/trace.hh"
35#include "cpu/thread_context.hh"
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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28 * Authors: Ali Saidi
29 */
30
31#include "arch/sparc/asi.hh"
32#include "arch/sparc/miscregfile.hh"
33#include "arch/sparc/tlb.hh"
34#include "base/trace.hh"
35#include "cpu/thread_context.hh"
36#include "cpu/base.hh"
37#include "mem/packet_access.hh"
38#include "mem/request.hh"
36#include "sim/builder.hh"
37
38/* @todo remove some of the magic constants. -- ali
39 * */
40namespace SparcISA
41{
42
43TLB::TLB(const std::string &name, int s)

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422 ct = Nucleus;
423 context = 0;
424 } else {
425 asi = ASI_P;
426 ct = Primary;
427 context = tc->readMiscReg(MISCREG_MMU_P_CONTEXT);
428 }
429 } else if (!hpriv && !red) {
39#include "sim/builder.hh"
40
41/* @todo remove some of the magic constants. -- ali
42 * */
43namespace SparcISA
44{
45
46TLB::TLB(const std::string &name, int s)

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425 ct = Nucleus;
426 context = 0;
427 } else {
428 asi = ASI_P;
429 ct = Primary;
430 context = tc->readMiscReg(MISCREG_MMU_P_CONTEXT);
431 }
432 } else if (!hpriv && !red) {
430 if (tl > 0) {
433 if (tl > 0 || AsiIsNucleus(asi)) {
431 ct = Nucleus;
432 context = 0;
433 } else if (AsiIsSecondary(asi)) {
434 ct = Secondary;
435 context = tc->readMiscReg(MISCREG_MMU_S_CONTEXT);
436 } else {
437 context = tc->readMiscReg(MISCREG_MMU_P_CONTEXT);
438 ct = Primary; //???

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471 if (AsiIsBlock(asi))
472 panic("Block ASIs not supported\n");
473 if (AsiIsNoFault(asi))
474 panic("No Fault ASIs not supported\n");
475 if (AsiIsTwin(asi))
476 panic("Twin ASIs not supported\n");
477 if (AsiIsPartialStore(asi))
478 panic("Partial Store ASIs not supported\n");
434 ct = Nucleus;
435 context = 0;
436 } else if (AsiIsSecondary(asi)) {
437 ct = Secondary;
438 context = tc->readMiscReg(MISCREG_MMU_S_CONTEXT);
439 } else {
440 context = tc->readMiscReg(MISCREG_MMU_P_CONTEXT);
441 ct = Primary; //???

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474 if (AsiIsBlock(asi))
475 panic("Block ASIs not supported\n");
476 if (AsiIsNoFault(asi))
477 panic("No Fault ASIs not supported\n");
478 if (AsiIsTwin(asi))
479 panic("Twin ASIs not supported\n");
480 if (AsiIsPartialStore(asi))
481 panic("Partial Store ASIs not supported\n");
482
479 if (AsiIsMmu(asi))
480 goto handleMmuRegAccess;
483 if (AsiIsMmu(asi))
484 goto handleMmuRegAccess;
481
482 if (AsiIsScratchPad(asi))
483 goto handleScratchRegAccess;
485 if (AsiIsScratchPad(asi))
486 goto handleScratchRegAccess;
487
488 if (!AsiIsReal(asi) && !AsiIsNucleus(asi))
489 panic("Accessing ASI %#X. Should we?\n", asi);
484 }
485
486 if ((!lsuDm && !hpriv) || AsiIsReal(asi)) {
487 real = true;
488 context = 0;
489 };
490
491 if (hpriv && (implicit || (!AsiIsAsIfUser(asi) && !AsiIsReal(asi)))) {

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541 req->setMmapedIpr(true);
542 req->setPaddr(req->getVaddr());
543 return NoFault;
544};
545
546Tick
547DTB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
548{
490 }
491
492 if ((!lsuDm && !hpriv) || AsiIsReal(asi)) {
493 real = true;
494 context = 0;
495 };
496
497 if (hpriv && (implicit || (!AsiIsAsIfUser(asi) && !AsiIsReal(asi)))) {

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547 req->setMmapedIpr(true);
548 req->setPaddr(req->getVaddr());
549 return NoFault;
550};
551
552Tick
553DTB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
554{
549 panic("need to implement DTB::doMmuRegRead()\n");
555 Addr va = pkt->getAddr();
556 ASI asi = (ASI)pkt->req->getAsi();
557
558 DPRINTF(IPR, "Memory Mapped IPR Read: asi=%#X a=%#x\n",
559 (uint32_t)pkt->req->getAsi(), pkt->getAddr());
560
561 switch (asi) {
562 case ASI_LSU_CONTROL_REG:
563 assert(va == 0);
564 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_LSU_CTRL));
565 break;
566 case ASI_MMU:
567 switch (va) {
568 case 0x8:
569 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_P_CONTEXT));
570 break;
571 case 0x10:
572 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_S_CONTEXT));
573 break;
574 default:
575 goto doMmuReadError;
576 }
577 break;
578 case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0:
579 assert(va == 0);
580 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS0));
581 break;
582 case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1:
583 assert(va == 0);
584 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS1));
585 break;
586 case ASI_DMMU_CTXT_ZERO_CONFIG:
587 assert(va == 0);
588 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG));
589 break;
590 case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0:
591 assert(va == 0);
592 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS0));
593 break;
594 case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1:
595 assert(va == 0);
596 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS1));
597 break;
598 case ASI_IMMU_CTXT_ZERO_CONFIG:
599 assert(va == 0);
600 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG));
601 break;
602 case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0:
603 assert(va == 0);
604 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS0));
605 break;
606 case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1:
607 assert(va == 0);
608 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS1));
609 break;
610 case ASI_DMMU_CTXT_NONZERO_CONFIG:
611 assert(va == 0);
612 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG));
613 break;
614 case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0:
615 assert(va == 0);
616 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS0));
617 break;
618 case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1:
619 assert(va == 0);
620 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS1));
621 break;
622 case ASI_IMMU_CTXT_NONZERO_CONFIG:
623 assert(va == 0);
624 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG));
625 break;
626 case ASI_HYP_SCRATCHPAD:
627 case ASI_SCRATCHPAD:
628 pkt->set(tc->readMiscRegWithEffect(MISCREG_SCRATCHPAD_R0 + (va >> 3)));
629 break;
630 case ASI_DMMU:
631 switch (va) {
632 case 0x80:
633 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID));
634 break;
635 default:
636 goto doMmuReadError;
637 }
638 break;
639 default:
640doMmuReadError:
641 panic("need to impl DTB::doMmuRegRead() got asi=%#x, va=%#x\n",
642 (uint32_t)asi, va);
643 }
644 pkt->result = Packet::Success;
645 return tc->getCpuPtr()->cycles(1);
550}
551
552Tick
553DTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
554{
646}
647
648Tick
649DTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
650{
555 panic("need to implement DTB::doMmuRegWrite()\n");
651 uint64_t data = gtoh(pkt->get<uint64_t>());
652 Addr va = pkt->getAddr();
653 ASI asi = (ASI)pkt->req->getAsi();
654
655 DPRINTF(IPR, "Memory Mapped IPR Write: asi=#%X a=%#x d=%#X\n",
656 (uint32_t)asi, va, data);
657
658 switch (asi) {
659 case ASI_LSU_CONTROL_REG:
660 assert(va == 0);
661 tc->setMiscRegWithEffect(MISCREG_MMU_LSU_CTRL, data);
662 break;
663 case ASI_MMU:
664 switch (va) {
665 case 0x8:
666 tc->setMiscRegWithEffect(MISCREG_MMU_P_CONTEXT, data);
667 break;
668 case 0x10:
669 tc->setMiscRegWithEffect(MISCREG_MMU_S_CONTEXT, data);
670 break;
671 default:
672 goto doMmuWriteError;
673 }
674 break;
675 case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0:
676 assert(va == 0);
677 tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS0, data);
678 break;
679 case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1:
680 assert(va == 0);
681 tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS1, data);
682 break;
683 case ASI_DMMU_CTXT_ZERO_CONFIG:
684 assert(va == 0);
685 tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG, data);
686 break;
687 case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0:
688 assert(va == 0);
689 tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS0, data);
690 break;
691 case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1:
692 assert(va == 0);
693 tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS1, data);
694 break;
695 case ASI_IMMU_CTXT_ZERO_CONFIG:
696 assert(va == 0);
697 tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG, data);
698 break;
699 case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0:
700 assert(va == 0);
701 tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS0, data);
702 break;
703 case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1:
704 assert(va == 0);
705 tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS1, data);
706 break;
707 case ASI_DMMU_CTXT_NONZERO_CONFIG:
708 assert(va == 0);
709 tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG, data);
710 break;
711 case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0:
712 assert(va == 0);
713 tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS0, data);
714 break;
715 case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1:
716 assert(va == 0);
717 tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS1, data);
718 break;
719 case ASI_IMMU_CTXT_NONZERO_CONFIG:
720 assert(va == 0);
721 tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG, data);
722 break;
723 case ASI_HYP_SCRATCHPAD:
724 case ASI_SCRATCHPAD:
725 tc->setMiscRegWithEffect(MISCREG_SCRATCHPAD_R0 + (va >> 3), data);
726 break;
727 case ASI_DMMU:
728 switch (va) {
729 case 0x80:
730 tc->setMiscRegWithEffect(MISCREG_MMU_PART_ID, data);
731 break;
732 default:
733 goto doMmuWriteError;
734 }
735 break;
736 default:
737doMmuWriteError:
738 panic("need to impl DTB::doMmuRegWrite() got asi=%#x, va=%#x d=%#x\n",
739 (uint32_t)pkt->req->getAsi(), pkt->getAddr(), data);
740 }
741 pkt->result = Packet::Success;
742 return tc->getCpuPtr()->cycles(1);
556}
557
558void
559TLB::serialize(std::ostream &os)
560{
561 panic("Need to implement serialize tlb for SPARC\n");
562}
563

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744
745void
746TLB::serialize(std::ostream &os)
747{
748 panic("Need to implement serialize tlb for SPARC\n");
749}
750

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