tlb.cc (12749:223c83ed9979) tlb.cc (13231:c6c133f9e007)
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 857 unchanged lines hidden (view full) ---

866 DPRINTF(IPR, "Memory Mapped IPR Read: asi=%#X a=%#x\n",
867 (uint32_t)pkt->req->getArchFlags(), pkt->getAddr());
868
869 TLB *itb = dynamic_cast<TLB *>(tc->getITBPtr());
870
871 switch (asi) {
872 case ASI_LSU_CONTROL_REG:
873 assert(va == 0);
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 857 unchanged lines hidden (view full) ---

866 DPRINTF(IPR, "Memory Mapped IPR Read: asi=%#X a=%#x\n",
867 (uint32_t)pkt->req->getArchFlags(), pkt->getAddr());
868
869 TLB *itb = dynamic_cast<TLB *>(tc->getITBPtr());
870
871 switch (asi) {
872 case ASI_LSU_CONTROL_REG:
873 assert(va == 0);
874 pkt->set(tc->readMiscReg(MISCREG_MMU_LSU_CTRL));
874 pkt->setBE(tc->readMiscReg(MISCREG_MMU_LSU_CTRL));
875 break;
876 case ASI_MMU:
877 switch (va) {
878 case 0x8:
875 break;
876 case ASI_MMU:
877 switch (va) {
878 case 0x8:
879 pkt->set(tc->readMiscReg(MISCREG_MMU_P_CONTEXT));
879 pkt->setBE(tc->readMiscReg(MISCREG_MMU_P_CONTEXT));
880 break;
881 case 0x10:
880 break;
881 case 0x10:
882 pkt->set(tc->readMiscReg(MISCREG_MMU_S_CONTEXT));
882 pkt->setBE(tc->readMiscReg(MISCREG_MMU_S_CONTEXT));
883 break;
884 default:
885 goto doMmuReadError;
886 }
887 break;
888 case ASI_QUEUE:
883 break;
884 default:
885 goto doMmuReadError;
886 }
887 break;
888 case ASI_QUEUE:
889 pkt->set(tc->readMiscReg(MISCREG_QUEUE_CPU_MONDO_HEAD +
889 pkt->setBE(tc->readMiscReg(MISCREG_QUEUE_CPU_MONDO_HEAD +
890 (va >> 4) - 0x3c));
891 break;
892 case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0:
893 assert(va == 0);
890 (va >> 4) - 0x3c));
891 break;
892 case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0:
893 assert(va == 0);
894 pkt->set(c0_tsb_ps0);
894 pkt->setBE(c0_tsb_ps0);
895 break;
896 case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1:
897 assert(va == 0);
895 break;
896 case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1:
897 assert(va == 0);
898 pkt->set(c0_tsb_ps1);
898 pkt->setBE(c0_tsb_ps1);
899 break;
900 case ASI_DMMU_CTXT_ZERO_CONFIG:
901 assert(va == 0);
899 break;
900 case ASI_DMMU_CTXT_ZERO_CONFIG:
901 assert(va == 0);
902 pkt->set(c0_config);
902 pkt->setBE(c0_config);
903 break;
904 case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0:
905 assert(va == 0);
903 break;
904 case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0:
905 assert(va == 0);
906 pkt->set(itb->c0_tsb_ps0);
906 pkt->setBE(itb->c0_tsb_ps0);
907 break;
908 case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1:
909 assert(va == 0);
907 break;
908 case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1:
909 assert(va == 0);
910 pkt->set(itb->c0_tsb_ps1);
910 pkt->setBE(itb->c0_tsb_ps1);
911 break;
912 case ASI_IMMU_CTXT_ZERO_CONFIG:
913 assert(va == 0);
911 break;
912 case ASI_IMMU_CTXT_ZERO_CONFIG:
913 assert(va == 0);
914 pkt->set(itb->c0_config);
914 pkt->setBE(itb->c0_config);
915 break;
916 case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0:
917 assert(va == 0);
915 break;
916 case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0:
917 assert(va == 0);
918 pkt->set(cx_tsb_ps0);
918 pkt->setBE(cx_tsb_ps0);
919 break;
920 case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1:
921 assert(va == 0);
919 break;
920 case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1:
921 assert(va == 0);
922 pkt->set(cx_tsb_ps1);
922 pkt->setBE(cx_tsb_ps1);
923 break;
924 case ASI_DMMU_CTXT_NONZERO_CONFIG:
925 assert(va == 0);
923 break;
924 case ASI_DMMU_CTXT_NONZERO_CONFIG:
925 assert(va == 0);
926 pkt->set(cx_config);
926 pkt->setBE(cx_config);
927 break;
928 case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0:
929 assert(va == 0);
927 break;
928 case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0:
929 assert(va == 0);
930 pkt->set(itb->cx_tsb_ps0);
930 pkt->setBE(itb->cx_tsb_ps0);
931 break;
932 case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1:
933 assert(va == 0);
931 break;
932 case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1:
933 assert(va == 0);
934 pkt->set(itb->cx_tsb_ps1);
934 pkt->setBE(itb->cx_tsb_ps1);
935 break;
936 case ASI_IMMU_CTXT_NONZERO_CONFIG:
937 assert(va == 0);
935 break;
936 case ASI_IMMU_CTXT_NONZERO_CONFIG:
937 assert(va == 0);
938 pkt->set(itb->cx_config);
938 pkt->setBE(itb->cx_config);
939 break;
940 case ASI_SPARC_ERROR_STATUS_REG:
939 break;
940 case ASI_SPARC_ERROR_STATUS_REG:
941 pkt->set((uint64_t)0);
941 pkt->setBE((uint64_t)0);
942 break;
943 case ASI_HYP_SCRATCHPAD:
944 case ASI_SCRATCHPAD:
942 break;
943 case ASI_HYP_SCRATCHPAD:
944 case ASI_SCRATCHPAD:
945 pkt->set(tc->readMiscReg(MISCREG_SCRATCHPAD_R0 + (va >> 3)));
945 pkt->setBE(tc->readMiscReg(MISCREG_SCRATCHPAD_R0 + (va >> 3)));
946 break;
947 case ASI_IMMU:
948 switch (va) {
949 case 0x0:
950 temp = itb->tag_access;
946 break;
947 case ASI_IMMU:
948 switch (va) {
949 case 0x0:
950 temp = itb->tag_access;
951 pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48);
951 pkt->setBE(bits(temp,63,22) | bits(temp,12,0) << 48);
952 break;
953 case 0x18:
952 break;
953 case 0x18:
954 pkt->set(itb->sfsr);
954 pkt->setBE(itb->sfsr);
955 break;
956 case 0x30:
955 break;
956 case 0x30:
957 pkt->set(itb->tag_access);
957 pkt->setBE(itb->tag_access);
958 break;
959 default:
960 goto doMmuReadError;
961 }
962 break;
963 case ASI_DMMU:
964 switch (va) {
965 case 0x0:
966 temp = tag_access;
958 break;
959 default:
960 goto doMmuReadError;
961 }
962 break;
963 case ASI_DMMU:
964 switch (va) {
965 case 0x0:
966 temp = tag_access;
967 pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48);
967 pkt->setBE(bits(temp,63,22) | bits(temp,12,0) << 48);
968 break;
969 case 0x18:
968 break;
969 case 0x18:
970 pkt->set(sfsr);
970 pkt->setBE(sfsr);
971 break;
972 case 0x20:
971 break;
972 case 0x20:
973 pkt->set(sfar);
973 pkt->setBE(sfar);
974 break;
975 case 0x30:
974 break;
975 case 0x30:
976 pkt->set(tag_access);
976 pkt->setBE(tag_access);
977 break;
978 case 0x80:
977 break;
978 case 0x80:
979 pkt->set(tc->readMiscReg(MISCREG_MMU_PART_ID));
979 pkt->setBE(tc->readMiscReg(MISCREG_MMU_PART_ID));
980 break;
981 default:
982 goto doMmuReadError;
983 }
984 break;
985 case ASI_DMMU_TSB_PS0_PTR_REG:
980 break;
981 default:
982 goto doMmuReadError;
983 }
984 break;
985 case ASI_DMMU_TSB_PS0_PTR_REG:
986 pkt->set(MakeTsbPtr(Ps0,
986 pkt->setBE(MakeTsbPtr(Ps0,
987 tag_access,
988 c0_tsb_ps0,
989 c0_config,
990 cx_tsb_ps0,
991 cx_config));
992 break;
993 case ASI_DMMU_TSB_PS1_PTR_REG:
987 tag_access,
988 c0_tsb_ps0,
989 c0_config,
990 cx_tsb_ps0,
991 cx_config));
992 break;
993 case ASI_DMMU_TSB_PS1_PTR_REG:
994 pkt->set(MakeTsbPtr(Ps1,
994 pkt->setBE(MakeTsbPtr(Ps1,
995 tag_access,
996 c0_tsb_ps1,
997 c0_config,
998 cx_tsb_ps1,
999 cx_config));
1000 break;
1001 case ASI_IMMU_TSB_PS0_PTR_REG:
995 tag_access,
996 c0_tsb_ps1,
997 c0_config,
998 cx_tsb_ps1,
999 cx_config));
1000 break;
1001 case ASI_IMMU_TSB_PS0_PTR_REG:
1002 pkt->set(MakeTsbPtr(Ps0,
1002 pkt->setBE(MakeTsbPtr(Ps0,
1003 itb->tag_access,
1004 itb->c0_tsb_ps0,
1005 itb->c0_config,
1006 itb->cx_tsb_ps0,
1007 itb->cx_config));
1008 break;
1009 case ASI_IMMU_TSB_PS1_PTR_REG:
1003 itb->tag_access,
1004 itb->c0_tsb_ps0,
1005 itb->c0_config,
1006 itb->cx_tsb_ps0,
1007 itb->cx_config));
1008 break;
1009 case ASI_IMMU_TSB_PS1_PTR_REG:
1010 pkt->set(MakeTsbPtr(Ps1,
1010 pkt->setBE(MakeTsbPtr(Ps1,
1011 itb->tag_access,
1012 itb->c0_tsb_ps1,
1013 itb->c0_config,
1014 itb->cx_tsb_ps1,
1015 itb->cx_config));
1016 break;
1017 case ASI_SWVR_INTR_RECEIVE:
1018 {
1019 SparcISA::Interrupts * interrupts =
1020 dynamic_cast<SparcISA::Interrupts *>(
1021 tc->getCpuPtr()->getInterruptController(0));
1011 itb->tag_access,
1012 itb->c0_tsb_ps1,
1013 itb->c0_config,
1014 itb->cx_tsb_ps1,
1015 itb->cx_config));
1016 break;
1017 case ASI_SWVR_INTR_RECEIVE:
1018 {
1019 SparcISA::Interrupts * interrupts =
1020 dynamic_cast<SparcISA::Interrupts *>(
1021 tc->getCpuPtr()->getInterruptController(0));
1022 pkt->set(interrupts->get_vec(IT_INT_VEC));
1022 pkt->setBE(interrupts->get_vec(IT_INT_VEC));
1023 }
1024 break;
1025 case ASI_SWVR_UDB_INTR_R:
1026 {
1027 SparcISA::Interrupts * interrupts =
1028 dynamic_cast<SparcISA::Interrupts *>(
1029 tc->getCpuPtr()->getInterruptController(0));
1030 temp = findMsbSet(interrupts->get_vec(IT_INT_VEC));
1031 tc->getCpuPtr()->clearInterrupt(0, IT_INT_VEC, temp);
1023 }
1024 break;
1025 case ASI_SWVR_UDB_INTR_R:
1026 {
1027 SparcISA::Interrupts * interrupts =
1028 dynamic_cast<SparcISA::Interrupts *>(
1029 tc->getCpuPtr()->getInterruptController(0));
1030 temp = findMsbSet(interrupts->get_vec(IT_INT_VEC));
1031 tc->getCpuPtr()->clearInterrupt(0, IT_INT_VEC, temp);
1032 pkt->set(temp);
1032 pkt->setBE(temp);
1033 }
1034 break;
1035 default:
1036doMmuReadError:
1037 panic("need to impl DTB::doMmuRegRead() got asi=%#x, va=%#x\n",
1038 (uint32_t)asi, va);
1039 }
1040 pkt->makeAtomicResponse();
1041 return Cycles(1);
1042}
1043
1044Cycles
1045TLB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
1046{
1033 }
1034 break;
1035 default:
1036doMmuReadError:
1037 panic("need to impl DTB::doMmuRegRead() got asi=%#x, va=%#x\n",
1038 (uint32_t)asi, va);
1039 }
1040 pkt->makeAtomicResponse();
1041 return Cycles(1);
1042}
1043
1044Cycles
1045TLB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
1046{
1047 uint64_t data = pkt->get();
1047 uint64_t data = pkt->getBE<uint64_t>();
1048 Addr va = pkt->getAddr();
1049 ASI asi = (ASI)pkt->req->getArchFlags();
1050
1051 Addr ta_insert;
1052 Addr va_insert;
1053 Addr ct_insert;
1054 int part_insert;
1055 int entry_insert = -1;

--- 370 unchanged lines hidden --- 		1048 Addr va = pkt->getAddr();
1049 ASI asi = (ASI)pkt->req->getArchFlags();
1050
1051 Addr ta_insert;
1052 Addr va_insert;
1053 Addr ct_insert;
1054 int part_insert;
1055 int entry_insert = -1;

--- 370 unchanged lines hidden ---