tlb.cc (12620:fe5cdc0293dd) tlb.cc (12749:223c83ed9979)
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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410{
411 DPRINTF(TLB, "TLB: Fault: A=%#x w=%d ct=%d ft=%d asi=%d\n",
412 a, (int)write, ct, ft, asi);
413 TLB::writeSfsr(write, ct, se, ft, asi);
414 sfar = a;
415}
416
417Fault
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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410{
411 DPRINTF(TLB, "TLB: Fault: A=%#x w=%d ct=%d ft=%d asi=%d\n",
412 a, (int)write, ct, ft, asi);
413 TLB::writeSfsr(write, ct, se, ft, asi);
414 sfar = a;
415}
416
417Fault
418TLB::translateInst(RequestPtr req, ThreadContext *tc)
418TLB::translateInst(const RequestPtr &req, ThreadContext *tc)
419{
420 uint64_t tlbdata = tc->readMiscRegNoEffect(MISCREG_TLB_DATA);
421
422 Addr vaddr = req->getVaddr();
423 TlbEntry *e;
424
425 assert(req->getArchFlags() == ASI_IMPLICIT);
426

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524 cacheEntry[0] = e;
525
526 req->setPaddr(e->pte.translate(vaddr));
527 DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr());
528 return NoFault;
529}
530
531Fault
419{
420 uint64_t tlbdata = tc->readMiscRegNoEffect(MISCREG_TLB_DATA);
421
422 Addr vaddr = req->getVaddr();
423 TlbEntry *e;
424
425 assert(req->getArchFlags() == ASI_IMPLICIT);
426

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524 cacheEntry[0] = e;
525
526 req->setPaddr(e->pte.translate(vaddr));
527 DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr());
528 return NoFault;
529}
530
531Fault
532TLB::translateData(RequestPtr req, ThreadContext *tc, bool write)
532TLB::translateData(const RequestPtr &req, ThreadContext *tc, bool write)
533{
534 /*
535 * @todo this could really use some profiling and fixing to make
536 * it faster!
537 */
538 uint64_t tlbdata = tc->readMiscRegNoEffect(MISCREG_TLB_DATA);
539 Addr vaddr = req->getVaddr();
540 Addr size = req->getSize();

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828handleMmuRegAccess:
829 DPRINTF(TLB, "TLB: DTB Translating MM IPR access\n");
830 req->setFlags(Request::MMAPPED_IPR);
831 req->setPaddr(req->getVaddr());
832 return NoFault;
833};
834
835Fault
533{
534 /*
535 * @todo this could really use some profiling and fixing to make
536 * it faster!
537 */
538 uint64_t tlbdata = tc->readMiscRegNoEffect(MISCREG_TLB_DATA);
539 Addr vaddr = req->getVaddr();
540 Addr size = req->getSize();

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828handleMmuRegAccess:
829 DPRINTF(TLB, "TLB: DTB Translating MM IPR access\n");
830 req->setFlags(Request::MMAPPED_IPR);
831 req->setPaddr(req->getVaddr());
832 return NoFault;
833};
834
835Fault
836TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)
836TLB::translateAtomic(const RequestPtr &req, ThreadContext *tc, Mode mode)
837{
838 if (mode == Execute)
839 return translateInst(req, tc);
840 else
841 return translateData(req, tc, mode == Write);
842}
843
844void
837{
838 if (mode == Execute)
839 return translateInst(req, tc);
840 else
841 return translateData(req, tc, mode == Write);
842}
843
844void
845TLB::translateTiming(RequestPtr req, ThreadContext *tc,
845TLB::translateTiming(const RequestPtr &req, ThreadContext *tc,
846 Translation *translation, Mode mode)
847{
848 assert(translation);
849 translation->finish(translateAtomic(req, tc, mode), req, tc, mode);
850}
851
852Fault
846 Translation *translation, Mode mode)
847{
848 assert(translation);
849 translation->finish(translateAtomic(req, tc, mode), req, tc, mode);
850}
851
852Fault
853TLB::finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const
853TLB::finalizePhysical(const RequestPtr &req,
854 ThreadContext *tc, Mode mode) const
854{
855 return NoFault;
856}
857
858Cycles
859TLB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
860{
861 Addr va = pkt->getAddr();

--- 563 unchanged lines hidden --- 		855{
856 return NoFault;
857}
858
859Cycles
860TLB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
861{
862 Addr va = pkt->getAddr();

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