tlb.cc (12544:6a4c3acc4289) tlb.cc (12620:fe5cdc0293dd)
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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31#include "arch/sparc/tlb.hh"
32
33#include <cstring>
34
35#include "arch/sparc/asi.hh"
36#include "arch/sparc/faults.hh"
37#include "arch/sparc/registers.hh"
38#include "base/bitfield.hh"
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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31#include "arch/sparc/tlb.hh"
32
33#include <cstring>
34
35#include "arch/sparc/asi.hh"
36#include "arch/sparc/faults.hh"
37#include "arch/sparc/registers.hh"
38#include "base/bitfield.hh"
39#include "base/compiler.hh"
39#include "base/trace.hh"
40#include "cpu/base.hh"
41#include "cpu/thread_context.hh"
42#include "debug/IPR.hh"
43#include "debug/TLB.hh"
44#include "mem/packet_access.hh"
45#include "mem/request.hh"
46#include "sim/full_system.hh"

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1150 itb->tag_access = data;
1151 break;
1152 default:
1153 goto doMmuWriteError;
1154 }
1155 break;
1156 case ASI_ITLB_DATA_ACCESS_REG:
1157 entry_insert = bits(va, 8,3);
40#include "base/trace.hh"
41#include "cpu/base.hh"
42#include "cpu/thread_context.hh"
43#include "debug/IPR.hh"
44#include "debug/TLB.hh"
45#include "mem/packet_access.hh"
46#include "mem/request.hh"
47#include "sim/full_system.hh"

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1151 itb->tag_access = data;
1152 break;
1153 default:
1154 goto doMmuWriteError;
1155 }
1156 break;
1157 case ASI_ITLB_DATA_ACCESS_REG:
1158 entry_insert = bits(va, 8,3);
1159 M5_FALLTHROUGH;
1158 case ASI_ITLB_DATA_IN_REG:
1159 assert(entry_insert != -1 || mbits(va,10,9) == va);
1160 ta_insert = itb->tag_access;
1161 va_insert = mbits(ta_insert, 63,13);
1162 ct_insert = mbits(ta_insert, 12,0);
1163 part_insert = tc->readMiscReg(MISCREG_MMU_PART_ID);
1164 real_insert = bits(va, 9,9);
1165 pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v :
1166 PageTableEntry::sun4u);
1167 itb->insert(va_insert, part_insert, ct_insert, real_insert,
1168 pte, entry_insert);
1169 break;
1170 case ASI_DTLB_DATA_ACCESS_REG:
1171 entry_insert = bits(va, 8,3);
1160 case ASI_ITLB_DATA_IN_REG:
1161 assert(entry_insert != -1 || mbits(va,10,9) == va);
1162 ta_insert = itb->tag_access;
1163 va_insert = mbits(ta_insert, 63,13);
1164 ct_insert = mbits(ta_insert, 12,0);
1165 part_insert = tc->readMiscReg(MISCREG_MMU_PART_ID);
1166 real_insert = bits(va, 9,9);
1167 pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v :
1168 PageTableEntry::sun4u);
1169 itb->insert(va_insert, part_insert, ct_insert, real_insert,
1170 pte, entry_insert);
1171 break;
1172 case ASI_DTLB_DATA_ACCESS_REG:
1173 entry_insert = bits(va, 8,3);
1174 M5_FALLTHROUGH;
1172 case ASI_DTLB_DATA_IN_REG:
1173 assert(entry_insert != -1 || mbits(va,10,9) == va);
1174 ta_insert = tag_access;
1175 va_insert = mbits(ta_insert, 63,13);
1176 ct_insert = mbits(ta_insert, 12,0);
1177 part_insert = tc->readMiscReg(MISCREG_MMU_PART_ID);
1178 real_insert = bits(va, 9,9);
1179 pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v :

--- 242 unchanged lines hidden --- 		1175 case ASI_DTLB_DATA_IN_REG:
1176 assert(entry_insert != -1 || mbits(va,10,9) == va);
1177 ta_insert = tag_access;
1178 va_insert = mbits(ta_insert, 63,13);
1179 ct_insert = mbits(ta_insert, 12,0);
1180 part_insert = tc->readMiscReg(MISCREG_MMU_PART_ID);
1181 real_insert = bits(va, 9,9);
1182 pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v :

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