tlb.cc (11793:ef606668d247) tlb.cc (12406:86bde4a026b5)
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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844TLB::translateTiming(RequestPtr req, ThreadContext *tc,
845 Translation *translation, Mode mode)
846{
847 assert(translation);
848 translation->finish(translateAtomic(req, tc, mode), req, tc, mode);
849}
850
851Fault
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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844TLB::translateTiming(RequestPtr req, ThreadContext *tc,
845 Translation *translation, Mode mode)
846{
847 assert(translation);
848 translation->finish(translateAtomic(req, tc, mode), req, tc, mode);
849}
850
851Fault
852TLB::translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode)
853{
854 panic("Not implemented\n");
855 return NoFault;
856}
857
858Fault
859TLB::finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const
860{
861 return NoFault;
862}
863
864Cycles
865TLB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
866{
867 Addr va = pkt->getAddr();
868 ASI asi = (ASI)pkt->req->getArchFlags();
869 uint64_t temp;
870
871 DPRINTF(IPR, "Memory Mapped IPR Read: asi=%#X a=%#x\n",
872 (uint32_t)pkt->req->getArchFlags(), pkt->getAddr());
873
852TLB::finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const
853{
854 return NoFault;
855}
856
857Cycles
858TLB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
859{
860 Addr va = pkt->getAddr();
861 ASI asi = (ASI)pkt->req->getArchFlags();
862 uint64_t temp;
863
864 DPRINTF(IPR, "Memory Mapped IPR Read: asi=%#X a=%#x\n",
865 (uint32_t)pkt->req->getArchFlags(), pkt->getAddr());
866
874 TLB *itb = tc->getITBPtr();
867 TLB *itb = dynamic_cast<TLB *>(tc->getITBPtr());
875
876 switch (asi) {
877 case ASI_LSU_CONTROL_REG:
878 assert(va == 0);
879 pkt->set(tc->readMiscReg(MISCREG_MMU_LSU_CTRL));
880 break;
881 case ASI_MMU:
882 switch (va) {

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1062 bool ignore;
1063 int part_id;
1064 int ctx_id;
1065 PageTableEntry pte;
1066
1067 DPRINTF(IPR, "Memory Mapped IPR Write: asi=%#X a=%#x d=%#X\n",
1068 (uint32_t)asi, va, data);
1069
868
869 switch (asi) {
870 case ASI_LSU_CONTROL_REG:
871 assert(va == 0);
872 pkt->set(tc->readMiscReg(MISCREG_MMU_LSU_CTRL));
873 break;
874 case ASI_MMU:
875 switch (va) {

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1055 bool ignore;
1056 int part_id;
1057 int ctx_id;
1058 PageTableEntry pte;
1059
1060 DPRINTF(IPR, "Memory Mapped IPR Write: asi=%#X a=%#x d=%#X\n",
1061 (uint32_t)asi, va, data);
1062
1070 TLB *itb = tc->getITBPtr();
1063 TLB *itb = dynamic_cast<TLB *>(tc->getITBPtr());
1071
1072 switch (asi) {
1073 case ASI_LSU_CONTROL_REG:
1074 assert(va == 0);
1075 tc->setMiscReg(MISCREG_MMU_LSU_CTRL, data);
1076 break;
1077 case ASI_MMU:
1078 switch (va) {

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1166 assert(entry_insert != -1 || mbits(va,10,9) == va);
1167 ta_insert = itb->tag_access;
1168 va_insert = mbits(ta_insert, 63,13);
1169 ct_insert = mbits(ta_insert, 12,0);
1170 part_insert = tc->readMiscReg(MISCREG_MMU_PART_ID);
1171 real_insert = bits(va, 9,9);
1172 pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v :
1173 PageTableEntry::sun4u);
1064
1065 switch (asi) {
1066 case ASI_LSU_CONTROL_REG:
1067 assert(va == 0);
1068 tc->setMiscReg(MISCREG_MMU_LSU_CTRL, data);
1069 break;
1070 case ASI_MMU:
1071 switch (va) {

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1159 assert(entry_insert != -1 || mbits(va,10,9) == va);
1160 ta_insert = itb->tag_access;
1161 va_insert = mbits(ta_insert, 63,13);
1162 ct_insert = mbits(ta_insert, 12,0);
1163 part_insert = tc->readMiscReg(MISCREG_MMU_PART_ID);
1164 real_insert = bits(va, 9,9);
1165 pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v :
1166 PageTableEntry::sun4u);
1174 tc->getITBPtr()->insert(va_insert, part_insert, ct_insert, real_insert,
1175 pte, entry_insert);
1167 itb->insert(va_insert, part_insert, ct_insert, real_insert,
1168 pte, entry_insert);
1176 break;
1177 case ASI_DTLB_DATA_ACCESS_REG:
1178 entry_insert = bits(va, 8,3);
1179 case ASI_DTLB_DATA_IN_REG:
1180 assert(entry_insert != -1 || mbits(va,10,9) == va);
1181 ta_insert = tag_access;
1182 va_insert = mbits(ta_insert, 63,13);
1183 ct_insert = mbits(ta_insert, 12,0);

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1204 break;
1205 default:
1206 ignore = true;
1207 }
1208
1209 switch (bits(va,7,6)) {
1210 case 0: // demap page
1211 if (!ignore)
1169 break;
1170 case ASI_DTLB_DATA_ACCESS_REG:
1171 entry_insert = bits(va, 8,3);
1172 case ASI_DTLB_DATA_IN_REG:
1173 assert(entry_insert != -1 || mbits(va,10,9) == va);
1174 ta_insert = tag_access;
1175 va_insert = mbits(ta_insert, 63,13);
1176 ct_insert = mbits(ta_insert, 12,0);

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1197 break;
1198 default:
1199 ignore = true;
1200 }
1201
1202 switch (bits(va,7,6)) {
1203 case 0: // demap page
1204 if (!ignore)
1212 tc->getITBPtr()->demapPage(mbits(va,63,13), part_id,
1213 bits(va,9,9), ctx_id);
1205 itb->demapPage(mbits(va,63,13), part_id, bits(va,9,9), ctx_id);
1214 break;
1215 case 1: // demap context
1216 if (!ignore)
1206 break;
1207 case 1: // demap context
1208 if (!ignore)
1217 tc->getITBPtr()->demapContext(part_id, ctx_id);
1209 itb->demapContext(part_id, ctx_id);
1218 break;
1219 case 2:
1210 break;
1211 case 2:
1220 tc->getITBPtr()->demapAll(part_id);
1212 itb->demapAll(part_id);
1221 break;
1222 default:
1223 panic("Invalid type for IMMU demap\n");
1224 }
1225 break;
1226 case ASI_DMMU:
1227 switch (va) {
1228 case 0x18:

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1298 pkt->makeAtomicResponse();
1299 return Cycles(1);
1300}
1301
1302void
1303TLB::GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs)
1304{
1305 uint64_t tag_access = mbits(addr,63,13) | mbits(ctx,12,0);
1213 break;
1214 default:
1215 panic("Invalid type for IMMU demap\n");
1216 }
1217 break;
1218 case ASI_DMMU:
1219 switch (va) {
1220 case 0x18:

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1290 pkt->makeAtomicResponse();
1291 return Cycles(1);
1292}
1293
1294void
1295TLB::GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs)
1296{
1297 uint64_t tag_access = mbits(addr,63,13) | mbits(ctx,12,0);
1306 TLB * itb = tc->getITBPtr();
1298 TLB *itb = dynamic_cast<TLB *>(tc->getITBPtr());
1307 ptrs[0] = MakeTsbPtr(Ps0, tag_access,
1308 c0_tsb_ps0,
1309 c0_config,
1310 cx_tsb_ps0,
1311 cx_config);
1312 ptrs[1] = MakeTsbPtr(Ps1, tag_access,
1313 c0_tsb_ps1,
1314 c0_config,

--- 115 unchanged lines hidden --- 		1299 ptrs[0] = MakeTsbPtr(Ps0, tag_access,
1300 c0_tsb_ps0,
1301 c0_config,
1302 cx_tsb_ps0,
1303 cx_config);
1304 ptrs[1] = MakeTsbPtr(Ps1, tag_access,
1305 c0_tsb_ps1,
1306 c0_config,

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