tlb.cc (10905:a6ca6831e775) tlb.cc (11150:a8a64cca231b)
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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1017 itb->c0_config,
1018 itb->cx_tsb_ps1,
1019 itb->cx_config));
1020 break;
1021 case ASI_SWVR_INTR_RECEIVE:
1022 {
1023 SparcISA::Interrupts * interrupts =
1024 dynamic_cast<SparcISA::Interrupts *>(
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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1017 itb->c0_config,
1018 itb->cx_tsb_ps1,
1019 itb->cx_config));
1020 break;
1021 case ASI_SWVR_INTR_RECEIVE:
1022 {
1023 SparcISA::Interrupts * interrupts =
1024 dynamic_cast<SparcISA::Interrupts *>(
1025 tc->getCpuPtr()->getInterruptController());
1025 tc->getCpuPtr()->getInterruptController(0));
1026 pkt->set(interrupts->get_vec(IT_INT_VEC));
1027 }
1028 break;
1029 case ASI_SWVR_UDB_INTR_R:
1030 {
1031 SparcISA::Interrupts * interrupts =
1032 dynamic_cast<SparcISA::Interrupts *>(
1026 pkt->set(interrupts->get_vec(IT_INT_VEC));
1027 }
1028 break;
1029 case ASI_SWVR_UDB_INTR_R:
1030 {
1031 SparcISA::Interrupts * interrupts =
1032 dynamic_cast<SparcISA::Interrupts *>(
1033 tc->getCpuPtr()->getInterruptController());
1033 tc->getCpuPtr()->getInterruptController(0));
1034 temp = findMsbSet(interrupts->get_vec(IT_INT_VEC));
1034 temp = findMsbSet(interrupts->get_vec(IT_INT_VEC));
1035 tc->getCpuPtr()->clearInterrupt(IT_INT_VEC, temp);
1035 tc->getCpuPtr()->clearInterrupt(0, IT_INT_VEC, temp);
1036 pkt->set(temp);
1037 }
1038 break;
1039 default:
1040doMmuReadError:
1041 panic("need to impl DTB::doMmuRegRead() got asi=%#x, va=%#x\n",
1042 (uint32_t)asi, va);
1043 }

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1273 }
1274 break;
1275 case ASI_SWVR_INTR_RECEIVE:
1276 {
1277 int msb;
1278 // clear all the interrupts that aren't set in the write
1279 SparcISA::Interrupts * interrupts =
1280 dynamic_cast<SparcISA::Interrupts *>(
1036 pkt->set(temp);
1037 }
1038 break;
1039 default:
1040doMmuReadError:
1041 panic("need to impl DTB::doMmuRegRead() got asi=%#x, va=%#x\n",
1042 (uint32_t)asi, va);
1043 }

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1273 }
1274 break;
1275 case ASI_SWVR_INTR_RECEIVE:
1276 {
1277 int msb;
1278 // clear all the interrupts that aren't set in the write
1279 SparcISA::Interrupts * interrupts =
1280 dynamic_cast<SparcISA::Interrupts *>(
1281 tc->getCpuPtr()->getInterruptController());
1281 tc->getCpuPtr()->getInterruptController(0));
1282 while (interrupts->get_vec(IT_INT_VEC) & data) {
1283 msb = findMsbSet(interrupts->get_vec(IT_INT_VEC) & data);
1282 while (interrupts->get_vec(IT_INT_VEC) & data) {
1283 msb = findMsbSet(interrupts->get_vec(IT_INT_VEC) & data);
1284 tc->getCpuPtr()->clearInterrupt(IT_INT_VEC, msb);
1284 tc->getCpuPtr()->clearInterrupt(0, IT_INT_VEC, msb);
1285 }
1286 }
1287 break;
1288 case ASI_SWVR_UDB_INTR_W:
1289 tc->getSystemPtr()->threadContexts[bits(data,12,8)]->getCpuPtr()->
1285 }
1286 }
1287 break;
1288 case ASI_SWVR_UDB_INTR_W:
1289 tc->getSystemPtr()->threadContexts[bits(data,12,8)]->getCpuPtr()->
1290 postInterrupt(bits(data, 5, 0), 0);
1290 postInterrupt(0, bits(data, 5, 0), 0);
1291 break;
1292 default:
1293doMmuWriteError:
1294 panic("need to impl DTB::doMmuRegWrite() got asi=%#x, va=%#x d=%#x\n",
1295 (uint32_t)pkt->req->getArchFlags(), pkt->getAddr(), data);
1296 }
1297 pkt->makeAtomicResponse();
1298 return Cycles(1);

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1292 default:
1293doMmuWriteError:
1294 panic("need to impl DTB::doMmuRegWrite() got asi=%#x, va=%#x d=%#x\n",
1295 (uint32_t)pkt->req->getArchFlags(), pkt->getAddr(), data);
1296 }
1297 pkt->makeAtomicResponse();
1298 return Cycles(1);

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