1/* 2 * Copyright (c) 2001-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 117 unchanged lines hidden (view full) --- 126 tlb[x].used = false; 127 usedEntries--; 128 } 129 lookupTable.erase(tlb[x].range); 130 } 131 } 132 } 133 |
134 if (entry != -1) { 135 assert(entry < size && entry >= 0); 136 new_entry = &tlb[entry]; 137 } else { 138 if (!freeList.empty()) { 139 new_entry = freeList.front(); 140 } else { 141 x = lastReplaced; 142 do { 143 ++x; 144 if (x == size) 145 x = 0; 146 if (x == lastReplaced) 147 goto insertAllLocked; 148 } while (tlb[x].pte.locked()); 149 lastReplaced = x; 150 new_entry = &tlb[x]; 151 } |
152 } 153 154insertAllLocked: 155 // Update the last ently if their all locked 156 if (!new_entry) { 157 new_entry = &tlb[size-1]; 158 } 159 --- 455 unchanged lines hidden (view full) --- 615 context = 0; 616 } else { 617 asi = ASI_P; 618 ct = Primary; 619 context = pri_context; 620 } 621 } else { 622 // We need to check for priv level/asi priv |
623 if (!priv && !hpriv && !asiIsUnPriv(asi)) { |
624 // It appears that context should be Nucleus in these cases? 625 writeSfsr(vaddr, write, Nucleus, false, IllegalAsi, asi); 626 return new PrivilegedAction; 627 } 628 |
629 if (!hpriv && asiIsHPriv(asi)) { |
630 writeSfsr(vaddr, write, Nucleus, false, IllegalAsi, asi); 631 return new DataAccessException; 632 } 633 |
634 if (asiIsPrimary(asi)) { |
635 context = pri_context; 636 ct = Primary; |
637 } else if (asiIsSecondary(asi)) { |
638 context = sec_context; 639 ct = Secondary; |
640 } else if (asiIsNucleus(asi)) { |
641 ct = Nucleus; 642 context = 0; 643 } else { // ???? 644 ct = Primary; 645 context = pri_context; 646 } 647 } 648 649 if (!implicit && asi != ASI_P && asi != ASI_S) { |
650 if (asiIsLittle(asi)) |
651 panic("Little Endian ASIs not supported\n"); 652 653 //XXX It's unclear from looking at the documentation how a no fault |
654 // load differs from a regular one, other than what happens concerning 655 // nfo and e bits in the TTE 656// if (asiIsNoFault(asi)) |
657// panic("No Fault ASIs not supported\n"); 658 |
659 if (asiIsPartialStore(asi)) |
660 panic("Partial Store ASIs not supported\n"); 661 |
662 if (asiIsCmt(asi)) |
663 panic("Cmt ASI registers not implmented\n"); 664 |
665 if (asiIsInterrupt(asi)) |
666 goto handleIntRegAccess; |
667 if (asiIsMmu(asi)) |
668 goto handleMmuRegAccess; |
669 if (asiIsScratchPad(asi)) |
670 goto handleScratchRegAccess; |
671 if (asiIsQueue(asi)) |
672 goto handleQueueRegAccess; |
673 if (asiIsSparcError(asi)) |
674 goto handleSparcErrorRegAccess; 675 |
676 if (!asiIsReal(asi) && !asiIsNucleus(asi) && !asiIsAsIfUser(asi) && 677 !asiIsTwin(asi) && !asiIsBlock(asi) && !asiIsNoFault(asi)) |
678 panic("Accessing ASI %#X. Should we?\n", asi); 679 } 680 681 // If the asi is unaligned trap 682 if (unaligned) { 683 writeSfsr(vaddr, false, ct, false, OtherFault, asi); 684 return new MemAddressNotAligned; 685 } 686 687 if (addr_mask) 688 vaddr = vaddr & VAddrAMask; 689 690 if (!validVirtualAddress(vaddr, addr_mask)) { 691 writeSfsr(vaddr, false, ct, true, VaOutOfRange, asi); 692 return new DataAccessException; 693 } 694 |
695 if ((!lsu_dm && !hpriv && !red) || asiIsReal(asi)) { |
696 real = true; 697 context = 0; 698 } 699 |
700 if (hpriv && (implicit || (!asiIsAsIfUser(asi) && !asiIsReal(asi)))) { |
701 req->setPaddr(vaddr & PAddrImplMask); 702 return NoFault; 703 } 704 705 e = lookup(vaddr, part_id, real, context); 706 707 if (e == NULL || !e->valid) { 708 writeTagAccess(vaddr, context); --- 16 unchanged lines hidden (view full) --- 725 } 726 727 if (write && !e->pte.writable()) { 728 writeTagAccess(vaddr, context); 729 writeSfsr(vaddr, write, ct, e->pte.sideffect(), OtherFault, asi); 730 return new FastDataAccessProtection; 731 } 732 |
733 if (e->pte.nofault() && !asiIsNoFault(asi)) { |
734 writeTagAccess(vaddr, context); 735 writeSfsr(vaddr, write, ct, e->pte.sideffect(), LoadFromNfo, asi); 736 return new DataAccessException; 737 } 738 |
739 if (e->pte.sideffect() && asiIsNoFault(asi)) { |
740 writeTagAccess(vaddr, context); 741 writeSfsr(vaddr, write, ct, e->pte.sideffect(), SideEffect, asi); 742 return new DataAccessException; 743 } 744 745 if (e->pte.sideffect() || (e->pte.paddr() >> 39) & 1) 746 req->setFlags(Request::UNCACHEABLE); 747 --- 432 unchanged lines hidden (view full) --- 1180 break; 1181 case 3: 1182 ctx_id = 0; 1183 break; 1184 default: 1185 ignore = true; 1186 } 1187 |
1188 switch (bits(va,7,6)) { |
1189 case 0: // demap page 1190 if (!ignore) 1191 tc->getITBPtr()->demapPage(mbits(va,63,13), part_id, 1192 bits(va,9,9), ctx_id); 1193 break; |
1194 case 1: // demap context |
1195 if (!ignore) 1196 tc->getITBPtr()->demapContext(part_id, ctx_id); 1197 break; 1198 case 2: 1199 tc->getITBPtr()->demapAll(part_id); 1200 break; 1201 default: 1202 panic("Invalid type for IMMU demap\n"); --- 28 unchanged lines hidden (view full) --- 1231 break; 1232 case 3: 1233 ctx_id = 0; 1234 break; 1235 default: 1236 ignore = true; 1237 } 1238 |
1239 switch (bits(va,7,6)) { |
1240 case 0: // demap page 1241 if (!ignore) 1242 demapPage(mbits(va,63,13), part_id, bits(va,9,9), ctx_id); 1243 break; |
1244 case 1: // demap context |
1245 if (!ignore) 1246 demapContext(part_id, ctx_id); 1247 break; 1248 case 2: 1249 demapAll(part_id); 1250 break; 1251 default: 1252 panic("Invalid type for IMMU demap\n"); --- 165 unchanged lines hidden --- |