1/* 2 * Copyright (c) 2001-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 29 unchanged lines hidden (view full) --- 38#include "cpu/thread_context.hh" 39#include "cpu/base.hh" 40#include "mem/packet_access.hh" 41#include "mem/request.hh" 42#include "sim/builder.hh" 43 44/* @todo remove some of the magic constants. -- ali 45 * */ |
46namespace SparcISA 47{ |
48 49TLB::TLB(const std::string &name, int s) 50 : SimObject(name), size(s), usedEntries(0), lastReplaced(0), 51 cacheValid(false) 52{ 53 // To make this work you'll have to change the hypervisor and OS 54 if (size > 64) 55 fatal("SPARC T1 TLB registers don't support more than 64 TLB entries."); --- 535 unchanged lines hidden (view full) --- 591 592 if (hpriv && implicit) { 593 req->setPaddr(vaddr & PAddrImplMask); 594 return NoFault; 595 } 596 597 // Be fast if we can! 598 if (cacheValid && cacheState == tlbdata) { |
599 |
600 601 602 if (cacheEntry[0]) { 603 TlbEntry *ce = cacheEntry[0]; 604 Addr ce_va = ce->range.va; 605 if (cacheAsi[0] == asi && 606 ce_va < vaddr + size && ce_va + ce->range.size > vaddr && 607 (!write || ce->pte.writable())) { 608 req->setPaddr(ce->pte.paddrMask() | vaddr & ce->pte.sizeMask()); 609 if (ce->pte.sideffect() || (ce->pte.paddr() >> 39) & 1) 610 req->setFlags(req->getFlags() | UNCACHEABLE); 611 DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr()); 612 return NoFault; 613 } // if matched 614 } // if cache entry valid 615 if (cacheEntry[1]) { 616 TlbEntry *ce = cacheEntry[1]; 617 Addr ce_va = ce->range.va; 618 if (cacheAsi[1] == asi && 619 ce_va < vaddr + size && ce_va + ce->range.size > vaddr && 620 (!write || ce->pte.writable())) { 621 req->setPaddr(ce->pte.paddrMask() | vaddr & ce->pte.sizeMask()); 622 if (ce->pte.sideffect() || (ce->pte.paddr() >> 39) & 1) 623 req->setFlags(req->getFlags() | UNCACHEABLE); 624 DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr()); 625 return NoFault; 626 } // if matched 627 } // if cache entry valid 628 } 629 |
630 bool red = bits(tlbdata,1,1); 631 bool priv = bits(tlbdata,2,2); 632 bool addr_mask = bits(tlbdata,3,3); 633 bool lsu_dm = bits(tlbdata,5,5); 634 635 int part_id = bits(tlbdata,15,8); 636 int tl = bits(tlbdata,18,16); 637 int pri_context = bits(tlbdata,47,32); --- 128 unchanged lines hidden (view full) --- 766 767 if (e->pte.sideffect() && AsiIsNoFault(asi)) { 768 writeTagAccess(tc, vaddr, context); 769 writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), SideEffect, asi); 770 return new DataAccessException; 771 } 772 773 |
774 if (e->pte.sideffect() || (e->pte.paddr() >> 39) & 1) |
775 req->setFlags(req->getFlags() | UNCACHEABLE); 776 777 // cache translation date for next translation 778 cacheState = tlbdata; 779 if (!cacheValid) { 780 cacheEntry[1] = NULL; 781 cacheEntry[0] = NULL; 782 } --- 556 unchanged lines hidden (view full) --- 1339 for (int x = 0; x < size; x++) { 1340 tlb[x].unserialize(cp, csprintf("%s.PTE%d", section, x)); 1341 if (tlb[x].valid) 1342 lookupTable.insert(tlb[x].range, &tlb[x]); 1343 1344 } 1345} 1346 |
1347 |
1348DEFINE_SIM_OBJECT_CLASS_NAME("SparcTLB", TLB) 1349 1350BEGIN_DECLARE_SIM_OBJECT_PARAMS(ITB) 1351 1352 Param<int> size; 1353 1354END_DECLARE_SIM_OBJECT_PARAMS(ITB) 1355 --- 25 unchanged lines hidden (view full) --- 1381 1382 1383CREATE_SIM_OBJECT(DTB) 1384{ 1385 return new DTB(getInstanceName(), size); 1386} 1387 1388REGISTER_SIM_OBJECT("SparcDTB", DTB) |
1389} |