1/* 2 * Copyright (c) 2001-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 611 unchanged lines hidden (view full) --- 620 writeSfr(tc, vaddr, write, Nucleus, false, IllegalAsi, asi); 621 return new PrivilegedAction; 622 } 623 if (priv && AsiIsHPriv(asi)) { 624 writeSfr(tc, vaddr, write, Nucleus, false, IllegalAsi, asi); 625 return new DataAccessException; 626 } 627 |
628 } 629 if (asi == ASI_P || asi == ASI_LDTX_P) { 630 ct = Primary; 631 context = pri_context; 632 goto continueDtbFlow; 633 } |
634 635 if (!implicit) { 636 if (AsiIsLittle(asi)) 637 panic("Little Endian ASIs not supported\n"); 638 if (AsiIsBlock(asi)) 639 panic("Block ASIs not supported\n"); 640 if (AsiIsNoFault(asi)) 641 panic("No Fault ASIs not supported\n"); |
642 if (!write && asi == ASI_QUAD_LDD) 643 goto continueDtbFlow; 644 645 if (AsiIsTwin(asi)) 646 panic("Twin ASIs not supported\n"); 647 if (AsiIsPartialStore(asi)) 648 panic("Partial Store ASIs not supported\n"); 649 if (AsiIsInterrupt(asi)) --- 602 unchanged lines hidden --- |