1/* 2 * Copyright (c) 2001-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 57 unchanged lines hidden (view full) --- 66 usedEntries--; 67 } 68 } 69} 70 71 72void 73TLB::insert(Addr va, int partition_id, int context_id, bool real, |
74 const PageTableEntry& PTE, int entry) |
75{ 76 77 78 MapIter i; |
79 TlbEntry *new_entry = NULL; 80 int x; |
81 |
82 DPRINTF(TLB, "TLB: Inserting TLB Entry; va=%#x pa=%#x pid=%d cid=%d r=%d\n", 83 va, PTE.paddr(), partition_id, context_id, (int)real); |
84 |
85 if (entry != -1) { 86 assert(entry < size && entry >= 0); 87 new_entry = &tlb[entry]; 88 } else { 89 for (x = 0; x < size; x++) { 90 if (!tlb[x].valid || !tlb[x].used) { 91 new_entry = &tlb[x]; 92 break; 93 } |
94 } 95 } 96 97 // Update the last ently if their all locked |
98 if (!new_entry) 99 new_entry = &tlb[size-1]; |
100 101 assert(PTE.valid()); 102 new_entry->range.va = va; 103 new_entry->range.size = PTE.size(); 104 new_entry->range.partitionId = partition_id; 105 new_entry->range.contextId = context_id; 106 new_entry->range.real = real; 107 new_entry->pte = PTE; --- 44 unchanged lines hidden (view full) --- 152 tr.real = real; 153 154 // Try to find the entry 155 i = lookupTable.find(tr); 156 if (i == lookupTable.end()) { 157 DPRINTF(TLB, "TLB: No valid entry found\n"); 158 return NULL; 159 } |
160 161 // Mark the entries used bit and clear other used bits in needed 162 t = i->second; |
163 DPRINTF(TLB, "TLB: Valid entry found pa: %#x size: %#x\n", t->pte.paddr(), 164 t->pte.size()); |
165 if (!t->used) { 166 t->used = true; 167 usedEntries++; 168 if (usedEntries == size) { 169 clearUsedBits(); 170 t->used = true; 171 usedEntries++; 172 } 173 } 174 175 return t; 176} 177 |
178void 179TLB::dumpAll() 180{ 181 for (int x = 0; x < size; x++) { 182 if (tlb[x].valid) { 183 DPRINTFN("%4d: %#2x:%#2x %c %#4x %#8x %#8x %#16x\n", 184 x, tlb[x].range.partitionId, tlb[x].range.contextId, 185 tlb[x].range.real ? 'R' : ' ', tlb[x].range.size, 186 tlb[x].range.va, tlb[x].pte.paddr(), tlb[x].pte()); 187 } 188 } 189} |
190 191void 192TLB::demapPage(Addr va, int partition_id, bool real, int context_id) 193{ 194 TlbRange tr; 195 MapIter i; 196 197 // Assemble full address structure --- 100 unchanged lines hidden (view full) --- 298 299 if (write) 300 sfsr |= 1 << 2; 301 sfsr |= ct << 4; 302 if (se) 303 sfsr |= 1 << 6; 304 sfsr |= ft << 7; 305 sfsr |= asi << 16; |
306 tc->setMiscRegWithEffect(reg, sfsr); |
307} 308 |
309void 310TLB::writeTagAccess(ThreadContext *tc, int reg, Addr va, int context) 311{ 312 tc->setMiscRegWithEffect(reg, mbits(va, 63,13) | mbits(context,12,0)); 313} |
314 315void 316ITB::writeSfsr(ThreadContext *tc, bool write, ContextType ct, 317 bool se, FaultTypes ft, int asi) 318{ 319 DPRINTF(TLB, "TLB: ITB Fault: w=%d ct=%d ft=%d asi=%d\n", 320 (int)write, ct, ft, asi); 321 TLB::writeSfsr(tc, MISCREG_MMU_ITLB_SFSR, write, ct, se, ft, asi); 322} 323 324void |
325ITB::writeTagAccess(ThreadContext *tc, Addr va, int context) 326{ 327 TLB::writeTagAccess(tc, MISCREG_MMU_ITLB_TAG_ACCESS, va, context); 328} 329 330void |
331DTB::writeSfr(ThreadContext *tc, Addr a, bool write, ContextType ct, 332 bool se, FaultTypes ft, int asi) 333{ 334 DPRINTF(TLB, "TLB: DTB Fault: A=%#x w=%d ct=%d ft=%d asi=%d\n", 335 a, (int)write, ct, ft, asi); 336 TLB::writeSfsr(tc, MISCREG_MMU_DTLB_SFSR, write, ct, se, ft, asi); |
337 tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_SFAR, a); |
338} 339 |
340 void 341DTB::writeTagAccess(ThreadContext *tc, Addr va, int context) 342{ 343 TLB::writeTagAccess(tc, MISCREG_MMU_DTLB_TAG_ACCESS, va, context); 344} |
345 |
346 347 |
348Fault 349ITB::translate(RequestPtr &req, ThreadContext *tc) 350{ 351 uint64_t hpstate = tc->readMiscReg(MISCREG_HPSTATE); 352 uint64_t pstate = tc->readMiscReg(MISCREG_PSTATE); 353 bool lsuIm = tc->readMiscReg(MISCREG_MMU_LSU_CTRL) >> 2 & 0x1; 354 uint64_t tl = tc->readMiscReg(MISCREG_TL); 355 uint64_t part_id = tc->readMiscReg(MISCREG_MMU_PART_ID); --- 24 unchanged lines hidden (view full) --- 380 } 381 382 if ( hpstate >> 2 & 0x1 || hpstate >> 5 & 0x1 ) { 383 req->setPaddr(req->getVaddr() & PAddrImplMask); 384 return NoFault; 385 } 386 387 // If the asi is unaligned trap |
388 if (vaddr & req->getSize()-1) { |
389 writeSfsr(tc, false, ct, false, OtherFault, asi); 390 return new MemAddressNotAligned; 391 } 392 393 if (addr_mask) 394 vaddr = vaddr & VAddrAMask; 395 396 if (!validVirtualAddress(vaddr, addr_mask)) { --- 19 unchanged lines hidden (view full) --- 416 } 417 418 // were not priviledged accesing priv page 419 if (!priv && e->pte.priv()) { 420 writeSfsr(tc, false, ct, false, PrivViolation, asi); 421 return new InstructionAccessException; 422 } 423 |
424 req->setPaddr(e->pte.paddr() & ~(e->pte.size()-1) | 425 req->getVaddr() & e->pte.size()-1 ); 426 DPRINTF(TLB, "TLB: %#X -> %#X\n", req->getVaddr(), req->getPaddr()); |
427 return NoFault; 428} 429 430 431 432Fault 433DTB::translate(RequestPtr &req, ThreadContext *tc, bool write) 434{ --- 53 unchanged lines hidden (view full) --- 488 writeSfr(tc, vaddr, write, Nucleus, false, IllegalAsi, asi); 489 return new PrivilegedAction; 490 } 491 if (priv && AsiIsHPriv(asi)) { 492 writeSfr(tc, vaddr, write, Nucleus, false, IllegalAsi, asi); 493 return new DataAccessException; 494 } 495 |
496 } else if (hpriv) { 497 if (asi == ASI_P) { 498 ct = Primary; 499 context = tc->readMiscReg(MISCREG_MMU_P_CONTEXT); 500 goto continueDtbFlow; 501 } |
502 } 503 |
504 if (!implicit) { 505 if (AsiIsLittle(asi)) 506 panic("Little Endian ASIs not supported\n"); 507 if (AsiIsBlock(asi)) 508 panic("Block ASIs not supported\n"); 509 if (AsiIsNoFault(asi)) 510 panic("No Fault ASIs not supported\n"); 511 if (AsiIsTwin(asi)) --- 11 unchanged lines hidden (view full) --- 523 goto handleQueueRegAccess; 524 if (AsiIsSparcError(asi)) 525 goto handleSparcErrorRegAccess; 526 527 if (!AsiIsReal(asi) && !AsiIsNucleus(asi)) 528 panic("Accessing ASI %#X. Should we?\n", asi); 529 } 530 |
531continueDtbFlow: 532 // If the asi is unaligned trap 533 if (vaddr & size-1) { 534 writeSfr(tc, vaddr, false, ct, false, OtherFault, asi); 535 return new MemAddressNotAligned; 536 } 537 538 if (addr_mask) 539 vaddr = vaddr & VAddrAMask; 540 541 if (!validVirtualAddress(vaddr, addr_mask)) { 542 writeSfr(tc, vaddr, false, ct, true, VaOutOfRange, asi); 543 return new DataAccessException; 544 } 545 546 |
547 if ((!lsuDm && !hpriv) || AsiIsReal(asi)) { 548 real = true; 549 context = 0; 550 }; 551 552 if (hpriv && (implicit || (!AsiIsAsIfUser(asi) && !AsiIsReal(asi)))) { 553 req->setPaddr(req->getVaddr() & PAddrImplMask); 554 return NoFault; --- 27 unchanged lines hidden (view full) --- 582 req->setFlags(req->getFlags() | UNCACHEABLE); 583 584 585 if (!priv && e->pte.priv()) { 586 writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), PrivViolation, asi); 587 return new DataAccessException; 588 } 589 |
590 req->setPaddr(e->pte.paddr() & ~(e->pte.size()-1) | 591 req->getVaddr() & e->pte.size()-1); 592 DPRINTF(TLB, "TLB: %#X -> %#X\n", req->getVaddr(), req->getPaddr()); |
593 return NoFault; 594 /** Normal flow ends here. */ 595 596handleScratchRegAccess: 597 if (vaddr > 0x38 || (vaddr >= 0x20 && vaddr < 0x30 && !hpriv)) { 598 writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi); 599 return new DataAccessException; 600 } --- 104 unchanged lines hidden (view full) --- 705 case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1: 706 assert(va == 0); 707 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS1)); 708 break; 709 case ASI_IMMU_CTXT_NONZERO_CONFIG: 710 assert(va == 0); 711 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG)); 712 break; |
713 case ASI_SPARC_ERROR_STATUS_REG: 714 warn("returning 0 for SPARC ERROR regsiter read\n"); 715 pkt->set(0); 716 break; |
717 case ASI_HYP_SCRATCHPAD: 718 case ASI_SCRATCHPAD: 719 pkt->set(tc->readMiscRegWithEffect(MISCREG_SCRATCHPAD_R0 + (va >> 3))); 720 break; |
721 case ASI_IMMU: 722 switch (va) { 723 case 0x30: 724 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS)); 725 break; 726 default: 727 goto doMmuReadError; 728 } 729 break; |
730 case ASI_DMMU: 731 switch (va) { |
732 case 0x30: 733 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS)); 734 break; |
735 case 0x80: 736 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID)); 737 break; 738 default: 739 goto doMmuReadError; 740 } 741 break; 742 default: --- 7 unchanged lines hidden (view full) --- 750 751Tick 752DTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt) 753{ 754 uint64_t data = gtoh(pkt->get<uint64_t>()); 755 Addr va = pkt->getAddr(); 756 ASI asi = (ASI)pkt->req->getAsi(); 757 |
758 Addr ta_insert; 759 Addr va_insert; 760 Addr ct_insert; 761 int part_insert; 762 int entry_insert = -1; 763 bool real_insert; 764 PageTableEntry pte; 765 |
766 DPRINTF(IPR, "Memory Mapped IPR Write: asi=%#X a=%#x d=%#X\n", 767 (uint32_t)asi, va, data); 768 769 switch (asi) { 770 case ASI_LSU_CONTROL_REG: 771 assert(va == 0); 772 tc->setMiscRegWithEffect(MISCREG_MMU_LSU_CTRL, data); 773 break; --- 65 unchanged lines hidden (view full) --- 839 case ASI_SPARC_ERROR_EN_REG: 840 case ASI_SPARC_ERROR_STATUS_REG: 841 warn("Ignoring write to SPARC ERROR regsiter\n"); 842 break; 843 case ASI_HYP_SCRATCHPAD: 844 case ASI_SCRATCHPAD: 845 tc->setMiscRegWithEffect(MISCREG_SCRATCHPAD_R0 + (va >> 3), data); 846 break; |
847 case ASI_IMMU: 848 switch (va) { 849 case 0x30: 850 tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS, data); 851 break; 852 default: 853 goto doMmuWriteError; 854 } 855 break; 856 case ASI_ITLB_DATA_ACCESS_REG: 857 entry_insert = bits(va, 8,3); 858 case ASI_ITLB_DATA_IN_REG: 859 assert(entry_insert != -1 || mbits(va,10,9) == va); 860 ta_insert = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS); 861 va_insert = mbits(ta_insert, 63,13); 862 ct_insert = mbits(ta_insert, 12,0); 863 part_insert = tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID); 864 real_insert = bits(va, 9,9); 865 pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v : 866 PageTableEntry::sun4u); 867 tc->getITBPtr()->insert(va_insert, part_insert, ct_insert, real_insert, 868 pte, entry_insert); 869 break; 870 case ASI_DTLB_DATA_ACCESS_REG: 871 entry_insert = bits(va, 8,3); 872 case ASI_DTLB_DATA_IN_REG: 873 assert(entry_insert != -1 || mbits(va,10,9) == va); 874 ta_insert = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS); 875 va_insert = mbits(ta_insert, 63,13); 876 ct_insert = mbits(ta_insert, 12,0); 877 part_insert = tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID); 878 real_insert = bits(va, 9,9); 879 pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v : 880 PageTableEntry::sun4u); 881 insert(va_insert, part_insert, ct_insert, real_insert, pte, entry_insert); 882 break; |
883 case ASI_DMMU: 884 switch (va) { |
885 case 0x30: 886 tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS, data); 887 break; |
888 case 0x80: 889 tc->setMiscRegWithEffect(MISCREG_MMU_PART_ID, data); 890 break; 891 default: 892 goto doMmuWriteError; 893 } 894 break; 895 default: --- 63 unchanged lines hidden --- |