48c48
< : SimObject(name), size(s)
---
> : SimObject(name), size(s), usedEntries(0), cacheValid(false)
81a82,83
> cacheValid = false;
>
196a199,200
> cacheValid = false;
>
219a224
> cacheValid = false;
236a242
> cacheValid = false;
252a259,260
> cacheValid = false;
>
340c348
< void
---
> void
352a361,383
> Addr vaddr = req->getVaddr();
> TlbEntry *e;
>
> assert(req->getAsi() == ASI_IMPLICIT);
>
> DPRINTF(TLB, "TLB: ITB Request to translate va=%#x size=%d\n",
> vaddr, req->getSize());
>
> // Be fast if we can!
> if (cacheValid && cacheState == tlbdata) {
> if (cacheEntry) {
> if (cacheEntry->range.va < vaddr + sizeof(MachInst) &&
> cacheEntry->range.va + cacheEntry->range.size >= vaddr) {
> req->setPaddr(cacheEntry->pte.paddr() & ~(cacheEntry->pte.size()-1) |
> vaddr & cacheEntry->pte.size()-1 );
> return NoFault;
> }
> } else {
> req->setPaddr(vaddr & PAddrImplMask);
> return NoFault;
> }
> }
>
362,363d392
<
< Addr vaddr = req->getVaddr();
368d396
< TlbEntry *e;
370,371d397
< DPRINTF(TLB, "TLB: ITB Request to translate va=%#x size=%d\n",
< vaddr, req->getSize());
375,376d400
< assert(req->getAsi() == ASI_IMPLICIT);
<
388c412,415
< req->setPaddr(req->getVaddr() & PAddrImplMask);
---
> cacheValid = true;
> cacheState = tlbdata;
> cacheEntry = NULL;
> req->setPaddr(vaddr & PAddrImplMask);
392,393c419,420
< // If the asi is unaligned trap
< if (vaddr & req->getSize()-1) {
---
> // If the access is unaligned trap
> if (vaddr & 0x3) {
407c434
< e = lookup(req->getVaddr(), part_id, true);
---
> e = lookup(vaddr, part_id, true);
428a456,460
> // cache translation date for next translation
> cacheValid = true;
> cacheState = tlbdata;
> cacheEntry = e;
>
430,431c462,463
< req->getVaddr() & e->pte.size()-1 );
< DPRINTF(TLB, "TLB: %#X -> %#X\n", req->getVaddr(), req->getPaddr());
---
> vaddr & e->pte.size()-1 );
> DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr());
442c474,478
<
---
> Addr vaddr = req->getVaddr();
> Addr size = req->getSize();
> ASI asi;
> asi = (ASI)req->getAsi();
> bool implicit = false;
443a480,507
>
> DPRINTF(TLB, "TLB: DTB Request to translate va=%#x size=%d asi=%#x\n",
> vaddr, size, asi);
>
> if (asi == ASI_IMPLICIT)
> implicit = true;
>
> if (hpriv && implicit) {
> req->setPaddr(vaddr & PAddrImplMask);
> return NoFault;
> }
>
> // Be fast if we can!
> if (cacheValid && cacheState == tlbdata) {
> if (cacheEntry[0] && cacheAsi[0] == asi && cacheEntry[0]->range.va < vaddr + size &&
> cacheEntry[0]->range.va + cacheEntry[0]->range.size >= vaddr) {
> req->setPaddr(cacheEntry[0]->pte.paddr() & ~(cacheEntry[0]->pte.size()-1) |
> vaddr & cacheEntry[0]->pte.size()-1 );
> return NoFault;
> }
> if (cacheEntry[1] && cacheAsi[1] == asi && cacheEntry[1]->range.va < vaddr + size &&
> cacheEntry[1]->range.va + cacheEntry[1]->range.size >= vaddr) {
> req->setPaddr(cacheEntry[1]->pte.paddr() & ~(cacheEntry[1]->pte.size()-1) |
> vaddr & cacheEntry[1]->pte.size()-1 );
> return NoFault;
> }
> }
>
454d517
< bool implicit = false;
456,457d518
< Addr vaddr = req->getVaddr();
< Addr size = req->getSize();
460d520
< ASI asi;
464,466d523
< asi = (ASI)req->getAsi();
< DPRINTF(TLB, "TLB: DTB Request to translate va=%#x size=%d asi=%#x\n",
< vaddr, size, asi);
469,470d525
< if (asi == ASI_IMPLICIT)
< implicit = true;
565c620
< req->setPaddr(req->getVaddr() & PAddrImplMask);
---
> req->setPaddr(vaddr & PAddrImplMask);
569c624
< e = lookup(req->getVaddr(), part_id, real, context);
---
> e = lookup(vaddr, part_id, real, context);
601a657,668
> // cache translation date for next translation
> cacheValid = true;
> cacheState = tlbdata;
> if (cacheEntry[0] != e && cacheEntry[1] != e) {
> cacheEntry[1] = cacheEntry[0];
> cacheEntry[0] = e;
> cacheAsi[1] = cacheAsi[0];
> cacheAsi[0] = asi;
> if (implicit)
> cacheAsi[0] = (ASI)0;
> }
>
603,604c670,671
< req->getVaddr() & e->pte.size()-1);
< DPRINTF(TLB, "TLB: %#X -> %#X\n", req->getVaddr(), req->getPaddr());
---
> vaddr & e->pte.size()-1);
> DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr());
776,777d842
< warn("base addr: %#X tag access: %#X page size: %#X tsb size: %#X\n",
< bits(tsbtemp,63,13), temp, bits(cnftemp,2,0), bits(tsbtemp,3,0));