74c74
< const PageTableEntry& PTE)
---
> const PageTableEntry& PTE, int entry)
79c79,80
< TlbEntry *new_entry;
---
> TlbEntry *new_entry = NULL;
> int x;
81,82c82,83
< DPRINTF(TLB, "TLB: Inserting TLB Entry; va=%#x, pid=%d cid=%d r=%d\n",
< va, partition_id, context_id, (int)real);
---
> DPRINTF(TLB, "TLB: Inserting TLB Entry; va=%#x pa=%#x pid=%d cid=%d r=%d\n",
> va, PTE.paddr(), partition_id, context_id, (int)real);
84,88c85,93
< int x = -1;
< for (x = 0; x < size; x++) {
< if (!tlb[x].valid || !tlb[x].used) {
< new_entry = &tlb[x];
< break;
---
> if (entry != -1) {
> assert(entry < size && entry >= 0);
> new_entry = &tlb[entry];
> } else {
> for (x = 0; x < size; x++) {
> if (!tlb[x].valid || !tlb[x].used) {
> new_entry = &tlb[x];
> break;
> }
93,94c98,99
< if (x == -1)
< x = size - 1;
---
> if (!new_entry)
> new_entry = &tlb[size-1];
155d159
< DPRINTF(TLB, "TLB: Valid entry found\n");
158a163,164
> DPRINTF(TLB, "TLB: Valid entry found pa: %#x size: %#x\n", t->pte.paddr(),
> t->pte.size());
171a178,189
> void
> TLB::dumpAll()
> {
> for (int x = 0; x < size; x++) {
> if (tlb[x].valid) {
> DPRINTFN("%4d: %#2x:%#2x %c %#4x %#8x %#8x %#16x\n",
> x, tlb[x].range.partitionId, tlb[x].range.contextId,
> tlb[x].range.real ? 'R' : ' ', tlb[x].range.size,
> tlb[x].range.va, tlb[x].pte.paddr(), tlb[x].pte());
> }
> }
> }
288c306
< tc->setMiscReg(reg, sfsr);
---
> tc->setMiscRegWithEffect(reg, sfsr);
290a309,313
> void
> TLB::writeTagAccess(ThreadContext *tc, int reg, Addr va, int context)
> {
> tc->setMiscRegWithEffect(reg, mbits(va, 63,13) | mbits(context,12,0));
> }
301a325,330
> ITB::writeTagAccess(ThreadContext *tc, Addr va, int context)
> {
> TLB::writeTagAccess(tc, MISCREG_MMU_ITLB_TAG_ACCESS, va, context);
> }
>
> void
308c337
< tc->setMiscReg(MISCREG_MMU_DTLB_SFAR, a);
---
> tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_SFAR, a);
310a340,344
> void
> DTB::writeTagAccess(ThreadContext *tc, Addr va, int context)
> {
> TLB::writeTagAccess(tc, MISCREG_MMU_DTLB_TAG_ACCESS, va, context);
> }
311a346,347
>
>
352c388
< if (vaddr & 0x7) {
---
> if (vaddr & req->getSize()-1) {
388,389c424,426
< req->setPaddr(e->pte.paddr() & ~e->pte.size() |
< req->getVaddr() & e->pte.size());
---
> req->setPaddr(e->pte.paddr() & ~(e->pte.size()-1) |
> req->getVaddr() & e->pte.size()-1 );
> DPRINTF(TLB, "TLB: %#X -> %#X\n", req->getVaddr(), req->getPaddr());
458a496,501
> } else if (hpriv) {
> if (asi == ASI_P) {
> ct = Primary;
> context = tc->readMiscReg(MISCREG_MMU_P_CONTEXT);
> goto continueDtbFlow;
> }
461,474d503
< // If the asi is unaligned trap
< if (vaddr & size-1) {
< writeSfr(tc, vaddr, false, ct, false, OtherFault, asi);
< return new MemAddressNotAligned;
< }
<
< if (addr_mask)
< vaddr = vaddr & VAddrAMask;
<
< if (!validVirtualAddress(vaddr, addr_mask)) {
< writeSfr(tc, vaddr, false, ct, true, VaOutOfRange, asi);
< return new DataAccessException;
< }
<
501a531,546
> continueDtbFlow:
> // If the asi is unaligned trap
> if (vaddr & size-1) {
> writeSfr(tc, vaddr, false, ct, false, OtherFault, asi);
> return new MemAddressNotAligned;
> }
>
> if (addr_mask)
> vaddr = vaddr & VAddrAMask;
>
> if (!validVirtualAddress(vaddr, addr_mask)) {
> writeSfr(tc, vaddr, false, ct, true, VaOutOfRange, asi);
> return new DataAccessException;
> }
>
>
545,546c590,592
< req->setPaddr(e->pte.paddr() & ~e->pte.size() |
< req->getVaddr() & e->pte.size());
---
> req->setPaddr(e->pte.paddr() & ~(e->pte.size()-1) |
> req->getVaddr() & e->pte.size()-1);
> DPRINTF(TLB, "TLB: %#X -> %#X\n", req->getVaddr(), req->getPaddr());
666a713,716
> case ASI_SPARC_ERROR_STATUS_REG:
> warn("returning 0 for SPARC ERROR regsiter read\n");
> pkt->set(0);
> break;
670a721,729
> case ASI_IMMU:
> switch (va) {
> case 0x30:
> pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS));
> break;
> default:
> goto doMmuReadError;
> }
> break;
672a732,734
> case 0x30:
> pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS));
> break;
695a758,765
> Addr ta_insert;
> Addr va_insert;
> Addr ct_insert;
> int part_insert;
> int entry_insert = -1;
> bool real_insert;
> PageTableEntry pte;
>
776a847,882
> case ASI_IMMU:
> switch (va) {
> case 0x30:
> tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS, data);
> break;
> default:
> goto doMmuWriteError;
> }
> break;
> case ASI_ITLB_DATA_ACCESS_REG:
> entry_insert = bits(va, 8,3);
> case ASI_ITLB_DATA_IN_REG:
> assert(entry_insert != -1 || mbits(va,10,9) == va);
> ta_insert = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS);
> va_insert = mbits(ta_insert, 63,13);
> ct_insert = mbits(ta_insert, 12,0);
> part_insert = tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID);
> real_insert = bits(va, 9,9);
> pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v :
> PageTableEntry::sun4u);
> tc->getITBPtr()->insert(va_insert, part_insert, ct_insert, real_insert,
> pte, entry_insert);
> break;
> case ASI_DTLB_DATA_ACCESS_REG:
> entry_insert = bits(va, 8,3);
> case ASI_DTLB_DATA_IN_REG:
> assert(entry_insert != -1 || mbits(va,10,9) == va);
> ta_insert = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS);
> va_insert = mbits(ta_insert, 63,13);
> ct_insert = mbits(ta_insert, 12,0);
> part_insert = tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID);
> real_insert = bits(va, 9,9);
> pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v :
> PageTableEntry::sun4u);
> insert(va_insert, part_insert, ct_insert, real_insert, pte, entry_insert);
> break;
778a885,887
> case 0x30:
> tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS, data);
> break;