tlb.cc (3979:3b0b08f60cdf) tlb.cc (3980:9bcb2a2e9bb8)
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Ali Saidi
29 */
30
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Ali Saidi
29 */
30
31#include <cstring>
32
31#include "arch/sparc/asi.hh"
32#include "arch/sparc/miscregfile.hh"
33#include "arch/sparc/tlb.hh"
34#include "base/bitfield.hh"
35#include "base/trace.hh"
36#include "cpu/thread_context.hh"
37#include "cpu/base.hh"
38#include "mem/packet_access.hh"
39#include "mem/request.hh"
40#include "sim/builder.hh"
41
42/* @todo remove some of the magic constants. -- ali
43 * */
44namespace SparcISA
45{
46
47TLB::TLB(const std::string &name, int s)
48 : SimObject(name), size(s), usedEntries(0), lastReplaced(0),
49 cacheValid(false)
50{
51 // To make this work you'll have to change the hypervisor and OS
52 if (size > 64)
53 fatal("SPARC T1 TLB registers don't support more than 64 TLB entries.");
54
55 tlb = new TlbEntry[size];
33#include "arch/sparc/asi.hh"
34#include "arch/sparc/miscregfile.hh"
35#include "arch/sparc/tlb.hh"
36#include "base/bitfield.hh"
37#include "base/trace.hh"
38#include "cpu/thread_context.hh"
39#include "cpu/base.hh"
40#include "mem/packet_access.hh"
41#include "mem/request.hh"
42#include "sim/builder.hh"
43
44/* @todo remove some of the magic constants. -- ali
45 * */
46namespace SparcISA
47{
48
49TLB::TLB(const std::string &name, int s)
50 : SimObject(name), size(s), usedEntries(0), lastReplaced(0),
51 cacheValid(false)
52{
53 // To make this work you'll have to change the hypervisor and OS
54 if (size > 64)
55 fatal("SPARC T1 TLB registers don't support more than 64 TLB entries.");
56
57 tlb = new TlbEntry[size];
56 memset(tlb, 0, sizeof(TlbEntry) * size);
58 std::memset(tlb, 0, sizeof(TlbEntry) * size);
57
58 for (int x = 0; x < size; x++)
59 freeList.push_back(&tlb[x]);
60}
61
62void
63TLB::clearUsedBits()
64{
65 MapIter i;
66 for (i = lookupTable.begin(); i != lookupTable.end(); i++) {
67 TlbEntry *t = i->second;
68 if (!t->pte.locked()) {
69 t->used = false;
70 usedEntries--;
71 }
72 }
73}
74
75
76void
77TLB::insert(Addr va, int partition_id, int context_id, bool real,
78 const PageTableEntry& PTE, int entry)
79{
80
81
82 MapIter i;
83 TlbEntry *new_entry = NULL;
84// TlbRange tr;
85 int x;
86
87 cacheValid = false;
88 va &= ~(PTE.size()-1);
89 /* tr.va = va;
90 tr.size = PTE.size() - 1;
91 tr.contextId = context_id;
92 tr.partitionId = partition_id;
93 tr.real = real;
94*/
95
96 DPRINTF(TLB, "TLB: Inserting TLB Entry; va=%#x pa=%#x pid=%d cid=%d r=%d entryid=%d\n",
97 va, PTE.paddr(), partition_id, context_id, (int)real, entry);
98
99 // Demap any entry that conflicts
100 for (x = 0; x < size; x++) {
101 if (tlb[x].range.real == real &&
102 tlb[x].range.partitionId == partition_id &&
103 tlb[x].range.va < va + PTE.size() - 1 &&
104 tlb[x].range.va + tlb[x].range.size >= va &&
105 (real || tlb[x].range.contextId == context_id ))
106 {
107 if (tlb[x].valid) {
108 freeList.push_front(&tlb[x]);
109 DPRINTF(TLB, "TLB: Conflicting entry %#X , deleting it\n", x);
110
111 tlb[x].valid = false;
112 if (tlb[x].used) {
113 tlb[x].used = false;
114 usedEntries--;
115 }
116 lookupTable.erase(tlb[x].range);
117 }
118 }
119 }
120
121
122/*
123 i = lookupTable.find(tr);
124 if (i != lookupTable.end()) {
125 i->second->valid = false;
126 if (i->second->used) {
127 i->second->used = false;
128 usedEntries--;
129 }
130 freeList.push_front(i->second);
131 DPRINTF(TLB, "TLB: Found conflicting entry %#X , deleting it\n",
132 i->second);
133 lookupTable.erase(i);
134 }
135*/
136
137 if (entry != -1) {
138 assert(entry < size && entry >= 0);
139 new_entry = &tlb[entry];
140 } else {
141 if (!freeList.empty()) {
142 new_entry = freeList.front();
143 } else {
144 x = lastReplaced;
145 do {
146 ++x;
147 if (x == size)
148 x = 0;
149 if (x == lastReplaced)
150 goto insertAllLocked;
151 } while (tlb[x].pte.locked());
152 lastReplaced = x;
153 new_entry = &tlb[x];
154 }
155 /*
156 for (x = 0; x < size; x++) {
157 if (!tlb[x].valid || !tlb[x].used) {
158 new_entry = &tlb[x];
159 break;
160 }
161 }*/
162 }
163
164insertAllLocked:
165 // Update the last ently if their all locked
166 if (!new_entry) {
167 new_entry = &tlb[size-1];
168 }
169
170 freeList.remove(new_entry);
171 if (new_entry->valid && new_entry->used)
172 usedEntries--;
59
60 for (int x = 0; x < size; x++)
61 freeList.push_back(&tlb[x]);
62}
63
64void
65TLB::clearUsedBits()
66{
67 MapIter i;
68 for (i = lookupTable.begin(); i != lookupTable.end(); i++) {
69 TlbEntry *t = i->second;
70 if (!t->pte.locked()) {
71 t->used = false;
72 usedEntries--;
73 }
74 }
75}
76
77
78void
79TLB::insert(Addr va, int partition_id, int context_id, bool real,
80 const PageTableEntry& PTE, int entry)
81{
82
83
84 MapIter i;
85 TlbEntry *new_entry = NULL;
86// TlbRange tr;
87 int x;
88
89 cacheValid = false;
90 va &= ~(PTE.size()-1);
91 /* tr.va = va;
92 tr.size = PTE.size() - 1;
93 tr.contextId = context_id;
94 tr.partitionId = partition_id;
95 tr.real = real;
96*/
97
98 DPRINTF(TLB, "TLB: Inserting TLB Entry; va=%#x pa=%#x pid=%d cid=%d r=%d entryid=%d\n",
99 va, PTE.paddr(), partition_id, context_id, (int)real, entry);
100
101 // Demap any entry that conflicts
102 for (x = 0; x < size; x++) {
103 if (tlb[x].range.real == real &&
104 tlb[x].range.partitionId == partition_id &&
105 tlb[x].range.va < va + PTE.size() - 1 &&
106 tlb[x].range.va + tlb[x].range.size >= va &&
107 (real || tlb[x].range.contextId == context_id ))
108 {
109 if (tlb[x].valid) {
110 freeList.push_front(&tlb[x]);
111 DPRINTF(TLB, "TLB: Conflicting entry %#X , deleting it\n", x);
112
113 tlb[x].valid = false;
114 if (tlb[x].used) {
115 tlb[x].used = false;
116 usedEntries--;
117 }
118 lookupTable.erase(tlb[x].range);
119 }
120 }
121 }
122
123
124/*
125 i = lookupTable.find(tr);
126 if (i != lookupTable.end()) {
127 i->second->valid = false;
128 if (i->second->used) {
129 i->second->used = false;
130 usedEntries--;
131 }
132 freeList.push_front(i->second);
133 DPRINTF(TLB, "TLB: Found conflicting entry %#X , deleting it\n",
134 i->second);
135 lookupTable.erase(i);
136 }
137*/
138
139 if (entry != -1) {
140 assert(entry < size && entry >= 0);
141 new_entry = &tlb[entry];
142 } else {
143 if (!freeList.empty()) {
144 new_entry = freeList.front();
145 } else {
146 x = lastReplaced;
147 do {
148 ++x;
149 if (x == size)
150 x = 0;
151 if (x == lastReplaced)
152 goto insertAllLocked;
153 } while (tlb[x].pte.locked());
154 lastReplaced = x;
155 new_entry = &tlb[x];
156 }
157 /*
158 for (x = 0; x < size; x++) {
159 if (!tlb[x].valid || !tlb[x].used) {
160 new_entry = &tlb[x];
161 break;
162 }
163 }*/
164 }
165
166insertAllLocked:
167 // Update the last ently if their all locked
168 if (!new_entry) {
169 new_entry = &tlb[size-1];
170 }
171
172 freeList.remove(new_entry);
173 if (new_entry->valid && new_entry->used)
174 usedEntries--;
175 if (new_entry->valid)
176 lookupTable.erase(new_entry->range);
173
177
174 lookupTable.erase(new_entry->range);
175
178
176
177 assert(PTE.valid());
178 new_entry->range.va = va;
179 new_entry->range.size = PTE.size() - 1;
180 new_entry->range.partitionId = partition_id;
181 new_entry->range.contextId = context_id;
182 new_entry->range.real = real;
183 new_entry->pte = PTE;
184 new_entry->used = true;;
185 new_entry->valid = true;
186 usedEntries++;
187
188
189
190 i = lookupTable.insert(new_entry->range, new_entry);
191 assert(i != lookupTable.end());
192
193 // If all entries have there used bit set, clear it on them all, but the
194 // one we just inserted
195 if (usedEntries == size) {
196 clearUsedBits();
197 new_entry->used = true;
198 usedEntries++;
199 }
200
201}
202
203
204TlbEntry*
205TLB::lookup(Addr va, int partition_id, bool real, int context_id)
206{
207 MapIter i;
208 TlbRange tr;
209 TlbEntry *t;
210
211 DPRINTF(TLB, "TLB: Looking up entry va=%#x pid=%d cid=%d r=%d\n",
212 va, partition_id, context_id, real);
213 // Assemble full address structure
214 tr.va = va;
215 tr.size = MachineBytes;
216 tr.contextId = context_id;
217 tr.partitionId = partition_id;
218 tr.real = real;
219
220 // Try to find the entry
221 i = lookupTable.find(tr);
222 if (i == lookupTable.end()) {
223 DPRINTF(TLB, "TLB: No valid entry found\n");
224 return NULL;
225 }
226
227 // Mark the entries used bit and clear other used bits in needed
228 t = i->second;
229 DPRINTF(TLB, "TLB: Valid entry found pa: %#x size: %#x\n", t->pte.paddr(),
230 t->pte.size());
231 if (!t->used) {
232 t->used = true;
233 usedEntries++;
234 if (usedEntries == size) {
235 clearUsedBits();
236 t->used = true;
237 usedEntries++;
238 }
239 }
240
241 return t;
242}
243
244void
245TLB::dumpAll()
246{
247 MapIter i;
248 for (int x = 0; x < size; x++) {
249 if (tlb[x].valid) {
250 DPRINTFN("%4d: %#2x:%#2x %c %#4x %#8x %#8x %#16x\n",
251 x, tlb[x].range.partitionId, tlb[x].range.contextId,
252 tlb[x].range.real ? 'R' : ' ', tlb[x].range.size,
253 tlb[x].range.va, tlb[x].pte.paddr(), tlb[x].pte());
254 }
255 }
256}
257
258void
259TLB::demapPage(Addr va, int partition_id, bool real, int context_id)
260{
261 TlbRange tr;
262 MapIter i;
263
264 DPRINTF(IPR, "TLB: Demapping Page va=%#x pid=%#d cid=%d r=%d\n",
265 va, partition_id, context_id, real);
266
267 cacheValid = false;
268
269 // Assemble full address structure
270 tr.va = va;
271 tr.size = MachineBytes;
272 tr.contextId = context_id;
273 tr.partitionId = partition_id;
274 tr.real = real;
275
276 // Demap any entry that conflicts
277 i = lookupTable.find(tr);
278 if (i != lookupTable.end()) {
279 DPRINTF(IPR, "TLB: Demapped page\n");
280 i->second->valid = false;
281 if (i->second->used) {
282 i->second->used = false;
283 usedEntries--;
284 }
285 freeList.push_front(i->second);
286 lookupTable.erase(i);
287 }
288}
289
290void
291TLB::demapContext(int partition_id, int context_id)
292{
293 int x;
294 DPRINTF(IPR, "TLB: Demapping Context pid=%#d cid=%d\n",
295 partition_id, context_id);
296 cacheValid = false;
297 for (x = 0; x < size; x++) {
298 if (tlb[x].range.contextId == context_id &&
299 tlb[x].range.partitionId == partition_id) {
300 if (tlb[x].valid == true) {
301 freeList.push_front(&tlb[x]);
302 }
303 tlb[x].valid = false;
304 if (tlb[x].used) {
305 tlb[x].used = false;
306 usedEntries--;
307 }
308 lookupTable.erase(tlb[x].range);
309 }
310 }
311}
312
313void
314TLB::demapAll(int partition_id)
315{
316 int x;
317 DPRINTF(TLB, "TLB: Demapping All pid=%#d\n", partition_id);
318 cacheValid = false;
319 for (x = 0; x < size; x++) {
320 if (!tlb[x].pte.locked() && tlb[x].range.partitionId == partition_id) {
321 if (tlb[x].valid == true){
322 freeList.push_front(&tlb[x]);
323 }
324 tlb[x].valid = false;
325 if (tlb[x].used) {
326 tlb[x].used = false;
327 usedEntries--;
328 }
329 lookupTable.erase(tlb[x].range);
330 }
331 }
332}
333
334void
335TLB::invalidateAll()
336{
337 int x;
338 cacheValid = false;
339
340 freeList.clear();
341 lookupTable.clear();
342 for (x = 0; x < size; x++) {
343 if (tlb[x].valid == true)
344 freeList.push_back(&tlb[x]);
345 tlb[x].valid = false;
346 tlb[x].used = false;
347 }
348 usedEntries = 0;
349}
350
351uint64_t
352TLB::TteRead(int entry) {
353 if (entry >= size)
354 panic("entry: %d\n", entry);
355
356 assert(entry < size);
357 if (tlb[entry].valid)
358 return tlb[entry].pte();
359 else
360 return (uint64_t)-1ll;
361}
362
363uint64_t
364TLB::TagRead(int entry) {
365 assert(entry < size);
366 uint64_t tag;
367 if (!tlb[entry].valid)
368 return (uint64_t)-1ll;
369
370 tag = tlb[entry].range.contextId;
371 tag |= tlb[entry].range.va;
372 tag |= (uint64_t)tlb[entry].range.partitionId << 61;
373 tag |= tlb[entry].range.real ? ULL(1) << 60 : 0;
374 tag |= (uint64_t)~tlb[entry].pte._size() << 56;
375 return tag;
376}
377
378bool
379TLB::validVirtualAddress(Addr va, bool am)
380{
381 if (am)
382 return true;
383 if (va >= StartVAddrHole && va <= EndVAddrHole)
384 return false;
385 return true;
386}
387
388void
389TLB::writeSfsr(ThreadContext *tc, int reg, bool write, ContextType ct,
390 bool se, FaultTypes ft, int asi)
391{
392 uint64_t sfsr;
393 sfsr = tc->readMiscReg(reg);
394
395 if (sfsr & 0x1)
396 sfsr = 0x3;
397 else
398 sfsr = 1;
399
400 if (write)
401 sfsr |= 1 << 2;
402 sfsr |= ct << 4;
403 if (se)
404 sfsr |= 1 << 6;
405 sfsr |= ft << 7;
406 sfsr |= asi << 16;
407 tc->setMiscRegWithEffect(reg, sfsr);
408}
409
410void
411TLB::writeTagAccess(ThreadContext *tc, int reg, Addr va, int context)
412{
413 DPRINTF(TLB, "TLB: Writing Tag Access: va: %#X ctx: %#X value: %#X\n",
414 va, context, mbits(va, 63,13) | mbits(context,12,0));
415
416 tc->setMiscRegWithEffect(reg, mbits(va, 63,13) | mbits(context,12,0));
417}
418
419void
420ITB::writeSfsr(ThreadContext *tc, bool write, ContextType ct,
421 bool se, FaultTypes ft, int asi)
422{
423 DPRINTF(TLB, "TLB: ITB Fault: w=%d ct=%d ft=%d asi=%d\n",
424 (int)write, ct, ft, asi);
425 TLB::writeSfsr(tc, MISCREG_MMU_ITLB_SFSR, write, ct, se, ft, asi);
426}
427
428void
429ITB::writeTagAccess(ThreadContext *tc, Addr va, int context)
430{
431 TLB::writeTagAccess(tc, MISCREG_MMU_ITLB_TAG_ACCESS, va, context);
432}
433
434void
435DTB::writeSfr(ThreadContext *tc, Addr a, bool write, ContextType ct,
436 bool se, FaultTypes ft, int asi)
437{
438 DPRINTF(TLB, "TLB: DTB Fault: A=%#x w=%d ct=%d ft=%d asi=%d\n",
439 a, (int)write, ct, ft, asi);
440 TLB::writeSfsr(tc, MISCREG_MMU_DTLB_SFSR, write, ct, se, ft, asi);
441 tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_SFAR, a);
442}
443
444void
445DTB::writeTagAccess(ThreadContext *tc, Addr va, int context)
446{
447 TLB::writeTagAccess(tc, MISCREG_MMU_DTLB_TAG_ACCESS, va, context);
448}
449
450
451
452Fault
453ITB::translate(RequestPtr &req, ThreadContext *tc)
454{
455 uint64_t tlbdata = tc->readMiscReg(MISCREG_TLB_DATA);
456
457 Addr vaddr = req->getVaddr();
458 TlbEntry *e;
459
460 assert(req->getAsi() == ASI_IMPLICIT);
461
462 DPRINTF(TLB, "TLB: ITB Request to translate va=%#x size=%d\n",
463 vaddr, req->getSize());
464
465 // Be fast if we can!
466 if (cacheValid && cacheState == tlbdata) {
467 if (cacheEntry) {
468 if (cacheEntry->range.va < vaddr + sizeof(MachInst) &&
469 cacheEntry->range.va + cacheEntry->range.size >= vaddr) {
470 req->setPaddr(cacheEntry->pte.paddr() & ~(cacheEntry->pte.size()-1) |
471 vaddr & cacheEntry->pte.size()-1 );
472 return NoFault;
473 }
474 } else {
475 req->setPaddr(vaddr & PAddrImplMask);
476 return NoFault;
477 }
478 }
479
480 bool hpriv = bits(tlbdata,0,0);
481 bool red = bits(tlbdata,1,1);
482 bool priv = bits(tlbdata,2,2);
483 bool addr_mask = bits(tlbdata,3,3);
484 bool lsu_im = bits(tlbdata,4,4);
485
486 int part_id = bits(tlbdata,15,8);
487 int tl = bits(tlbdata,18,16);
488 int pri_context = bits(tlbdata,47,32);
489 int context;
490 ContextType ct;
491 int asi;
492 bool real = false;
493
494 DPRINTF(TLB, "TLB: priv:%d hpriv:%d red:%d lsuim:%d part_id: %#X\n",
495 priv, hpriv, red, lsu_im, part_id);
496
497 if (tl > 0) {
498 asi = ASI_N;
499 ct = Nucleus;
500 context = 0;
501 } else {
502 asi = ASI_P;
503 ct = Primary;
504 context = pri_context;
505 }
506
507 if ( hpriv || red ) {
508 cacheValid = true;
509 cacheState = tlbdata;
510 cacheEntry = NULL;
511 req->setPaddr(vaddr & PAddrImplMask);
512 return NoFault;
513 }
514
515 // If the access is unaligned trap
516 if (vaddr & 0x3) {
517 writeSfsr(tc, false, ct, false, OtherFault, asi);
518 return new MemAddressNotAligned;
519 }
520
521 if (addr_mask)
522 vaddr = vaddr & VAddrAMask;
523
524 if (!validVirtualAddress(vaddr, addr_mask)) {
525 writeSfsr(tc, false, ct, false, VaOutOfRange, asi);
526 return new InstructionAccessException;
527 }
528
529 if (!lsu_im) {
530 e = lookup(vaddr, part_id, true);
531 real = true;
532 context = 0;
533 } else {
534 e = lookup(vaddr, part_id, false, context);
535 }
536
537 if (e == NULL || !e->valid) {
538 writeTagAccess(tc, vaddr, context);
539 if (real)
540 return new InstructionRealTranslationMiss;
541 else
542 return new FastInstructionAccessMMUMiss;
543 }
544
545 // were not priviledged accesing priv page
546 if (!priv && e->pte.priv()) {
547 writeTagAccess(tc, vaddr, context);
548 writeSfsr(tc, false, ct, false, PrivViolation, asi);
549 return new InstructionAccessException;
550 }
551
552 // cache translation date for next translation
553 cacheValid = true;
554 cacheState = tlbdata;
555 cacheEntry = e;
556
557 req->setPaddr(e->pte.paddr() & ~(e->pte.size()-1) |
558 vaddr & e->pte.size()-1 );
559 DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr());
560 return NoFault;
561}
562
563
564
565Fault
566DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
567{
568 /* @todo this could really use some profiling and fixing to make it faster! */
569 uint64_t tlbdata = tc->readMiscReg(MISCREG_TLB_DATA);
570 Addr vaddr = req->getVaddr();
571 Addr size = req->getSize();
572 ASI asi;
573 asi = (ASI)req->getAsi();
574 bool implicit = false;
575 bool hpriv = bits(tlbdata,0,0);
576
577 DPRINTF(TLB, "TLB: DTB Request to translate va=%#x size=%d asi=%#x\n",
578 vaddr, size, asi);
579
179 assert(PTE.valid());
180 new_entry->range.va = va;
181 new_entry->range.size = PTE.size() - 1;
182 new_entry->range.partitionId = partition_id;
183 new_entry->range.contextId = context_id;
184 new_entry->range.real = real;
185 new_entry->pte = PTE;
186 new_entry->used = true;;
187 new_entry->valid = true;
188 usedEntries++;
189
190
191
192 i = lookupTable.insert(new_entry->range, new_entry);
193 assert(i != lookupTable.end());
194
195 // If all entries have there used bit set, clear it on them all, but the
196 // one we just inserted
197 if (usedEntries == size) {
198 clearUsedBits();
199 new_entry->used = true;
200 usedEntries++;
201 }
202
203}
204
205
206TlbEntry*
207TLB::lookup(Addr va, int partition_id, bool real, int context_id)
208{
209 MapIter i;
210 TlbRange tr;
211 TlbEntry *t;
212
213 DPRINTF(TLB, "TLB: Looking up entry va=%#x pid=%d cid=%d r=%d\n",
214 va, partition_id, context_id, real);
215 // Assemble full address structure
216 tr.va = va;
217 tr.size = MachineBytes;
218 tr.contextId = context_id;
219 tr.partitionId = partition_id;
220 tr.real = real;
221
222 // Try to find the entry
223 i = lookupTable.find(tr);
224 if (i == lookupTable.end()) {
225 DPRINTF(TLB, "TLB: No valid entry found\n");
226 return NULL;
227 }
228
229 // Mark the entries used bit and clear other used bits in needed
230 t = i->second;
231 DPRINTF(TLB, "TLB: Valid entry found pa: %#x size: %#x\n", t->pte.paddr(),
232 t->pte.size());
233 if (!t->used) {
234 t->used = true;
235 usedEntries++;
236 if (usedEntries == size) {
237 clearUsedBits();
238 t->used = true;
239 usedEntries++;
240 }
241 }
242
243 return t;
244}
245
246void
247TLB::dumpAll()
248{
249 MapIter i;
250 for (int x = 0; x < size; x++) {
251 if (tlb[x].valid) {
252 DPRINTFN("%4d: %#2x:%#2x %c %#4x %#8x %#8x %#16x\n",
253 x, tlb[x].range.partitionId, tlb[x].range.contextId,
254 tlb[x].range.real ? 'R' : ' ', tlb[x].range.size,
255 tlb[x].range.va, tlb[x].pte.paddr(), tlb[x].pte());
256 }
257 }
258}
259
260void
261TLB::demapPage(Addr va, int partition_id, bool real, int context_id)
262{
263 TlbRange tr;
264 MapIter i;
265
266 DPRINTF(IPR, "TLB: Demapping Page va=%#x pid=%#d cid=%d r=%d\n",
267 va, partition_id, context_id, real);
268
269 cacheValid = false;
270
271 // Assemble full address structure
272 tr.va = va;
273 tr.size = MachineBytes;
274 tr.contextId = context_id;
275 tr.partitionId = partition_id;
276 tr.real = real;
277
278 // Demap any entry that conflicts
279 i = lookupTable.find(tr);
280 if (i != lookupTable.end()) {
281 DPRINTF(IPR, "TLB: Demapped page\n");
282 i->second->valid = false;
283 if (i->second->used) {
284 i->second->used = false;
285 usedEntries--;
286 }
287 freeList.push_front(i->second);
288 lookupTable.erase(i);
289 }
290}
291
292void
293TLB::demapContext(int partition_id, int context_id)
294{
295 int x;
296 DPRINTF(IPR, "TLB: Demapping Context pid=%#d cid=%d\n",
297 partition_id, context_id);
298 cacheValid = false;
299 for (x = 0; x < size; x++) {
300 if (tlb[x].range.contextId == context_id &&
301 tlb[x].range.partitionId == partition_id) {
302 if (tlb[x].valid == true) {
303 freeList.push_front(&tlb[x]);
304 }
305 tlb[x].valid = false;
306 if (tlb[x].used) {
307 tlb[x].used = false;
308 usedEntries--;
309 }
310 lookupTable.erase(tlb[x].range);
311 }
312 }
313}
314
315void
316TLB::demapAll(int partition_id)
317{
318 int x;
319 DPRINTF(TLB, "TLB: Demapping All pid=%#d\n", partition_id);
320 cacheValid = false;
321 for (x = 0; x < size; x++) {
322 if (!tlb[x].pte.locked() && tlb[x].range.partitionId == partition_id) {
323 if (tlb[x].valid == true){
324 freeList.push_front(&tlb[x]);
325 }
326 tlb[x].valid = false;
327 if (tlb[x].used) {
328 tlb[x].used = false;
329 usedEntries--;
330 }
331 lookupTable.erase(tlb[x].range);
332 }
333 }
334}
335
336void
337TLB::invalidateAll()
338{
339 int x;
340 cacheValid = false;
341
342 freeList.clear();
343 lookupTable.clear();
344 for (x = 0; x < size; x++) {
345 if (tlb[x].valid == true)
346 freeList.push_back(&tlb[x]);
347 tlb[x].valid = false;
348 tlb[x].used = false;
349 }
350 usedEntries = 0;
351}
352
353uint64_t
354TLB::TteRead(int entry) {
355 if (entry >= size)
356 panic("entry: %d\n", entry);
357
358 assert(entry < size);
359 if (tlb[entry].valid)
360 return tlb[entry].pte();
361 else
362 return (uint64_t)-1ll;
363}
364
365uint64_t
366TLB::TagRead(int entry) {
367 assert(entry < size);
368 uint64_t tag;
369 if (!tlb[entry].valid)
370 return (uint64_t)-1ll;
371
372 tag = tlb[entry].range.contextId;
373 tag |= tlb[entry].range.va;
374 tag |= (uint64_t)tlb[entry].range.partitionId << 61;
375 tag |= tlb[entry].range.real ? ULL(1) << 60 : 0;
376 tag |= (uint64_t)~tlb[entry].pte._size() << 56;
377 return tag;
378}
379
380bool
381TLB::validVirtualAddress(Addr va, bool am)
382{
383 if (am)
384 return true;
385 if (va >= StartVAddrHole && va <= EndVAddrHole)
386 return false;
387 return true;
388}
389
390void
391TLB::writeSfsr(ThreadContext *tc, int reg, bool write, ContextType ct,
392 bool se, FaultTypes ft, int asi)
393{
394 uint64_t sfsr;
395 sfsr = tc->readMiscReg(reg);
396
397 if (sfsr & 0x1)
398 sfsr = 0x3;
399 else
400 sfsr = 1;
401
402 if (write)
403 sfsr |= 1 << 2;
404 sfsr |= ct << 4;
405 if (se)
406 sfsr |= 1 << 6;
407 sfsr |= ft << 7;
408 sfsr |= asi << 16;
409 tc->setMiscRegWithEffect(reg, sfsr);
410}
411
412void
413TLB::writeTagAccess(ThreadContext *tc, int reg, Addr va, int context)
414{
415 DPRINTF(TLB, "TLB: Writing Tag Access: va: %#X ctx: %#X value: %#X\n",
416 va, context, mbits(va, 63,13) | mbits(context,12,0));
417
418 tc->setMiscRegWithEffect(reg, mbits(va, 63,13) | mbits(context,12,0));
419}
420
421void
422ITB::writeSfsr(ThreadContext *tc, bool write, ContextType ct,
423 bool se, FaultTypes ft, int asi)
424{
425 DPRINTF(TLB, "TLB: ITB Fault: w=%d ct=%d ft=%d asi=%d\n",
426 (int)write, ct, ft, asi);
427 TLB::writeSfsr(tc, MISCREG_MMU_ITLB_SFSR, write, ct, se, ft, asi);
428}
429
430void
431ITB::writeTagAccess(ThreadContext *tc, Addr va, int context)
432{
433 TLB::writeTagAccess(tc, MISCREG_MMU_ITLB_TAG_ACCESS, va, context);
434}
435
436void
437DTB::writeSfr(ThreadContext *tc, Addr a, bool write, ContextType ct,
438 bool se, FaultTypes ft, int asi)
439{
440 DPRINTF(TLB, "TLB: DTB Fault: A=%#x w=%d ct=%d ft=%d asi=%d\n",
441 a, (int)write, ct, ft, asi);
442 TLB::writeSfsr(tc, MISCREG_MMU_DTLB_SFSR, write, ct, se, ft, asi);
443 tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_SFAR, a);
444}
445
446void
447DTB::writeTagAccess(ThreadContext *tc, Addr va, int context)
448{
449 TLB::writeTagAccess(tc, MISCREG_MMU_DTLB_TAG_ACCESS, va, context);
450}
451
452
453
454Fault
455ITB::translate(RequestPtr &req, ThreadContext *tc)
456{
457 uint64_t tlbdata = tc->readMiscReg(MISCREG_TLB_DATA);
458
459 Addr vaddr = req->getVaddr();
460 TlbEntry *e;
461
462 assert(req->getAsi() == ASI_IMPLICIT);
463
464 DPRINTF(TLB, "TLB: ITB Request to translate va=%#x size=%d\n",
465 vaddr, req->getSize());
466
467 // Be fast if we can!
468 if (cacheValid && cacheState == tlbdata) {
469 if (cacheEntry) {
470 if (cacheEntry->range.va < vaddr + sizeof(MachInst) &&
471 cacheEntry->range.va + cacheEntry->range.size >= vaddr) {
472 req->setPaddr(cacheEntry->pte.paddr() & ~(cacheEntry->pte.size()-1) |
473 vaddr & cacheEntry->pte.size()-1 );
474 return NoFault;
475 }
476 } else {
477 req->setPaddr(vaddr & PAddrImplMask);
478 return NoFault;
479 }
480 }
481
482 bool hpriv = bits(tlbdata,0,0);
483 bool red = bits(tlbdata,1,1);
484 bool priv = bits(tlbdata,2,2);
485 bool addr_mask = bits(tlbdata,3,3);
486 bool lsu_im = bits(tlbdata,4,4);
487
488 int part_id = bits(tlbdata,15,8);
489 int tl = bits(tlbdata,18,16);
490 int pri_context = bits(tlbdata,47,32);
491 int context;
492 ContextType ct;
493 int asi;
494 bool real = false;
495
496 DPRINTF(TLB, "TLB: priv:%d hpriv:%d red:%d lsuim:%d part_id: %#X\n",
497 priv, hpriv, red, lsu_im, part_id);
498
499 if (tl > 0) {
500 asi = ASI_N;
501 ct = Nucleus;
502 context = 0;
503 } else {
504 asi = ASI_P;
505 ct = Primary;
506 context = pri_context;
507 }
508
509 if ( hpriv || red ) {
510 cacheValid = true;
511 cacheState = tlbdata;
512 cacheEntry = NULL;
513 req->setPaddr(vaddr & PAddrImplMask);
514 return NoFault;
515 }
516
517 // If the access is unaligned trap
518 if (vaddr & 0x3) {
519 writeSfsr(tc, false, ct, false, OtherFault, asi);
520 return new MemAddressNotAligned;
521 }
522
523 if (addr_mask)
524 vaddr = vaddr & VAddrAMask;
525
526 if (!validVirtualAddress(vaddr, addr_mask)) {
527 writeSfsr(tc, false, ct, false, VaOutOfRange, asi);
528 return new InstructionAccessException;
529 }
530
531 if (!lsu_im) {
532 e = lookup(vaddr, part_id, true);
533 real = true;
534 context = 0;
535 } else {
536 e = lookup(vaddr, part_id, false, context);
537 }
538
539 if (e == NULL || !e->valid) {
540 writeTagAccess(tc, vaddr, context);
541 if (real)
542 return new InstructionRealTranslationMiss;
543 else
544 return new FastInstructionAccessMMUMiss;
545 }
546
547 // were not priviledged accesing priv page
548 if (!priv && e->pte.priv()) {
549 writeTagAccess(tc, vaddr, context);
550 writeSfsr(tc, false, ct, false, PrivViolation, asi);
551 return new InstructionAccessException;
552 }
553
554 // cache translation date for next translation
555 cacheValid = true;
556 cacheState = tlbdata;
557 cacheEntry = e;
558
559 req->setPaddr(e->pte.paddr() & ~(e->pte.size()-1) |
560 vaddr & e->pte.size()-1 );
561 DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr());
562 return NoFault;
563}
564
565
566
567Fault
568DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
569{
570 /* @todo this could really use some profiling and fixing to make it faster! */
571 uint64_t tlbdata = tc->readMiscReg(MISCREG_TLB_DATA);
572 Addr vaddr = req->getVaddr();
573 Addr size = req->getSize();
574 ASI asi;
575 asi = (ASI)req->getAsi();
576 bool implicit = false;
577 bool hpriv = bits(tlbdata,0,0);
578
579 DPRINTF(TLB, "TLB: DTB Request to translate va=%#x size=%d asi=%#x\n",
580 vaddr, size, asi);
581
582 if (lookupTable.size() != 64 - freeList.size())
583 panic("Lookup table size: %d tlb size: %d\n", lookupTable.size(),
584 freeList.size());
580 if (asi == ASI_IMPLICIT)
581 implicit = true;
582
583 if (hpriv && implicit) {
584 req->setPaddr(vaddr & PAddrImplMask);
585 return NoFault;
586 }
587
588 // Be fast if we can!
589 if (cacheValid && cacheState == tlbdata) {
590 if (cacheEntry[0] && cacheAsi[0] == asi && cacheEntry[0]->range.va < vaddr + size &&
591 cacheEntry[0]->range.va + cacheEntry[0]->range.size > vaddr &&
592 (!write || cacheEntry[0]->pte.writable())) {
593 req->setPaddr(cacheEntry[0]->pte.paddr() & ~(cacheEntry[0]->pte.size()-1) |
594 vaddr & cacheEntry[0]->pte.size()-1 );
595 return NoFault;
596 }
597 if (cacheEntry[1] && cacheAsi[1] == asi && cacheEntry[1]->range.va < vaddr + size &&
598 cacheEntry[1]->range.va + cacheEntry[1]->range.size > vaddr &&
599 (!write || cacheEntry[1]->pte.writable())) {
600 req->setPaddr(cacheEntry[1]->pte.paddr() & ~(cacheEntry[1]->pte.size()-1) |
601 vaddr & cacheEntry[1]->pte.size()-1 );
602 return NoFault;
603 }
604 }
605
606 bool red = bits(tlbdata,1,1);
607 bool priv = bits(tlbdata,2,2);
608 bool addr_mask = bits(tlbdata,3,3);
609 bool lsu_dm = bits(tlbdata,5,5);
610
611 int part_id = bits(tlbdata,15,8);
612 int tl = bits(tlbdata,18,16);
613 int pri_context = bits(tlbdata,47,32);
614 int sec_context = bits(tlbdata,63,48);
615
616 bool real = false;
617 ContextType ct = Primary;
618 int context = 0;
619
620 TlbEntry *e;
621
622 DPRINTF(TLB, "TLB: priv:%d hpriv:%d red:%d lsudm:%d part_id: %#X\n",
623 priv, hpriv, red, lsu_dm, part_id);
624
625 if (implicit) {
626 if (tl > 0) {
627 asi = ASI_N;
628 ct = Nucleus;
629 context = 0;
630 } else {
631 asi = ASI_P;
632 ct = Primary;
633 context = pri_context;
634 }
635 } else {
636 // We need to check for priv level/asi priv
637 if (!priv && !hpriv && !AsiIsUnPriv(asi)) {
638 // It appears that context should be Nucleus in these cases?
639 writeSfr(tc, vaddr, write, Nucleus, false, IllegalAsi, asi);
640 return new PrivilegedAction;
641 }
642
643 if (!hpriv && AsiIsHPriv(asi)) {
644 writeSfr(tc, vaddr, write, Nucleus, false, IllegalAsi, asi);
645 return new DataAccessException;
646 }
647
648 if (AsiIsPrimary(asi)) {
649 context = pri_context;
650 ct = Primary;
651 } else if (AsiIsSecondary(asi)) {
652 context = sec_context;
653 ct = Secondary;
654 } else if (AsiIsNucleus(asi)) {
655 ct = Nucleus;
656 context = 0;
657 } else { // ????
658 ct = Primary;
659 context = pri_context;
660 }
661 }
662
663 if (!implicit && asi != ASI_P && asi != ASI_S) {
664 if (AsiIsLittle(asi))
665 panic("Little Endian ASIs not supported\n");
666 if (AsiIsBlock(asi))
667 panic("Block ASIs not supported\n");
668 if (AsiIsNoFault(asi))
669 panic("No Fault ASIs not supported\n");
670
671 if (AsiIsPartialStore(asi))
672 panic("Partial Store ASIs not supported\n");
673 if (AsiIsInterrupt(asi))
674 panic("Interrupt ASIs not supported\n");
675
676 if (AsiIsMmu(asi))
677 goto handleMmuRegAccess;
678 if (AsiIsScratchPad(asi))
679 goto handleScratchRegAccess;
680 if (AsiIsQueue(asi))
681 goto handleQueueRegAccess;
682 if (AsiIsSparcError(asi))
683 goto handleSparcErrorRegAccess;
684
685 if (!AsiIsReal(asi) && !AsiIsNucleus(asi) && !AsiIsAsIfUser(asi) &&
686 !AsiIsTwin(asi))
687 panic("Accessing ASI %#X. Should we?\n", asi);
688 }
689
690 // If the asi is unaligned trap
691 if (vaddr & size-1) {
692 writeSfr(tc, vaddr, false, ct, false, OtherFault, asi);
693 return new MemAddressNotAligned;
694 }
695
696 if (addr_mask)
697 vaddr = vaddr & VAddrAMask;
698
699 if (!validVirtualAddress(vaddr, addr_mask)) {
700 writeSfr(tc, vaddr, false, ct, true, VaOutOfRange, asi);
701 return new DataAccessException;
702 }
703
704
705 if ((!lsu_dm && !hpriv && !red) || AsiIsReal(asi)) {
706 real = true;
707 context = 0;
708 };
709
710 if (hpriv && (implicit || (!AsiIsAsIfUser(asi) && !AsiIsReal(asi)))) {
711 req->setPaddr(vaddr & PAddrImplMask);
712 return NoFault;
713 }
714
715 e = lookup(vaddr, part_id, real, context);
716
717 if (e == NULL || !e->valid) {
718 writeTagAccess(tc, vaddr, context);
719 DPRINTF(TLB, "TLB: DTB Failed to find matching TLB entry\n");
720 if (real)
721 return new DataRealTranslationMiss;
722 else
723 return new FastDataAccessMMUMiss;
724
725 }
726
727 if (!priv && e->pte.priv()) {
728 writeTagAccess(tc, vaddr, context);
729 writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), PrivViolation, asi);
730 return new DataAccessException;
731 }
732
733 if (write && !e->pte.writable()) {
734 writeTagAccess(tc, vaddr, context);
735 writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), OtherFault, asi);
736 return new FastDataAccessProtection;
737 }
738
739 if (e->pte.nofault() && !AsiIsNoFault(asi)) {
740 writeTagAccess(tc, vaddr, context);
741 writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), LoadFromNfo, asi);
742 return new DataAccessException;
743 }
744
745 if (e->pte.sideffect() && AsiIsNoFault(asi)) {
746 writeTagAccess(tc, vaddr, context);
747 writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), SideEffect, asi);
748 return new DataAccessException;
749 }
750
751
752 if (e->pte.sideffect())
753 req->setFlags(req->getFlags() | UNCACHEABLE);
754
755 // cache translation date for next translation
756 cacheState = tlbdata;
757 if (!cacheValid) {
758 cacheEntry[1] = NULL;
759 cacheEntry[0] = NULL;
760 }
761
762 if (cacheEntry[0] != e && cacheEntry[1] != e) {
763 cacheEntry[1] = cacheEntry[0];
764 cacheEntry[0] = e;
765 cacheAsi[1] = cacheAsi[0];
766 cacheAsi[0] = asi;
767 if (implicit)
768 cacheAsi[0] = (ASI)0;
769 }
770 cacheValid = true;
771 req->setPaddr(e->pte.paddr() & ~(e->pte.size()-1) |
772 vaddr & e->pte.size()-1);
773 DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr());
774 return NoFault;
775 /** Normal flow ends here. */
776
777handleScratchRegAccess:
778 if (vaddr > 0x38 || (vaddr >= 0x20 && vaddr < 0x30 && !hpriv)) {
779 writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi);
780 return new DataAccessException;
781 }
782 goto regAccessOk;
783
784handleQueueRegAccess:
785 if (!priv && !hpriv) {
786 writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi);
787 return new PrivilegedAction;
788 }
789 if (!hpriv && vaddr & 0xF || vaddr > 0x3f8 || vaddr < 0x3c0) {
790 writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi);
791 return new DataAccessException;
792 }
793 goto regAccessOk;
794
795handleSparcErrorRegAccess:
796 if (!hpriv) {
797 if (priv) {
798 writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi);
799 return new DataAccessException;
800 } else {
801 writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi);
802 return new PrivilegedAction;
803 }
804 }
805 goto regAccessOk;
806
807
808regAccessOk:
809handleMmuRegAccess:
810 DPRINTF(TLB, "TLB: DTB Translating MM IPR access\n");
811 req->setMmapedIpr(true);
812 req->setPaddr(req->getVaddr());
813 return NoFault;
814};
815
816Tick
817DTB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
818{
819 Addr va = pkt->getAddr();
820 ASI asi = (ASI)pkt->req->getAsi();
821 uint64_t temp, data;
822 uint64_t tsbtemp, cnftemp;
823
824 DPRINTF(IPR, "Memory Mapped IPR Read: asi=%#X a=%#x\n",
825 (uint32_t)pkt->req->getAsi(), pkt->getAddr());
826
827 switch (asi) {
828 case ASI_LSU_CONTROL_REG:
829 assert(va == 0);
830 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_LSU_CTRL));
831 break;
832 case ASI_MMU:
833 switch (va) {
834 case 0x8:
835 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_P_CONTEXT));
836 break;
837 case 0x10:
838 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_S_CONTEXT));
839 break;
840 default:
841 goto doMmuReadError;
842 }
843 break;
844 case ASI_QUEUE:
845 pkt->set(tc->readMiscRegWithEffect(MISCREG_QUEUE_CPU_MONDO_HEAD +
846 (va >> 4) - 0x3c));
847 break;
848 case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0:
849 assert(va == 0);
850 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS0));
851 break;
852 case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1:
853 assert(va == 0);
854 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS1));
855 break;
856 case ASI_DMMU_CTXT_ZERO_CONFIG:
857 assert(va == 0);
858 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG));
859 break;
860 case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0:
861 assert(va == 0);
862 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS0));
863 break;
864 case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1:
865 assert(va == 0);
866 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS1));
867 break;
868 case ASI_IMMU_CTXT_ZERO_CONFIG:
869 assert(va == 0);
870 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG));
871 break;
872 case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0:
873 assert(va == 0);
874 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS0));
875 break;
876 case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1:
877 assert(va == 0);
878 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS1));
879 break;
880 case ASI_DMMU_CTXT_NONZERO_CONFIG:
881 assert(va == 0);
882 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG));
883 break;
884 case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0:
885 assert(va == 0);
886 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS0));
887 break;
888 case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1:
889 assert(va == 0);
890 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS1));
891 break;
892 case ASI_IMMU_CTXT_NONZERO_CONFIG:
893 assert(va == 0);
894 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG));
895 break;
896 case ASI_SPARC_ERROR_STATUS_REG:
897 warn("returning 0 for SPARC ERROR regsiter read\n");
898 pkt->set((uint64_t)0);
899 break;
900 case ASI_HYP_SCRATCHPAD:
901 case ASI_SCRATCHPAD:
902 pkt->set(tc->readMiscRegWithEffect(MISCREG_SCRATCHPAD_R0 + (va >> 3)));
903 break;
904 case ASI_IMMU:
905 switch (va) {
906 case 0x0:
907 temp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS);
908 pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48);
909 break;
910 case 0x18:
911 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_SFSR));
912 break;
913 case 0x30:
914 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS));
915 break;
916 default:
917 goto doMmuReadError;
918 }
919 break;
920 case ASI_DMMU:
921 switch (va) {
922 case 0x0:
923 temp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS);
924 pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48);
925 break;
926 case 0x18:
927 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_SFSR));
928 break;
929 case 0x20:
930 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_SFAR));
931 break;
932 case 0x30:
933 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS));
934 break;
935 case 0x80:
936 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID));
937 break;
938 default:
939 goto doMmuReadError;
940 }
941 break;
942 case ASI_DMMU_TSB_PS0_PTR_REG:
943 temp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS);
944 if (bits(temp,12,0) == 0) {
945 tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS0);
946 cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG);
947 } else {
948 tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS0);
949 cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG);
950 }
951 data = mbits(tsbtemp,63,13);
952 data |= temp >> (9 + bits(cnftemp,2,0) * 3) &
953 mbits((uint64_t)-1ll,12+bits(tsbtemp,3,0), 4);
954 pkt->set(data);
955 break;
956 case ASI_DMMU_TSB_PS1_PTR_REG:
957 temp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS);
958 if (bits(temp,12,0) == 0) {
959 tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS1);
960 cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG);
961 } else {
962 tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS1);
963 cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG);
964 }
965 data = mbits(tsbtemp,63,13);
966 if (bits(tsbtemp,12,12))
967 data |= ULL(1) << (13+bits(tsbtemp,3,0));
968 data |= temp >> (9 + bits(cnftemp,10,8) * 3) &
969 mbits((uint64_t)-1ll,12+bits(tsbtemp,3,0), 4);
970 pkt->set(data);
971 break;
972 case ASI_IMMU_TSB_PS0_PTR_REG:
973 temp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS);
974 if (bits(temp,12,0) == 0) {
975 tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS0);
976 cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG);
977 } else {
978 tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS0);
979 cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG);
980 }
981 data = mbits(tsbtemp,63,13);
982 data |= temp >> (9 + bits(cnftemp,2,0) * 3) &
983 mbits((uint64_t)-1ll,12+bits(tsbtemp,3,0), 4);
984 pkt->set(data);
985 break;
986 case ASI_IMMU_TSB_PS1_PTR_REG:
987 temp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS);
988 if (bits(temp,12,0) == 0) {
989 tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS1);
990 cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG);
991 } else {
992 tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS1);
993 cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG);
994 }
995 data = mbits(tsbtemp,63,13);
996 if (bits(tsbtemp,12,12))
997 data |= ULL(1) << (13+bits(tsbtemp,3,0));
998 data |= temp >> (9 + bits(cnftemp,10,8) * 3) &
999 mbits((uint64_t)-1ll,12+bits(tsbtemp,3,0), 4);
1000 pkt->set(data);
1001 break;
1002
1003 default:
1004doMmuReadError:
1005 panic("need to impl DTB::doMmuRegRead() got asi=%#x, va=%#x\n",
1006 (uint32_t)asi, va);
1007 }
1008 pkt->result = Packet::Success;
1009 return tc->getCpuPtr()->cycles(1);
1010}
1011
1012Tick
1013DTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
1014{
1015 uint64_t data = gtoh(pkt->get<uint64_t>());
1016 Addr va = pkt->getAddr();
1017 ASI asi = (ASI)pkt->req->getAsi();
1018
1019 Addr ta_insert;
1020 Addr va_insert;
1021 Addr ct_insert;
1022 int part_insert;
1023 int entry_insert = -1;
1024 bool real_insert;
1025 bool ignore;
1026 int part_id;
1027 int ctx_id;
1028 PageTableEntry pte;
1029
1030 DPRINTF(IPR, "Memory Mapped IPR Write: asi=%#X a=%#x d=%#X\n",
1031 (uint32_t)asi, va, data);
1032
1033 switch (asi) {
1034 case ASI_LSU_CONTROL_REG:
1035 assert(va == 0);
1036 tc->setMiscRegWithEffect(MISCREG_MMU_LSU_CTRL, data);
1037 break;
1038 case ASI_MMU:
1039 switch (va) {
1040 case 0x8:
1041 tc->setMiscRegWithEffect(MISCREG_MMU_P_CONTEXT, data);
1042 break;
1043 case 0x10:
1044 tc->setMiscRegWithEffect(MISCREG_MMU_S_CONTEXT, data);
1045 break;
1046 default:
1047 goto doMmuWriteError;
1048 }
1049 break;
1050 case ASI_QUEUE:
1051 assert(mbits(data,13,6) == data);
1052 tc->setMiscRegWithEffect(MISCREG_QUEUE_CPU_MONDO_HEAD +
1053 (va >> 4) - 0x3c, data);
1054 break;
1055 case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0:
1056 assert(va == 0);
1057 tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS0, data);
1058 break;
1059 case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1:
1060 assert(va == 0);
1061 tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS1, data);
1062 break;
1063 case ASI_DMMU_CTXT_ZERO_CONFIG:
1064 assert(va == 0);
1065 tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG, data);
1066 break;
1067 case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0:
1068 assert(va == 0);
1069 tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS0, data);
1070 break;
1071 case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1:
1072 assert(va == 0);
1073 tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS1, data);
1074 break;
1075 case ASI_IMMU_CTXT_ZERO_CONFIG:
1076 assert(va == 0);
1077 tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG, data);
1078 break;
1079 case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0:
1080 assert(va == 0);
1081 tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS0, data);
1082 break;
1083 case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1:
1084 assert(va == 0);
1085 tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS1, data);
1086 break;
1087 case ASI_DMMU_CTXT_NONZERO_CONFIG:
1088 assert(va == 0);
1089 tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG, data);
1090 break;
1091 case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0:
1092 assert(va == 0);
1093 tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS0, data);
1094 break;
1095 case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1:
1096 assert(va == 0);
1097 tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS1, data);
1098 break;
1099 case ASI_IMMU_CTXT_NONZERO_CONFIG:
1100 assert(va == 0);
1101 tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG, data);
1102 break;
1103 case ASI_SPARC_ERROR_EN_REG:
1104 case ASI_SPARC_ERROR_STATUS_REG:
1105 warn("Ignoring write to SPARC ERROR regsiter\n");
1106 break;
1107 case ASI_HYP_SCRATCHPAD:
1108 case ASI_SCRATCHPAD:
1109 tc->setMiscRegWithEffect(MISCREG_SCRATCHPAD_R0 + (va >> 3), data);
1110 break;
1111 case ASI_IMMU:
1112 switch (va) {
1113 case 0x18:
1114 tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_SFSR, data);
1115 break;
1116 case 0x30:
1117 sext<59>(bits(data, 59,0));
1118 tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS, data);
1119 break;
1120 default:
1121 goto doMmuWriteError;
1122 }
1123 break;
1124 case ASI_ITLB_DATA_ACCESS_REG:
1125 entry_insert = bits(va, 8,3);
1126 case ASI_ITLB_DATA_IN_REG:
1127 assert(entry_insert != -1 || mbits(va,10,9) == va);
1128 ta_insert = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS);
1129 va_insert = mbits(ta_insert, 63,13);
1130 ct_insert = mbits(ta_insert, 12,0);
1131 part_insert = tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID);
1132 real_insert = bits(va, 9,9);
1133 pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v :
1134 PageTableEntry::sun4u);
1135 tc->getITBPtr()->insert(va_insert, part_insert, ct_insert, real_insert,
1136 pte, entry_insert);
1137 break;
1138 case ASI_DTLB_DATA_ACCESS_REG:
1139 entry_insert = bits(va, 8,3);
1140 case ASI_DTLB_DATA_IN_REG:
1141 assert(entry_insert != -1 || mbits(va,10,9) == va);
1142 ta_insert = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS);
1143 va_insert = mbits(ta_insert, 63,13);
1144 ct_insert = mbits(ta_insert, 12,0);
1145 part_insert = tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID);
1146 real_insert = bits(va, 9,9);
1147 pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v :
1148 PageTableEntry::sun4u);
1149 insert(va_insert, part_insert, ct_insert, real_insert, pte, entry_insert);
1150 break;
1151 case ASI_IMMU_DEMAP:
1152 ignore = false;
1153 ctx_id = -1;
1154 part_id = tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID);
1155 switch (bits(va,5,4)) {
1156 case 0:
1157 ctx_id = tc->readMiscRegWithEffect(MISCREG_MMU_P_CONTEXT);
1158 break;
1159 case 1:
1160 ignore = true;
1161 break;
1162 case 3:
1163 ctx_id = 0;
1164 break;
1165 default:
1166 ignore = true;
1167 }
1168
1169 switch(bits(va,7,6)) {
1170 case 0: // demap page
1171 if (!ignore)
1172 tc->getITBPtr()->demapPage(mbits(va,63,13), part_id,
1173 bits(va,9,9), ctx_id);
1174 break;
1175 case 1: //demap context
1176 if (!ignore)
1177 tc->getITBPtr()->demapContext(part_id, ctx_id);
1178 break;
1179 case 2:
1180 tc->getITBPtr()->demapAll(part_id);
1181 break;
1182 default:
1183 panic("Invalid type for IMMU demap\n");
1184 }
1185 break;
1186 case ASI_DMMU:
1187 switch (va) {
1188 case 0x18:
1189 tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_SFSR, data);
1190 break;
1191 case 0x30:
1192 sext<59>(bits(data, 59,0));
1193 tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS, data);
1194 break;
1195 case 0x80:
1196 tc->setMiscRegWithEffect(MISCREG_MMU_PART_ID, data);
1197 break;
1198 default:
1199 goto doMmuWriteError;
1200 }
1201 break;
1202 case ASI_DMMU_DEMAP:
1203 ignore = false;
1204 ctx_id = -1;
1205 part_id = tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID);
1206 switch (bits(va,5,4)) {
1207 case 0:
1208 ctx_id = tc->readMiscRegWithEffect(MISCREG_MMU_P_CONTEXT);
1209 break;
1210 case 1:
1211 ctx_id = tc->readMiscRegWithEffect(MISCREG_MMU_S_CONTEXT);
1212 break;
1213 case 3:
1214 ctx_id = 0;
1215 break;
1216 default:
1217 ignore = true;
1218 }
1219
1220 switch(bits(va,7,6)) {
1221 case 0: // demap page
1222 if (!ignore)
1223 demapPage(mbits(va,63,13), part_id, bits(va,9,9), ctx_id);
1224 break;
1225 case 1: //demap context
1226 if (!ignore)
1227 demapContext(part_id, ctx_id);
1228 break;
1229 case 2:
1230 demapAll(part_id);
1231 break;
1232 default:
1233 panic("Invalid type for IMMU demap\n");
1234 }
1235 break;
1236 default:
1237doMmuWriteError:
1238 panic("need to impl DTB::doMmuRegWrite() got asi=%#x, va=%#x d=%#x\n",
1239 (uint32_t)pkt->req->getAsi(), pkt->getAddr(), data);
1240 }
1241 pkt->result = Packet::Success;
1242 return tc->getCpuPtr()->cycles(1);
1243}
1244
1245void
1246TLB::serialize(std::ostream &os)
1247{
1248 panic("Need to implement serialize tlb for SPARC\n");
1249}
1250
1251void
1252TLB::unserialize(Checkpoint *cp, const std::string &section)
1253{
1254 panic("Need to implement unserialize tlb for SPARC\n");
1255}
1256
1257
1258DEFINE_SIM_OBJECT_CLASS_NAME("SparcTLB", TLB)
1259
1260BEGIN_DECLARE_SIM_OBJECT_PARAMS(ITB)
1261
1262 Param<int> size;
1263
1264END_DECLARE_SIM_OBJECT_PARAMS(ITB)
1265
1266BEGIN_INIT_SIM_OBJECT_PARAMS(ITB)
1267
1268 INIT_PARAM_DFLT(size, "TLB size", 48)
1269
1270END_INIT_SIM_OBJECT_PARAMS(ITB)
1271
1272
1273CREATE_SIM_OBJECT(ITB)
1274{
1275 return new ITB(getInstanceName(), size);
1276}
1277
1278REGISTER_SIM_OBJECT("SparcITB", ITB)
1279
1280BEGIN_DECLARE_SIM_OBJECT_PARAMS(DTB)
1281
1282 Param<int> size;
1283
1284END_DECLARE_SIM_OBJECT_PARAMS(DTB)
1285
1286BEGIN_INIT_SIM_OBJECT_PARAMS(DTB)
1287
1288 INIT_PARAM_DFLT(size, "TLB size", 64)
1289
1290END_INIT_SIM_OBJECT_PARAMS(DTB)
1291
1292
1293CREATE_SIM_OBJECT(DTB)
1294{
1295 return new DTB(getInstanceName(), size);
1296}
1297
1298REGISTER_SIM_OBJECT("SparcDTB", DTB)
1299}
585 if (asi == ASI_IMPLICIT)
586 implicit = true;
587
588 if (hpriv && implicit) {
589 req->setPaddr(vaddr & PAddrImplMask);
590 return NoFault;
591 }
592
593 // Be fast if we can!
594 if (cacheValid && cacheState == tlbdata) {
595 if (cacheEntry[0] && cacheAsi[0] == asi && cacheEntry[0]->range.va < vaddr + size &&
596 cacheEntry[0]->range.va + cacheEntry[0]->range.size > vaddr &&
597 (!write || cacheEntry[0]->pte.writable())) {
598 req->setPaddr(cacheEntry[0]->pte.paddr() & ~(cacheEntry[0]->pte.size()-1) |
599 vaddr & cacheEntry[0]->pte.size()-1 );
600 return NoFault;
601 }
602 if (cacheEntry[1] && cacheAsi[1] == asi && cacheEntry[1]->range.va < vaddr + size &&
603 cacheEntry[1]->range.va + cacheEntry[1]->range.size > vaddr &&
604 (!write || cacheEntry[1]->pte.writable())) {
605 req->setPaddr(cacheEntry[1]->pte.paddr() & ~(cacheEntry[1]->pte.size()-1) |
606 vaddr & cacheEntry[1]->pte.size()-1 );
607 return NoFault;
608 }
609 }
610
611 bool red = bits(tlbdata,1,1);
612 bool priv = bits(tlbdata,2,2);
613 bool addr_mask = bits(tlbdata,3,3);
614 bool lsu_dm = bits(tlbdata,5,5);
615
616 int part_id = bits(tlbdata,15,8);
617 int tl = bits(tlbdata,18,16);
618 int pri_context = bits(tlbdata,47,32);
619 int sec_context = bits(tlbdata,63,48);
620
621 bool real = false;
622 ContextType ct = Primary;
623 int context = 0;
624
625 TlbEntry *e;
626
627 DPRINTF(TLB, "TLB: priv:%d hpriv:%d red:%d lsudm:%d part_id: %#X\n",
628 priv, hpriv, red, lsu_dm, part_id);
629
630 if (implicit) {
631 if (tl > 0) {
632 asi = ASI_N;
633 ct = Nucleus;
634 context = 0;
635 } else {
636 asi = ASI_P;
637 ct = Primary;
638 context = pri_context;
639 }
640 } else {
641 // We need to check for priv level/asi priv
642 if (!priv && !hpriv && !AsiIsUnPriv(asi)) {
643 // It appears that context should be Nucleus in these cases?
644 writeSfr(tc, vaddr, write, Nucleus, false, IllegalAsi, asi);
645 return new PrivilegedAction;
646 }
647
648 if (!hpriv && AsiIsHPriv(asi)) {
649 writeSfr(tc, vaddr, write, Nucleus, false, IllegalAsi, asi);
650 return new DataAccessException;
651 }
652
653 if (AsiIsPrimary(asi)) {
654 context = pri_context;
655 ct = Primary;
656 } else if (AsiIsSecondary(asi)) {
657 context = sec_context;
658 ct = Secondary;
659 } else if (AsiIsNucleus(asi)) {
660 ct = Nucleus;
661 context = 0;
662 } else { // ????
663 ct = Primary;
664 context = pri_context;
665 }
666 }
667
668 if (!implicit && asi != ASI_P && asi != ASI_S) {
669 if (AsiIsLittle(asi))
670 panic("Little Endian ASIs not supported\n");
671 if (AsiIsBlock(asi))
672 panic("Block ASIs not supported\n");
673 if (AsiIsNoFault(asi))
674 panic("No Fault ASIs not supported\n");
675
676 if (AsiIsPartialStore(asi))
677 panic("Partial Store ASIs not supported\n");
678 if (AsiIsInterrupt(asi))
679 panic("Interrupt ASIs not supported\n");
680
681 if (AsiIsMmu(asi))
682 goto handleMmuRegAccess;
683 if (AsiIsScratchPad(asi))
684 goto handleScratchRegAccess;
685 if (AsiIsQueue(asi))
686 goto handleQueueRegAccess;
687 if (AsiIsSparcError(asi))
688 goto handleSparcErrorRegAccess;
689
690 if (!AsiIsReal(asi) && !AsiIsNucleus(asi) && !AsiIsAsIfUser(asi) &&
691 !AsiIsTwin(asi))
692 panic("Accessing ASI %#X. Should we?\n", asi);
693 }
694
695 // If the asi is unaligned trap
696 if (vaddr & size-1) {
697 writeSfr(tc, vaddr, false, ct, false, OtherFault, asi);
698 return new MemAddressNotAligned;
699 }
700
701 if (addr_mask)
702 vaddr = vaddr & VAddrAMask;
703
704 if (!validVirtualAddress(vaddr, addr_mask)) {
705 writeSfr(tc, vaddr, false, ct, true, VaOutOfRange, asi);
706 return new DataAccessException;
707 }
708
709
710 if ((!lsu_dm && !hpriv && !red) || AsiIsReal(asi)) {
711 real = true;
712 context = 0;
713 };
714
715 if (hpriv && (implicit || (!AsiIsAsIfUser(asi) && !AsiIsReal(asi)))) {
716 req->setPaddr(vaddr & PAddrImplMask);
717 return NoFault;
718 }
719
720 e = lookup(vaddr, part_id, real, context);
721
722 if (e == NULL || !e->valid) {
723 writeTagAccess(tc, vaddr, context);
724 DPRINTF(TLB, "TLB: DTB Failed to find matching TLB entry\n");
725 if (real)
726 return new DataRealTranslationMiss;
727 else
728 return new FastDataAccessMMUMiss;
729
730 }
731
732 if (!priv && e->pte.priv()) {
733 writeTagAccess(tc, vaddr, context);
734 writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), PrivViolation, asi);
735 return new DataAccessException;
736 }
737
738 if (write && !e->pte.writable()) {
739 writeTagAccess(tc, vaddr, context);
740 writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), OtherFault, asi);
741 return new FastDataAccessProtection;
742 }
743
744 if (e->pte.nofault() && !AsiIsNoFault(asi)) {
745 writeTagAccess(tc, vaddr, context);
746 writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), LoadFromNfo, asi);
747 return new DataAccessException;
748 }
749
750 if (e->pte.sideffect() && AsiIsNoFault(asi)) {
751 writeTagAccess(tc, vaddr, context);
752 writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), SideEffect, asi);
753 return new DataAccessException;
754 }
755
756
757 if (e->pte.sideffect())
758 req->setFlags(req->getFlags() | UNCACHEABLE);
759
760 // cache translation date for next translation
761 cacheState = tlbdata;
762 if (!cacheValid) {
763 cacheEntry[1] = NULL;
764 cacheEntry[0] = NULL;
765 }
766
767 if (cacheEntry[0] != e && cacheEntry[1] != e) {
768 cacheEntry[1] = cacheEntry[0];
769 cacheEntry[0] = e;
770 cacheAsi[1] = cacheAsi[0];
771 cacheAsi[0] = asi;
772 if (implicit)
773 cacheAsi[0] = (ASI)0;
774 }
775 cacheValid = true;
776 req->setPaddr(e->pte.paddr() & ~(e->pte.size()-1) |
777 vaddr & e->pte.size()-1);
778 DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr());
779 return NoFault;
780 /** Normal flow ends here. */
781
782handleScratchRegAccess:
783 if (vaddr > 0x38 || (vaddr >= 0x20 && vaddr < 0x30 && !hpriv)) {
784 writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi);
785 return new DataAccessException;
786 }
787 goto regAccessOk;
788
789handleQueueRegAccess:
790 if (!priv && !hpriv) {
791 writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi);
792 return new PrivilegedAction;
793 }
794 if (!hpriv && vaddr & 0xF || vaddr > 0x3f8 || vaddr < 0x3c0) {
795 writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi);
796 return new DataAccessException;
797 }
798 goto regAccessOk;
799
800handleSparcErrorRegAccess:
801 if (!hpriv) {
802 if (priv) {
803 writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi);
804 return new DataAccessException;
805 } else {
806 writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi);
807 return new PrivilegedAction;
808 }
809 }
810 goto regAccessOk;
811
812
813regAccessOk:
814handleMmuRegAccess:
815 DPRINTF(TLB, "TLB: DTB Translating MM IPR access\n");
816 req->setMmapedIpr(true);
817 req->setPaddr(req->getVaddr());
818 return NoFault;
819};
820
821Tick
822DTB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
823{
824 Addr va = pkt->getAddr();
825 ASI asi = (ASI)pkt->req->getAsi();
826 uint64_t temp, data;
827 uint64_t tsbtemp, cnftemp;
828
829 DPRINTF(IPR, "Memory Mapped IPR Read: asi=%#X a=%#x\n",
830 (uint32_t)pkt->req->getAsi(), pkt->getAddr());
831
832 switch (asi) {
833 case ASI_LSU_CONTROL_REG:
834 assert(va == 0);
835 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_LSU_CTRL));
836 break;
837 case ASI_MMU:
838 switch (va) {
839 case 0x8:
840 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_P_CONTEXT));
841 break;
842 case 0x10:
843 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_S_CONTEXT));
844 break;
845 default:
846 goto doMmuReadError;
847 }
848 break;
849 case ASI_QUEUE:
850 pkt->set(tc->readMiscRegWithEffect(MISCREG_QUEUE_CPU_MONDO_HEAD +
851 (va >> 4) - 0x3c));
852 break;
853 case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0:
854 assert(va == 0);
855 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS0));
856 break;
857 case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1:
858 assert(va == 0);
859 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS1));
860 break;
861 case ASI_DMMU_CTXT_ZERO_CONFIG:
862 assert(va == 0);
863 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG));
864 break;
865 case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0:
866 assert(va == 0);
867 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS0));
868 break;
869 case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1:
870 assert(va == 0);
871 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS1));
872 break;
873 case ASI_IMMU_CTXT_ZERO_CONFIG:
874 assert(va == 0);
875 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG));
876 break;
877 case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0:
878 assert(va == 0);
879 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS0));
880 break;
881 case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1:
882 assert(va == 0);
883 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS1));
884 break;
885 case ASI_DMMU_CTXT_NONZERO_CONFIG:
886 assert(va == 0);
887 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG));
888 break;
889 case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0:
890 assert(va == 0);
891 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS0));
892 break;
893 case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1:
894 assert(va == 0);
895 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS1));
896 break;
897 case ASI_IMMU_CTXT_NONZERO_CONFIG:
898 assert(va == 0);
899 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG));
900 break;
901 case ASI_SPARC_ERROR_STATUS_REG:
902 warn("returning 0 for SPARC ERROR regsiter read\n");
903 pkt->set((uint64_t)0);
904 break;
905 case ASI_HYP_SCRATCHPAD:
906 case ASI_SCRATCHPAD:
907 pkt->set(tc->readMiscRegWithEffect(MISCREG_SCRATCHPAD_R0 + (va >> 3)));
908 break;
909 case ASI_IMMU:
910 switch (va) {
911 case 0x0:
912 temp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS);
913 pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48);
914 break;
915 case 0x18:
916 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_SFSR));
917 break;
918 case 0x30:
919 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS));
920 break;
921 default:
922 goto doMmuReadError;
923 }
924 break;
925 case ASI_DMMU:
926 switch (va) {
927 case 0x0:
928 temp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS);
929 pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48);
930 break;
931 case 0x18:
932 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_SFSR));
933 break;
934 case 0x20:
935 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_SFAR));
936 break;
937 case 0x30:
938 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS));
939 break;
940 case 0x80:
941 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID));
942 break;
943 default:
944 goto doMmuReadError;
945 }
946 break;
947 case ASI_DMMU_TSB_PS0_PTR_REG:
948 temp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS);
949 if (bits(temp,12,0) == 0) {
950 tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS0);
951 cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG);
952 } else {
953 tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS0);
954 cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG);
955 }
956 data = mbits(tsbtemp,63,13);
957 data |= temp >> (9 + bits(cnftemp,2,0) * 3) &
958 mbits((uint64_t)-1ll,12+bits(tsbtemp,3,0), 4);
959 pkt->set(data);
960 break;
961 case ASI_DMMU_TSB_PS1_PTR_REG:
962 temp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS);
963 if (bits(temp,12,0) == 0) {
964 tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS1);
965 cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG);
966 } else {
967 tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS1);
968 cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG);
969 }
970 data = mbits(tsbtemp,63,13);
971 if (bits(tsbtemp,12,12))
972 data |= ULL(1) << (13+bits(tsbtemp,3,0));
973 data |= temp >> (9 + bits(cnftemp,10,8) * 3) &
974 mbits((uint64_t)-1ll,12+bits(tsbtemp,3,0), 4);
975 pkt->set(data);
976 break;
977 case ASI_IMMU_TSB_PS0_PTR_REG:
978 temp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS);
979 if (bits(temp,12,0) == 0) {
980 tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS0);
981 cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG);
982 } else {
983 tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS0);
984 cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG);
985 }
986 data = mbits(tsbtemp,63,13);
987 data |= temp >> (9 + bits(cnftemp,2,0) * 3) &
988 mbits((uint64_t)-1ll,12+bits(tsbtemp,3,0), 4);
989 pkt->set(data);
990 break;
991 case ASI_IMMU_TSB_PS1_PTR_REG:
992 temp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS);
993 if (bits(temp,12,0) == 0) {
994 tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS1);
995 cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG);
996 } else {
997 tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS1);
998 cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG);
999 }
1000 data = mbits(tsbtemp,63,13);
1001 if (bits(tsbtemp,12,12))
1002 data |= ULL(1) << (13+bits(tsbtemp,3,0));
1003 data |= temp >> (9 + bits(cnftemp,10,8) * 3) &
1004 mbits((uint64_t)-1ll,12+bits(tsbtemp,3,0), 4);
1005 pkt->set(data);
1006 break;
1007
1008 default:
1009doMmuReadError:
1010 panic("need to impl DTB::doMmuRegRead() got asi=%#x, va=%#x\n",
1011 (uint32_t)asi, va);
1012 }
1013 pkt->result = Packet::Success;
1014 return tc->getCpuPtr()->cycles(1);
1015}
1016
1017Tick
1018DTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
1019{
1020 uint64_t data = gtoh(pkt->get<uint64_t>());
1021 Addr va = pkt->getAddr();
1022 ASI asi = (ASI)pkt->req->getAsi();
1023
1024 Addr ta_insert;
1025 Addr va_insert;
1026 Addr ct_insert;
1027 int part_insert;
1028 int entry_insert = -1;
1029 bool real_insert;
1030 bool ignore;
1031 int part_id;
1032 int ctx_id;
1033 PageTableEntry pte;
1034
1035 DPRINTF(IPR, "Memory Mapped IPR Write: asi=%#X a=%#x d=%#X\n",
1036 (uint32_t)asi, va, data);
1037
1038 switch (asi) {
1039 case ASI_LSU_CONTROL_REG:
1040 assert(va == 0);
1041 tc->setMiscRegWithEffect(MISCREG_MMU_LSU_CTRL, data);
1042 break;
1043 case ASI_MMU:
1044 switch (va) {
1045 case 0x8:
1046 tc->setMiscRegWithEffect(MISCREG_MMU_P_CONTEXT, data);
1047 break;
1048 case 0x10:
1049 tc->setMiscRegWithEffect(MISCREG_MMU_S_CONTEXT, data);
1050 break;
1051 default:
1052 goto doMmuWriteError;
1053 }
1054 break;
1055 case ASI_QUEUE:
1056 assert(mbits(data,13,6) == data);
1057 tc->setMiscRegWithEffect(MISCREG_QUEUE_CPU_MONDO_HEAD +
1058 (va >> 4) - 0x3c, data);
1059 break;
1060 case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0:
1061 assert(va == 0);
1062 tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS0, data);
1063 break;
1064 case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1:
1065 assert(va == 0);
1066 tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS1, data);
1067 break;
1068 case ASI_DMMU_CTXT_ZERO_CONFIG:
1069 assert(va == 0);
1070 tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG, data);
1071 break;
1072 case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0:
1073 assert(va == 0);
1074 tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS0, data);
1075 break;
1076 case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1:
1077 assert(va == 0);
1078 tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS1, data);
1079 break;
1080 case ASI_IMMU_CTXT_ZERO_CONFIG:
1081 assert(va == 0);
1082 tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG, data);
1083 break;
1084 case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0:
1085 assert(va == 0);
1086 tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS0, data);
1087 break;
1088 case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1:
1089 assert(va == 0);
1090 tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS1, data);
1091 break;
1092 case ASI_DMMU_CTXT_NONZERO_CONFIG:
1093 assert(va == 0);
1094 tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG, data);
1095 break;
1096 case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0:
1097 assert(va == 0);
1098 tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS0, data);
1099 break;
1100 case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1:
1101 assert(va == 0);
1102 tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS1, data);
1103 break;
1104 case ASI_IMMU_CTXT_NONZERO_CONFIG:
1105 assert(va == 0);
1106 tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG, data);
1107 break;
1108 case ASI_SPARC_ERROR_EN_REG:
1109 case ASI_SPARC_ERROR_STATUS_REG:
1110 warn("Ignoring write to SPARC ERROR regsiter\n");
1111 break;
1112 case ASI_HYP_SCRATCHPAD:
1113 case ASI_SCRATCHPAD:
1114 tc->setMiscRegWithEffect(MISCREG_SCRATCHPAD_R0 + (va >> 3), data);
1115 break;
1116 case ASI_IMMU:
1117 switch (va) {
1118 case 0x18:
1119 tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_SFSR, data);
1120 break;
1121 case 0x30:
1122 sext<59>(bits(data, 59,0));
1123 tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS, data);
1124 break;
1125 default:
1126 goto doMmuWriteError;
1127 }
1128 break;
1129 case ASI_ITLB_DATA_ACCESS_REG:
1130 entry_insert = bits(va, 8,3);
1131 case ASI_ITLB_DATA_IN_REG:
1132 assert(entry_insert != -1 || mbits(va,10,9) == va);
1133 ta_insert = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS);
1134 va_insert = mbits(ta_insert, 63,13);
1135 ct_insert = mbits(ta_insert, 12,0);
1136 part_insert = tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID);
1137 real_insert = bits(va, 9,9);
1138 pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v :
1139 PageTableEntry::sun4u);
1140 tc->getITBPtr()->insert(va_insert, part_insert, ct_insert, real_insert,
1141 pte, entry_insert);
1142 break;
1143 case ASI_DTLB_DATA_ACCESS_REG:
1144 entry_insert = bits(va, 8,3);
1145 case ASI_DTLB_DATA_IN_REG:
1146 assert(entry_insert != -1 || mbits(va,10,9) == va);
1147 ta_insert = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS);
1148 va_insert = mbits(ta_insert, 63,13);
1149 ct_insert = mbits(ta_insert, 12,0);
1150 part_insert = tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID);
1151 real_insert = bits(va, 9,9);
1152 pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v :
1153 PageTableEntry::sun4u);
1154 insert(va_insert, part_insert, ct_insert, real_insert, pte, entry_insert);
1155 break;
1156 case ASI_IMMU_DEMAP:
1157 ignore = false;
1158 ctx_id = -1;
1159 part_id = tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID);
1160 switch (bits(va,5,4)) {
1161 case 0:
1162 ctx_id = tc->readMiscRegWithEffect(MISCREG_MMU_P_CONTEXT);
1163 break;
1164 case 1:
1165 ignore = true;
1166 break;
1167 case 3:
1168 ctx_id = 0;
1169 break;
1170 default:
1171 ignore = true;
1172 }
1173
1174 switch(bits(va,7,6)) {
1175 case 0: // demap page
1176 if (!ignore)
1177 tc->getITBPtr()->demapPage(mbits(va,63,13), part_id,
1178 bits(va,9,9), ctx_id);
1179 break;
1180 case 1: //demap context
1181 if (!ignore)
1182 tc->getITBPtr()->demapContext(part_id, ctx_id);
1183 break;
1184 case 2:
1185 tc->getITBPtr()->demapAll(part_id);
1186 break;
1187 default:
1188 panic("Invalid type for IMMU demap\n");
1189 }
1190 break;
1191 case ASI_DMMU:
1192 switch (va) {
1193 case 0x18:
1194 tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_SFSR, data);
1195 break;
1196 case 0x30:
1197 sext<59>(bits(data, 59,0));
1198 tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS, data);
1199 break;
1200 case 0x80:
1201 tc->setMiscRegWithEffect(MISCREG_MMU_PART_ID, data);
1202 break;
1203 default:
1204 goto doMmuWriteError;
1205 }
1206 break;
1207 case ASI_DMMU_DEMAP:
1208 ignore = false;
1209 ctx_id = -1;
1210 part_id = tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID);
1211 switch (bits(va,5,4)) {
1212 case 0:
1213 ctx_id = tc->readMiscRegWithEffect(MISCREG_MMU_P_CONTEXT);
1214 break;
1215 case 1:
1216 ctx_id = tc->readMiscRegWithEffect(MISCREG_MMU_S_CONTEXT);
1217 break;
1218 case 3:
1219 ctx_id = 0;
1220 break;
1221 default:
1222 ignore = true;
1223 }
1224
1225 switch(bits(va,7,6)) {
1226 case 0: // demap page
1227 if (!ignore)
1228 demapPage(mbits(va,63,13), part_id, bits(va,9,9), ctx_id);
1229 break;
1230 case 1: //demap context
1231 if (!ignore)
1232 demapContext(part_id, ctx_id);
1233 break;
1234 case 2:
1235 demapAll(part_id);
1236 break;
1237 default:
1238 panic("Invalid type for IMMU demap\n");
1239 }
1240 break;
1241 default:
1242doMmuWriteError:
1243 panic("need to impl DTB::doMmuRegWrite() got asi=%#x, va=%#x d=%#x\n",
1244 (uint32_t)pkt->req->getAsi(), pkt->getAddr(), data);
1245 }
1246 pkt->result = Packet::Success;
1247 return tc->getCpuPtr()->cycles(1);
1248}
1249
1250void
1251TLB::serialize(std::ostream &os)
1252{
1253 panic("Need to implement serialize tlb for SPARC\n");
1254}
1255
1256void
1257TLB::unserialize(Checkpoint *cp, const std::string &section)
1258{
1259 panic("Need to implement unserialize tlb for SPARC\n");
1260}
1261
1262
1263DEFINE_SIM_OBJECT_CLASS_NAME("SparcTLB", TLB)
1264
1265BEGIN_DECLARE_SIM_OBJECT_PARAMS(ITB)
1266
1267 Param<int> size;
1268
1269END_DECLARE_SIM_OBJECT_PARAMS(ITB)
1270
1271BEGIN_INIT_SIM_OBJECT_PARAMS(ITB)
1272
1273 INIT_PARAM_DFLT(size, "TLB size", 48)
1274
1275END_INIT_SIM_OBJECT_PARAMS(ITB)
1276
1277
1278CREATE_SIM_OBJECT(ITB)
1279{
1280 return new ITB(getInstanceName(), size);
1281}
1282
1283REGISTER_SIM_OBJECT("SparcITB", ITB)
1284
1285BEGIN_DECLARE_SIM_OBJECT_PARAMS(DTB)
1286
1287 Param<int> size;
1288
1289END_DECLARE_SIM_OBJECT_PARAMS(DTB)
1290
1291BEGIN_INIT_SIM_OBJECT_PARAMS(DTB)
1292
1293 INIT_PARAM_DFLT(size, "TLB size", 64)
1294
1295END_INIT_SIM_OBJECT_PARAMS(DTB)
1296
1297
1298CREATE_SIM_OBJECT(DTB)
1299{
1300 return new DTB(getInstanceName(), size);
1301}
1302
1303REGISTER_SIM_OBJECT("SparcDTB", DTB)
1304}