1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Ali Saidi
29 */
30
31#include "arch/sparc/asi.hh"
32#include "arch/sparc/miscregfile.hh"
33#include "arch/sparc/tlb.hh"
34#include "base/bitfield.hh"
35#include "base/trace.hh"
36#include "cpu/thread_context.hh"
37#include "cpu/base.hh"
38#include "mem/packet_access.hh"
39#include "mem/request.hh"
40#include "sim/builder.hh"
41
42/* @todo remove some of the magic constants. -- ali
43 * */
44namespace SparcISA
45{
46
47TLB::TLB(const std::string &name, int s)
48 : SimObject(name), size(s), usedEntries(0), lastReplaced(0),
49 cacheValid(false)
50{
51 // To make this work you'll have to change the hypervisor and OS
52 if (size > 64)
53 fatal("SPARC T1 TLB registers don't support more than 64 TLB entries.");
54
55 tlb = new TlbEntry[size];
56 memset(tlb, 0, sizeof(TlbEntry) * size);
57
58 for (int x = 0; x < size; x++)
59 freeList.push_back(&tlb[x]);
60}
61
62void
63TLB::clearUsedBits()
64{
65 MapIter i;
66 for (i = lookupTable.begin(); i != lookupTable.end(); i++) {
67 TlbEntry *t = i->second;
68 if (!t->pte.locked()) {
69 t->used = false;
70 usedEntries--;
71 }
72 }
73}
74
75
76void
77TLB::insert(Addr va, int partition_id, int context_id, bool real,
78 const PageTableEntry& PTE, int entry)
79{
80
81
82 MapIter i;
83 TlbEntry *new_entry = NULL;
84// TlbRange tr;
85 int x;
86
87 cacheValid = false;
88 va &= ~(PTE.size()-1);
89 /* tr.va = va;
90 tr.size = PTE.size() - 1;
91 tr.contextId = context_id;
92 tr.partitionId = partition_id;
93 tr.real = real;
94*/
95
96 DPRINTF(TLB, "TLB: Inserting TLB Entry; va=%#x pa=%#x pid=%d cid=%d r=%d entryid=%d\n",
97 va, PTE.paddr(), partition_id, context_id, (int)real, entry);
98
99 // Demap any entry that conflicts
100 for (x = 0; x < size; x++) {
101 if (tlb[x].range.real == real &&
102 tlb[x].range.partitionId == partition_id &&
103 tlb[x].range.va < va + PTE.size() - 1 &&
104 tlb[x].range.va + tlb[x].range.size >= va &&
105 (real || tlb[x].range.contextId == context_id ))
106 {
107 if (tlb[x].valid) {
108 freeList.push_front(&tlb[x]);
109 DPRINTF(TLB, "TLB: Conflicting entry %#X , deleting it\n", x);
110
111 tlb[x].valid = false;
112 if (tlb[x].used) {
113 tlb[x].used = false;
114 usedEntries--;
115 }
116 lookupTable.erase(tlb[x].range);
117 }
118 }
119 }
120
121
122/*
123 i = lookupTable.find(tr);
124 if (i != lookupTable.end()) {
125 i->second->valid = false;
126 if (i->second->used) {
127 i->second->used = false;
128 usedEntries--;
129 }
130 freeList.push_front(i->second);
131 DPRINTF(TLB, "TLB: Found conflicting entry %#X , deleting it\n",
132 i->second);
133 lookupTable.erase(i);
134 }
135*/
136
137 if (entry != -1) {
138 assert(entry < size && entry >= 0);
139 new_entry = &tlb[entry];
140 } else {
141 if (!freeList.empty()) {
142 new_entry = freeList.front();
143 } else {
144 x = lastReplaced;
145 do {
146 ++x;
147 if (x == size)
148 x = 0;
149 if (x == lastReplaced)
150 goto insertAllLocked;
151 } while (tlb[x].pte.locked());
152 lastReplaced = x;
153 new_entry = &tlb[x];
154 }
155 /*
156 for (x = 0; x < size; x++) {
157 if (!tlb[x].valid || !tlb[x].used) {
158 new_entry = &tlb[x];
159 break;
160 }
161 }*/
162 }
163
164insertAllLocked:
165 // Update the last ently if their all locked
166 if (!new_entry) {
167 new_entry = &tlb[size-1];
168 }
169
170 freeList.remove(new_entry);
171 if (new_entry->valid && new_entry->used)
172 usedEntries--;
173
174 lookupTable.erase(new_entry->range);
175
176
177 DPRINTF(TLB, "Using entry: %#X\n", new_entry);
178
179 assert(PTE.valid());
180 new_entry->range.va = va;
181 new_entry->range.size = PTE.size() - 1;
182 new_entry->range.partitionId = partition_id;
183 new_entry->range.contextId = context_id;
184 new_entry->range.real = real;
185 new_entry->pte = PTE;
186 new_entry->used = true;;
187 new_entry->valid = true;
188 usedEntries++;
189
190
191
192 i = lookupTable.insert(new_entry->range, new_entry);
193 assert(i != lookupTable.end());
194
195 // If all entries have there used bit set, clear it on them all, but the
196 // one we just inserted
197 if (usedEntries == size) {
198 clearUsedBits();
199 new_entry->used = true;
200 usedEntries++;
201 }
202
203}
204
205
206TlbEntry*
207TLB::lookup(Addr va, int partition_id, bool real, int context_id)
208{
209 MapIter i;
210 TlbRange tr;
211 TlbEntry *t;
212
213 DPRINTF(TLB, "TLB: Looking up entry va=%#x pid=%d cid=%d r=%d\n",
214 va, partition_id, context_id, real);
215 // Assemble full address structure
216 tr.va = va;
217 tr.size = MachineBytes;
218 tr.contextId = context_id;
219 tr.partitionId = partition_id;
220 tr.real = real;
221
222 // Try to find the entry
223 i = lookupTable.find(tr);
224 if (i == lookupTable.end()) {
225 DPRINTF(TLB, "TLB: No valid entry found\n");
226 return NULL;
227 }
228
229 // Mark the entries used bit and clear other used bits in needed
230 t = i->second;
231 DPRINTF(TLB, "TLB: Valid entry found pa: %#x size: %#x\n", t->pte.paddr(),
232 t->pte.size());
233 if (!t->used) {
234 t->used = true;
235 usedEntries++;
236 if (usedEntries == size) {
237 clearUsedBits();
238 t->used = true;
239 usedEntries++;
240 }
241 }
242
243 return t;
244}
245
246void
247TLB::dumpAll()
248{
249 MapIter i;
250 for (int x = 0; x < size; x++) {
251 if (tlb[x].valid) {
252 DPRINTFN("%4d: %#2x:%#2x %c %#4x %#8x %#8x %#16x\n",
253 x, tlb[x].range.partitionId, tlb[x].range.contextId,
254 tlb[x].range.real ? 'R' : ' ', tlb[x].range.size,
255 tlb[x].range.va, tlb[x].pte.paddr(), tlb[x].pte());
256 }
257 }
258}
259
260void
261TLB::demapPage(Addr va, int partition_id, bool real, int context_id)
262{
263 TlbRange tr;
264 MapIter i;
265
266 DPRINTF(IPR, "TLB: Demapping Page va=%#x pid=%#d cid=%d r=%d\n",
267 va, partition_id, context_id, real);
268
269 cacheValid = false;
270
271 // Assemble full address structure
272 tr.va = va;
273 tr.size = MachineBytes;
274 tr.contextId = context_id;
275 tr.partitionId = partition_id;
276 tr.real = real;
277
278 // Demap any entry that conflicts
279 i = lookupTable.find(tr);
280 if (i != lookupTable.end()) {
281 DPRINTF(IPR, "TLB: Demapped page\n");
282 i->second->valid = false;
283 if (i->second->used) {
284 i->second->used = false;
285 usedEntries--;
286 }
287 freeList.push_front(i->second);
288 DPRINTF(TLB, "Freeing TLB entry : %#X\n", i->second);
289 lookupTable.erase(i);
290 }
291}
292
293void
294TLB::demapContext(int partition_id, int context_id)
295{
296 int x;
297 DPRINTF(IPR, "TLB: Demapping Context pid=%#d cid=%d\n",
298 partition_id, context_id);
299 cacheValid = false;
300 for (x = 0; x < size; x++) {
301 if (tlb[x].range.contextId == context_id &&
302 tlb[x].range.partitionId == partition_id) {
303 if (tlb[x].valid == true) {
304 freeList.push_front(&tlb[x]);
305 DPRINTF(TLB, "Freeing TLB entry : %#X\n", &tlb[x]);
306 }
307 tlb[x].valid = false;
308 if (tlb[x].used) {
309 tlb[x].used = false;
310 usedEntries--;
311 }
312 lookupTable.erase(tlb[x].range);
313 }
314 }
315}
316
317void
318TLB::demapAll(int partition_id)
319{
320 int x;
321 DPRINTF(TLB, "TLB: Demapping All pid=%#d\n", partition_id);
322 cacheValid = false;
323 for (x = 0; x < size; x++) {
324 if (!tlb[x].pte.locked() && tlb[x].range.partitionId == partition_id) {
325 if (tlb[x].valid == true){
326 freeList.push_front(&tlb[x]);
327 DPRINTF(TLB, "Freeing TLB entry : %#X\n", &tlb[x]);
328 }
329 tlb[x].valid = false;
330 if (tlb[x].used) {
331 tlb[x].used = false;
332 usedEntries--;
333 }
334 lookupTable.erase(tlb[x].range);
335 }
336 }
337}
338
339void
340TLB::invalidateAll()
341{
342 int x;
343 cacheValid = false;
344
345 freeList.clear();
346 lookupTable.clear();
347 for (x = 0; x < size; x++) {
348 if (tlb[x].valid == true)
349 freeList.push_back(&tlb[x]);
350 tlb[x].valid = false;
351 tlb[x].used = false;
352 }
353 usedEntries = 0;
354}
355
356uint64_t
357TLB::TteRead(int entry) {
358 if (entry >= size)
359 panic("entry: %d\n", entry);
360
361 assert(entry < size);
362 if (tlb[entry].valid)
363 return tlb[entry].pte();
364 else
365 return (uint64_t)-1ll;
366}
367
368uint64_t
369TLB::TagRead(int entry) {
370 assert(entry < size);
371 uint64_t tag;
372 if (!tlb[entry].valid)
373 return (uint64_t)-1ll;
374
375 tag = tlb[entry].range.contextId;
376 tag |= tlb[entry].range.va;
377 tag |= (uint64_t)tlb[entry].range.partitionId << 61;
378 tag |= tlb[entry].range.real ? ULL(1) << 60 : 0;
379 tag |= (uint64_t)~tlb[entry].pte._size() << 56;
380 return tag;
381}
382
383bool
384TLB::validVirtualAddress(Addr va, bool am)
385{
386 if (am)
387 return true;
388 if (va >= StartVAddrHole && va <= EndVAddrHole)
389 return false;
390 return true;
391}
392
393void
394TLB::writeSfsr(ThreadContext *tc, int reg, bool write, ContextType ct,
395 bool se, FaultTypes ft, int asi)
396{
397 uint64_t sfsr;
398 sfsr = tc->readMiscReg(reg);
399
400 if (sfsr & 0x1)
401 sfsr = 0x3;
402 else
403 sfsr = 1;
404
405 if (write)
406 sfsr |= 1 << 2;
407 sfsr |= ct << 4;
408 if (se)
409 sfsr |= 1 << 6;
410 sfsr |= ft << 7;
411 sfsr |= asi << 16;
412 tc->setMiscRegWithEffect(reg, sfsr);
413}
414
415void
416TLB::writeTagAccess(ThreadContext *tc, int reg, Addr va, int context)
417{
| 1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Ali Saidi
29 */
30
31#include "arch/sparc/asi.hh"
32#include "arch/sparc/miscregfile.hh"
33#include "arch/sparc/tlb.hh"
34#include "base/bitfield.hh"
35#include "base/trace.hh"
36#include "cpu/thread_context.hh"
37#include "cpu/base.hh"
38#include "mem/packet_access.hh"
39#include "mem/request.hh"
40#include "sim/builder.hh"
41
42/* @todo remove some of the magic constants. -- ali
43 * */
44namespace SparcISA
45{
46
47TLB::TLB(const std::string &name, int s)
48 : SimObject(name), size(s), usedEntries(0), lastReplaced(0),
49 cacheValid(false)
50{
51 // To make this work you'll have to change the hypervisor and OS
52 if (size > 64)
53 fatal("SPARC T1 TLB registers don't support more than 64 TLB entries.");
54
55 tlb = new TlbEntry[size];
56 memset(tlb, 0, sizeof(TlbEntry) * size);
57
58 for (int x = 0; x < size; x++)
59 freeList.push_back(&tlb[x]);
60}
61
62void
63TLB::clearUsedBits()
64{
65 MapIter i;
66 for (i = lookupTable.begin(); i != lookupTable.end(); i++) {
67 TlbEntry *t = i->second;
68 if (!t->pte.locked()) {
69 t->used = false;
70 usedEntries--;
71 }
72 }
73}
74
75
76void
77TLB::insert(Addr va, int partition_id, int context_id, bool real,
78 const PageTableEntry& PTE, int entry)
79{
80
81
82 MapIter i;
83 TlbEntry *new_entry = NULL;
84// TlbRange tr;
85 int x;
86
87 cacheValid = false;
88 va &= ~(PTE.size()-1);
89 /* tr.va = va;
90 tr.size = PTE.size() - 1;
91 tr.contextId = context_id;
92 tr.partitionId = partition_id;
93 tr.real = real;
94*/
95
96 DPRINTF(TLB, "TLB: Inserting TLB Entry; va=%#x pa=%#x pid=%d cid=%d r=%d entryid=%d\n",
97 va, PTE.paddr(), partition_id, context_id, (int)real, entry);
98
99 // Demap any entry that conflicts
100 for (x = 0; x < size; x++) {
101 if (tlb[x].range.real == real &&
102 tlb[x].range.partitionId == partition_id &&
103 tlb[x].range.va < va + PTE.size() - 1 &&
104 tlb[x].range.va + tlb[x].range.size >= va &&
105 (real || tlb[x].range.contextId == context_id ))
106 {
107 if (tlb[x].valid) {
108 freeList.push_front(&tlb[x]);
109 DPRINTF(TLB, "TLB: Conflicting entry %#X , deleting it\n", x);
110
111 tlb[x].valid = false;
112 if (tlb[x].used) {
113 tlb[x].used = false;
114 usedEntries--;
115 }
116 lookupTable.erase(tlb[x].range);
117 }
118 }
119 }
120
121
122/*
123 i = lookupTable.find(tr);
124 if (i != lookupTable.end()) {
125 i->second->valid = false;
126 if (i->second->used) {
127 i->second->used = false;
128 usedEntries--;
129 }
130 freeList.push_front(i->second);
131 DPRINTF(TLB, "TLB: Found conflicting entry %#X , deleting it\n",
132 i->second);
133 lookupTable.erase(i);
134 }
135*/
136
137 if (entry != -1) {
138 assert(entry < size && entry >= 0);
139 new_entry = &tlb[entry];
140 } else {
141 if (!freeList.empty()) {
142 new_entry = freeList.front();
143 } else {
144 x = lastReplaced;
145 do {
146 ++x;
147 if (x == size)
148 x = 0;
149 if (x == lastReplaced)
150 goto insertAllLocked;
151 } while (tlb[x].pte.locked());
152 lastReplaced = x;
153 new_entry = &tlb[x];
154 }
155 /*
156 for (x = 0; x < size; x++) {
157 if (!tlb[x].valid || !tlb[x].used) {
158 new_entry = &tlb[x];
159 break;
160 }
161 }*/
162 }
163
164insertAllLocked:
165 // Update the last ently if their all locked
166 if (!new_entry) {
167 new_entry = &tlb[size-1];
168 }
169
170 freeList.remove(new_entry);
171 if (new_entry->valid && new_entry->used)
172 usedEntries--;
173
174 lookupTable.erase(new_entry->range);
175
176
177 DPRINTF(TLB, "Using entry: %#X\n", new_entry);
178
179 assert(PTE.valid());
180 new_entry->range.va = va;
181 new_entry->range.size = PTE.size() - 1;
182 new_entry->range.partitionId = partition_id;
183 new_entry->range.contextId = context_id;
184 new_entry->range.real = real;
185 new_entry->pte = PTE;
186 new_entry->used = true;;
187 new_entry->valid = true;
188 usedEntries++;
189
190
191
192 i = lookupTable.insert(new_entry->range, new_entry);
193 assert(i != lookupTable.end());
194
195 // If all entries have there used bit set, clear it on them all, but the
196 // one we just inserted
197 if (usedEntries == size) {
198 clearUsedBits();
199 new_entry->used = true;
200 usedEntries++;
201 }
202
203}
204
205
206TlbEntry*
207TLB::lookup(Addr va, int partition_id, bool real, int context_id)
208{
209 MapIter i;
210 TlbRange tr;
211 TlbEntry *t;
212
213 DPRINTF(TLB, "TLB: Looking up entry va=%#x pid=%d cid=%d r=%d\n",
214 va, partition_id, context_id, real);
215 // Assemble full address structure
216 tr.va = va;
217 tr.size = MachineBytes;
218 tr.contextId = context_id;
219 tr.partitionId = partition_id;
220 tr.real = real;
221
222 // Try to find the entry
223 i = lookupTable.find(tr);
224 if (i == lookupTable.end()) {
225 DPRINTF(TLB, "TLB: No valid entry found\n");
226 return NULL;
227 }
228
229 // Mark the entries used bit and clear other used bits in needed
230 t = i->second;
231 DPRINTF(TLB, "TLB: Valid entry found pa: %#x size: %#x\n", t->pte.paddr(),
232 t->pte.size());
233 if (!t->used) {
234 t->used = true;
235 usedEntries++;
236 if (usedEntries == size) {
237 clearUsedBits();
238 t->used = true;
239 usedEntries++;
240 }
241 }
242
243 return t;
244}
245
246void
247TLB::dumpAll()
248{
249 MapIter i;
250 for (int x = 0; x < size; x++) {
251 if (tlb[x].valid) {
252 DPRINTFN("%4d: %#2x:%#2x %c %#4x %#8x %#8x %#16x\n",
253 x, tlb[x].range.partitionId, tlb[x].range.contextId,
254 tlb[x].range.real ? 'R' : ' ', tlb[x].range.size,
255 tlb[x].range.va, tlb[x].pte.paddr(), tlb[x].pte());
256 }
257 }
258}
259
260void
261TLB::demapPage(Addr va, int partition_id, bool real, int context_id)
262{
263 TlbRange tr;
264 MapIter i;
265
266 DPRINTF(IPR, "TLB: Demapping Page va=%#x pid=%#d cid=%d r=%d\n",
267 va, partition_id, context_id, real);
268
269 cacheValid = false;
270
271 // Assemble full address structure
272 tr.va = va;
273 tr.size = MachineBytes;
274 tr.contextId = context_id;
275 tr.partitionId = partition_id;
276 tr.real = real;
277
278 // Demap any entry that conflicts
279 i = lookupTable.find(tr);
280 if (i != lookupTable.end()) {
281 DPRINTF(IPR, "TLB: Demapped page\n");
282 i->second->valid = false;
283 if (i->second->used) {
284 i->second->used = false;
285 usedEntries--;
286 }
287 freeList.push_front(i->second);
288 DPRINTF(TLB, "Freeing TLB entry : %#X\n", i->second);
289 lookupTable.erase(i);
290 }
291}
292
293void
294TLB::demapContext(int partition_id, int context_id)
295{
296 int x;
297 DPRINTF(IPR, "TLB: Demapping Context pid=%#d cid=%d\n",
298 partition_id, context_id);
299 cacheValid = false;
300 for (x = 0; x < size; x++) {
301 if (tlb[x].range.contextId == context_id &&
302 tlb[x].range.partitionId == partition_id) {
303 if (tlb[x].valid == true) {
304 freeList.push_front(&tlb[x]);
305 DPRINTF(TLB, "Freeing TLB entry : %#X\n", &tlb[x]);
306 }
307 tlb[x].valid = false;
308 if (tlb[x].used) {
309 tlb[x].used = false;
310 usedEntries--;
311 }
312 lookupTable.erase(tlb[x].range);
313 }
314 }
315}
316
317void
318TLB::demapAll(int partition_id)
319{
320 int x;
321 DPRINTF(TLB, "TLB: Demapping All pid=%#d\n", partition_id);
322 cacheValid = false;
323 for (x = 0; x < size; x++) {
324 if (!tlb[x].pte.locked() && tlb[x].range.partitionId == partition_id) {
325 if (tlb[x].valid == true){
326 freeList.push_front(&tlb[x]);
327 DPRINTF(TLB, "Freeing TLB entry : %#X\n", &tlb[x]);
328 }
329 tlb[x].valid = false;
330 if (tlb[x].used) {
331 tlb[x].used = false;
332 usedEntries--;
333 }
334 lookupTable.erase(tlb[x].range);
335 }
336 }
337}
338
339void
340TLB::invalidateAll()
341{
342 int x;
343 cacheValid = false;
344
345 freeList.clear();
346 lookupTable.clear();
347 for (x = 0; x < size; x++) {
348 if (tlb[x].valid == true)
349 freeList.push_back(&tlb[x]);
350 tlb[x].valid = false;
351 tlb[x].used = false;
352 }
353 usedEntries = 0;
354}
355
356uint64_t
357TLB::TteRead(int entry) {
358 if (entry >= size)
359 panic("entry: %d\n", entry);
360
361 assert(entry < size);
362 if (tlb[entry].valid)
363 return tlb[entry].pte();
364 else
365 return (uint64_t)-1ll;
366}
367
368uint64_t
369TLB::TagRead(int entry) {
370 assert(entry < size);
371 uint64_t tag;
372 if (!tlb[entry].valid)
373 return (uint64_t)-1ll;
374
375 tag = tlb[entry].range.contextId;
376 tag |= tlb[entry].range.va;
377 tag |= (uint64_t)tlb[entry].range.partitionId << 61;
378 tag |= tlb[entry].range.real ? ULL(1) << 60 : 0;
379 tag |= (uint64_t)~tlb[entry].pte._size() << 56;
380 return tag;
381}
382
383bool
384TLB::validVirtualAddress(Addr va, bool am)
385{
386 if (am)
387 return true;
388 if (va >= StartVAddrHole && va <= EndVAddrHole)
389 return false;
390 return true;
391}
392
393void
394TLB::writeSfsr(ThreadContext *tc, int reg, bool write, ContextType ct,
395 bool se, FaultTypes ft, int asi)
396{
397 uint64_t sfsr;
398 sfsr = tc->readMiscReg(reg);
399
400 if (sfsr & 0x1)
401 sfsr = 0x3;
402 else
403 sfsr = 1;
404
405 if (write)
406 sfsr |= 1 << 2;
407 sfsr |= ct << 4;
408 if (se)
409 sfsr |= 1 << 6;
410 sfsr |= ft << 7;
411 sfsr |= asi << 16;
412 tc->setMiscRegWithEffect(reg, sfsr);
413}
414
415void
416TLB::writeTagAccess(ThreadContext *tc, int reg, Addr va, int context)
417{
|
| 418 DPRINTF(TLB, "TLB: Writing Tag Access: va: %#X ctx: %#X value: %#X\n",
419 va, context, mbits(va, 63,13) | mbits(context,12,0));
420
|
418 tc->setMiscRegWithEffect(reg, mbits(va, 63,13) | mbits(context,12,0));
419}
420
421void
422ITB::writeSfsr(ThreadContext *tc, bool write, ContextType ct,
423 bool se, FaultTypes ft, int asi)
424{
425 DPRINTF(TLB, "TLB: ITB Fault: w=%d ct=%d ft=%d asi=%d\n",
426 (int)write, ct, ft, asi);
427 TLB::writeSfsr(tc, MISCREG_MMU_ITLB_SFSR, write, ct, se, ft, asi);
428}
429
430void
431ITB::writeTagAccess(ThreadContext *tc, Addr va, int context)
432{
433 TLB::writeTagAccess(tc, MISCREG_MMU_ITLB_TAG_ACCESS, va, context);
434}
435
436void
437DTB::writeSfr(ThreadContext *tc, Addr a, bool write, ContextType ct,
438 bool se, FaultTypes ft, int asi)
439{
440 DPRINTF(TLB, "TLB: DTB Fault: A=%#x w=%d ct=%d ft=%d asi=%d\n",
441 a, (int)write, ct, ft, asi);
442 TLB::writeSfsr(tc, MISCREG_MMU_DTLB_SFSR, write, ct, se, ft, asi);
443 tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_SFAR, a);
444}
445
446void
447DTB::writeTagAccess(ThreadContext *tc, Addr va, int context)
448{
449 TLB::writeTagAccess(tc, MISCREG_MMU_DTLB_TAG_ACCESS, va, context);
450}
451
452
453
454Fault
455ITB::translate(RequestPtr &req, ThreadContext *tc)
456{
457 uint64_t tlbdata = tc->readMiscReg(MISCREG_TLB_DATA);
458
459 Addr vaddr = req->getVaddr();
460 TlbEntry *e;
461
462 assert(req->getAsi() == ASI_IMPLICIT);
463
464 DPRINTF(TLB, "TLB: ITB Request to translate va=%#x size=%d\n",
465 vaddr, req->getSize());
466
467 // Be fast if we can!
468 if (cacheValid && cacheState == tlbdata) {
469 if (cacheEntry) {
470 if (cacheEntry->range.va < vaddr + sizeof(MachInst) &&
471 cacheEntry->range.va + cacheEntry->range.size >= vaddr) {
472 req->setPaddr(cacheEntry->pte.paddr() & ~(cacheEntry->pte.size()-1) |
473 vaddr & cacheEntry->pte.size()-1 );
474 return NoFault;
475 }
476 } else {
477 req->setPaddr(vaddr & PAddrImplMask);
478 return NoFault;
479 }
480 }
481
482 bool hpriv = bits(tlbdata,0,0);
483 bool red = bits(tlbdata,1,1);
484 bool priv = bits(tlbdata,2,2);
485 bool addr_mask = bits(tlbdata,3,3);
486 bool lsu_im = bits(tlbdata,4,4);
487
488 int part_id = bits(tlbdata,15,8);
489 int tl = bits(tlbdata,18,16);
490 int pri_context = bits(tlbdata,47,32);
491 int context;
492 ContextType ct;
493 int asi;
494 bool real = false;
495
496 DPRINTF(TLB, "TLB: priv:%d hpriv:%d red:%d lsuim:%d part_id: %#X\n",
497 priv, hpriv, red, lsu_im, part_id);
498
499 if (tl > 0) {
500 asi = ASI_N;
501 ct = Nucleus;
502 context = 0;
503 } else {
504 asi = ASI_P;
505 ct = Primary;
506 context = pri_context;
507 }
508
509 if ( hpriv || red ) {
510 cacheValid = true;
511 cacheState = tlbdata;
512 cacheEntry = NULL;
513 req->setPaddr(vaddr & PAddrImplMask);
514 return NoFault;
515 }
516
517 // If the access is unaligned trap
518 if (vaddr & 0x3) {
519 writeSfsr(tc, false, ct, false, OtherFault, asi);
520 return new MemAddressNotAligned;
521 }
522
523 if (addr_mask)
524 vaddr = vaddr & VAddrAMask;
525
526 if (!validVirtualAddress(vaddr, addr_mask)) {
527 writeSfsr(tc, false, ct, false, VaOutOfRange, asi);
528 return new InstructionAccessException;
529 }
530
531 if (!lsu_im) {
532 e = lookup(vaddr, part_id, true);
533 real = true;
534 context = 0;
535 } else {
536 e = lookup(vaddr, part_id, false, context);
537 }
538
539 if (e == NULL || !e->valid) {
| 421 tc->setMiscRegWithEffect(reg, mbits(va, 63,13) | mbits(context,12,0));
422}
423
424void
425ITB::writeSfsr(ThreadContext *tc, bool write, ContextType ct,
426 bool se, FaultTypes ft, int asi)
427{
428 DPRINTF(TLB, "TLB: ITB Fault: w=%d ct=%d ft=%d asi=%d\n",
429 (int)write, ct, ft, asi);
430 TLB::writeSfsr(tc, MISCREG_MMU_ITLB_SFSR, write, ct, se, ft, asi);
431}
432
433void
434ITB::writeTagAccess(ThreadContext *tc, Addr va, int context)
435{
436 TLB::writeTagAccess(tc, MISCREG_MMU_ITLB_TAG_ACCESS, va, context);
437}
438
439void
440DTB::writeSfr(ThreadContext *tc, Addr a, bool write, ContextType ct,
441 bool se, FaultTypes ft, int asi)
442{
443 DPRINTF(TLB, "TLB: DTB Fault: A=%#x w=%d ct=%d ft=%d asi=%d\n",
444 a, (int)write, ct, ft, asi);
445 TLB::writeSfsr(tc, MISCREG_MMU_DTLB_SFSR, write, ct, se, ft, asi);
446 tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_SFAR, a);
447}
448
449void
450DTB::writeTagAccess(ThreadContext *tc, Addr va, int context)
451{
452 TLB::writeTagAccess(tc, MISCREG_MMU_DTLB_TAG_ACCESS, va, context);
453}
454
455
456
457Fault
458ITB::translate(RequestPtr &req, ThreadContext *tc)
459{
460 uint64_t tlbdata = tc->readMiscReg(MISCREG_TLB_DATA);
461
462 Addr vaddr = req->getVaddr();
463 TlbEntry *e;
464
465 assert(req->getAsi() == ASI_IMPLICIT);
466
467 DPRINTF(TLB, "TLB: ITB Request to translate va=%#x size=%d\n",
468 vaddr, req->getSize());
469
470 // Be fast if we can!
471 if (cacheValid && cacheState == tlbdata) {
472 if (cacheEntry) {
473 if (cacheEntry->range.va < vaddr + sizeof(MachInst) &&
474 cacheEntry->range.va + cacheEntry->range.size >= vaddr) {
475 req->setPaddr(cacheEntry->pte.paddr() & ~(cacheEntry->pte.size()-1) |
476 vaddr & cacheEntry->pte.size()-1 );
477 return NoFault;
478 }
479 } else {
480 req->setPaddr(vaddr & PAddrImplMask);
481 return NoFault;
482 }
483 }
484
485 bool hpriv = bits(tlbdata,0,0);
486 bool red = bits(tlbdata,1,1);
487 bool priv = bits(tlbdata,2,2);
488 bool addr_mask = bits(tlbdata,3,3);
489 bool lsu_im = bits(tlbdata,4,4);
490
491 int part_id = bits(tlbdata,15,8);
492 int tl = bits(tlbdata,18,16);
493 int pri_context = bits(tlbdata,47,32);
494 int context;
495 ContextType ct;
496 int asi;
497 bool real = false;
498
499 DPRINTF(TLB, "TLB: priv:%d hpriv:%d red:%d lsuim:%d part_id: %#X\n",
500 priv, hpriv, red, lsu_im, part_id);
501
502 if (tl > 0) {
503 asi = ASI_N;
504 ct = Nucleus;
505 context = 0;
506 } else {
507 asi = ASI_P;
508 ct = Primary;
509 context = pri_context;
510 }
511
512 if ( hpriv || red ) {
513 cacheValid = true;
514 cacheState = tlbdata;
515 cacheEntry = NULL;
516 req->setPaddr(vaddr & PAddrImplMask);
517 return NoFault;
518 }
519
520 // If the access is unaligned trap
521 if (vaddr & 0x3) {
522 writeSfsr(tc, false, ct, false, OtherFault, asi);
523 return new MemAddressNotAligned;
524 }
525
526 if (addr_mask)
527 vaddr = vaddr & VAddrAMask;
528
529 if (!validVirtualAddress(vaddr, addr_mask)) {
530 writeSfsr(tc, false, ct, false, VaOutOfRange, asi);
531 return new InstructionAccessException;
532 }
533
534 if (!lsu_im) {
535 e = lookup(vaddr, part_id, true);
536 real = true;
537 context = 0;
538 } else {
539 e = lookup(vaddr, part_id, false, context);
540 }
541
542 if (e == NULL || !e->valid) {
|
540 tc->setMiscReg(MISCREG_MMU_ITLB_TAG_ACCESS,
541 vaddr & ~BytesInPageMask | context);
| 543 writeTagAccess(tc, vaddr, context);
|
542 if (real)
543 return new InstructionRealTranslationMiss;
544 else
545 return new FastInstructionAccessMMUMiss;
546 }
547
548 // were not priviledged accesing priv page
549 if (!priv && e->pte.priv()) {
550 writeSfsr(tc, false, ct, false, PrivViolation, asi);
551 return new InstructionAccessException;
552 }
553
554 // cache translation date for next translation
555 cacheValid = true;
556 cacheState = tlbdata;
557 cacheEntry = e;
558
559 req->setPaddr(e->pte.paddr() & ~(e->pte.size()-1) |
560 vaddr & e->pte.size()-1 );
561 DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr());
562 return NoFault;
563}
564
565
566
567Fault
568DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
569{
570 /* @todo this could really use some profiling and fixing to make it faster! */
571 uint64_t tlbdata = tc->readMiscReg(MISCREG_TLB_DATA);
572 Addr vaddr = req->getVaddr();
573 Addr size = req->getSize();
574 ASI asi;
575 asi = (ASI)req->getAsi();
576 bool implicit = false;
577 bool hpriv = bits(tlbdata,0,0);
578
579 DPRINTF(TLB, "TLB: DTB Request to translate va=%#x size=%d asi=%#x\n",
580 vaddr, size, asi);
581
582 if (asi == ASI_IMPLICIT)
583 implicit = true;
584
585 if (hpriv && implicit) {
586 req->setPaddr(vaddr & PAddrImplMask);
587 return NoFault;
588 }
589
590 // Be fast if we can!
591 if (cacheValid && cacheState == tlbdata) {
592 if (cacheEntry[0] && cacheAsi[0] == asi && cacheEntry[0]->range.va < vaddr + size &&
593 cacheEntry[0]->range.va + cacheEntry[0]->range.size > vaddr) {
594 req->setPaddr(cacheEntry[0]->pte.paddr() & ~(cacheEntry[0]->pte.size()-1) |
595 vaddr & cacheEntry[0]->pte.size()-1 );
596 return NoFault;
597 }
598 if (cacheEntry[1] && cacheAsi[1] == asi && cacheEntry[1]->range.va < vaddr + size &&
599 cacheEntry[1]->range.va + cacheEntry[1]->range.size > vaddr) {
600 req->setPaddr(cacheEntry[1]->pte.paddr() & ~(cacheEntry[1]->pte.size()-1) |
601 vaddr & cacheEntry[1]->pte.size()-1 );
602 return NoFault;
603 }
604 }
605
606 bool red = bits(tlbdata,1,1);
607 bool priv = bits(tlbdata,2,2);
608 bool addr_mask = bits(tlbdata,3,3);
609 bool lsu_dm = bits(tlbdata,5,5);
610
611 int part_id = bits(tlbdata,15,8);
612 int tl = bits(tlbdata,18,16);
613 int pri_context = bits(tlbdata,47,32);
| 544 if (real)
545 return new InstructionRealTranslationMiss;
546 else
547 return new FastInstructionAccessMMUMiss;
548 }
549
550 // were not priviledged accesing priv page
551 if (!priv && e->pte.priv()) {
552 writeSfsr(tc, false, ct, false, PrivViolation, asi);
553 return new InstructionAccessException;
554 }
555
556 // cache translation date for next translation
557 cacheValid = true;
558 cacheState = tlbdata;
559 cacheEntry = e;
560
561 req->setPaddr(e->pte.paddr() & ~(e->pte.size()-1) |
562 vaddr & e->pte.size()-1 );
563 DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr());
564 return NoFault;
565}
566
567
568
569Fault
570DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
571{
572 /* @todo this could really use some profiling and fixing to make it faster! */
573 uint64_t tlbdata = tc->readMiscReg(MISCREG_TLB_DATA);
574 Addr vaddr = req->getVaddr();
575 Addr size = req->getSize();
576 ASI asi;
577 asi = (ASI)req->getAsi();
578 bool implicit = false;
579 bool hpriv = bits(tlbdata,0,0);
580
581 DPRINTF(TLB, "TLB: DTB Request to translate va=%#x size=%d asi=%#x\n",
582 vaddr, size, asi);
583
584 if (asi == ASI_IMPLICIT)
585 implicit = true;
586
587 if (hpriv && implicit) {
588 req->setPaddr(vaddr & PAddrImplMask);
589 return NoFault;
590 }
591
592 // Be fast if we can!
593 if (cacheValid && cacheState == tlbdata) {
594 if (cacheEntry[0] && cacheAsi[0] == asi && cacheEntry[0]->range.va < vaddr + size &&
595 cacheEntry[0]->range.va + cacheEntry[0]->range.size > vaddr) {
596 req->setPaddr(cacheEntry[0]->pte.paddr() & ~(cacheEntry[0]->pte.size()-1) |
597 vaddr & cacheEntry[0]->pte.size()-1 );
598 return NoFault;
599 }
600 if (cacheEntry[1] && cacheAsi[1] == asi && cacheEntry[1]->range.va < vaddr + size &&
601 cacheEntry[1]->range.va + cacheEntry[1]->range.size > vaddr) {
602 req->setPaddr(cacheEntry[1]->pte.paddr() & ~(cacheEntry[1]->pte.size()-1) |
603 vaddr & cacheEntry[1]->pte.size()-1 );
604 return NoFault;
605 }
606 }
607
608 bool red = bits(tlbdata,1,1);
609 bool priv = bits(tlbdata,2,2);
610 bool addr_mask = bits(tlbdata,3,3);
611 bool lsu_dm = bits(tlbdata,5,5);
612
613 int part_id = bits(tlbdata,15,8);
614 int tl = bits(tlbdata,18,16);
615 int pri_context = bits(tlbdata,47,32);
|
614 int sec_context = bits(tlbdata,47,32);
| 616 int sec_context = bits(tlbdata,63,48);
|
615
616 bool real = false;
617 ContextType ct = Primary;
618 int context = 0;
619
620 TlbEntry *e;
621
622 DPRINTF(TLB, "TLB: priv:%d hpriv:%d red:%d lsudm:%d part_id: %#X\n",
623 priv, hpriv, red, lsu_dm, part_id);
624
625 if (implicit) {
626 if (tl > 0) {
627 asi = ASI_N;
628 ct = Nucleus;
629 context = 0;
630 } else {
631 asi = ASI_P;
632 ct = Primary;
633 context = pri_context;
634 }
635 } else {
636 // We need to check for priv level/asi priv
637 if (!priv && !hpriv && !AsiIsUnPriv(asi)) {
638 // It appears that context should be Nucleus in these cases?
639 writeSfr(tc, vaddr, write, Nucleus, false, IllegalAsi, asi);
640 return new PrivilegedAction;
641 }
642
643 if (!hpriv && AsiIsHPriv(asi)) {
644 writeSfr(tc, vaddr, write, Nucleus, false, IllegalAsi, asi);
645 return new DataAccessException;
646 }
647
648 if (AsiIsPrimary(asi)) {
649 context = pri_context;
650 ct = Primary;
651 } else if (AsiIsSecondary(asi)) {
652 context = sec_context;
653 ct = Secondary;
654 } else if (AsiIsNucleus(asi)) {
655 ct = Nucleus;
656 context = 0;
657 } else { // ????
658 ct = Primary;
659 context = pri_context;
660 }
661 }
662
663 if (!implicit) {
664 if (AsiIsLittle(asi))
665 panic("Little Endian ASIs not supported\n");
666 if (AsiIsBlock(asi))
667 panic("Block ASIs not supported\n");
668 if (AsiIsNoFault(asi))
669 panic("No Fault ASIs not supported\n");
670
671 // These twin ASIs are OK
672 if (asi == ASI_P || asi == ASI_LDTX_P)
673 goto continueDtbFlow;
674 if (!write && (asi == ASI_QUAD_LDD || asi == ASI_LDTX_REAL))
675 goto continueDtbFlow;
676
677 if (AsiIsTwin(asi))
678 panic("Twin ASIs not supported\n");
679 if (AsiIsPartialStore(asi))
680 panic("Partial Store ASIs not supported\n");
681 if (AsiIsInterrupt(asi))
682 panic("Interrupt ASIs not supported\n");
683
684 if (AsiIsMmu(asi))
685 goto handleMmuRegAccess;
686 if (AsiIsScratchPad(asi))
687 goto handleScratchRegAccess;
688 if (AsiIsQueue(asi))
689 goto handleQueueRegAccess;
690 if (AsiIsSparcError(asi))
691 goto handleSparcErrorRegAccess;
692
693 if (!AsiIsReal(asi) && !AsiIsNucleus(asi) && !AsiIsAsIfUser(asi))
694 panic("Accessing ASI %#X. Should we?\n", asi);
695 }
696
697continueDtbFlow:
698 // If the asi is unaligned trap
699 if (vaddr & size-1) {
700 writeSfr(tc, vaddr, false, ct, false, OtherFault, asi);
701 return new MemAddressNotAligned;
702 }
703
704 if (addr_mask)
705 vaddr = vaddr & VAddrAMask;
706
707 if (!validVirtualAddress(vaddr, addr_mask)) {
708 writeSfr(tc, vaddr, false, ct, true, VaOutOfRange, asi);
709 return new DataAccessException;
710 }
711
712
713 if ((!lsu_dm && !hpriv && !red) || AsiIsReal(asi)) {
714 real = true;
715 context = 0;
716 };
717
718 if (hpriv && (implicit || (!AsiIsAsIfUser(asi) && !AsiIsReal(asi)))) {
719 req->setPaddr(vaddr & PAddrImplMask);
720 return NoFault;
721 }
722
723 e = lookup(vaddr, part_id, real, context);
724
725 if (e == NULL || !e->valid) {
| 617
618 bool real = false;
619 ContextType ct = Primary;
620 int context = 0;
621
622 TlbEntry *e;
623
624 DPRINTF(TLB, "TLB: priv:%d hpriv:%d red:%d lsudm:%d part_id: %#X\n",
625 priv, hpriv, red, lsu_dm, part_id);
626
627 if (implicit) {
628 if (tl > 0) {
629 asi = ASI_N;
630 ct = Nucleus;
631 context = 0;
632 } else {
633 asi = ASI_P;
634 ct = Primary;
635 context = pri_context;
636 }
637 } else {
638 // We need to check for priv level/asi priv
639 if (!priv && !hpriv && !AsiIsUnPriv(asi)) {
640 // It appears that context should be Nucleus in these cases?
641 writeSfr(tc, vaddr, write, Nucleus, false, IllegalAsi, asi);
642 return new PrivilegedAction;
643 }
644
645 if (!hpriv && AsiIsHPriv(asi)) {
646 writeSfr(tc, vaddr, write, Nucleus, false, IllegalAsi, asi);
647 return new DataAccessException;
648 }
649
650 if (AsiIsPrimary(asi)) {
651 context = pri_context;
652 ct = Primary;
653 } else if (AsiIsSecondary(asi)) {
654 context = sec_context;
655 ct = Secondary;
656 } else if (AsiIsNucleus(asi)) {
657 ct = Nucleus;
658 context = 0;
659 } else { // ????
660 ct = Primary;
661 context = pri_context;
662 }
663 }
664
665 if (!implicit) {
666 if (AsiIsLittle(asi))
667 panic("Little Endian ASIs not supported\n");
668 if (AsiIsBlock(asi))
669 panic("Block ASIs not supported\n");
670 if (AsiIsNoFault(asi))
671 panic("No Fault ASIs not supported\n");
672
673 // These twin ASIs are OK
674 if (asi == ASI_P || asi == ASI_LDTX_P)
675 goto continueDtbFlow;
676 if (!write && (asi == ASI_QUAD_LDD || asi == ASI_LDTX_REAL))
677 goto continueDtbFlow;
678
679 if (AsiIsTwin(asi))
680 panic("Twin ASIs not supported\n");
681 if (AsiIsPartialStore(asi))
682 panic("Partial Store ASIs not supported\n");
683 if (AsiIsInterrupt(asi))
684 panic("Interrupt ASIs not supported\n");
685
686 if (AsiIsMmu(asi))
687 goto handleMmuRegAccess;
688 if (AsiIsScratchPad(asi))
689 goto handleScratchRegAccess;
690 if (AsiIsQueue(asi))
691 goto handleQueueRegAccess;
692 if (AsiIsSparcError(asi))
693 goto handleSparcErrorRegAccess;
694
695 if (!AsiIsReal(asi) && !AsiIsNucleus(asi) && !AsiIsAsIfUser(asi))
696 panic("Accessing ASI %#X. Should we?\n", asi);
697 }
698
699continueDtbFlow:
700 // If the asi is unaligned trap
701 if (vaddr & size-1) {
702 writeSfr(tc, vaddr, false, ct, false, OtherFault, asi);
703 return new MemAddressNotAligned;
704 }
705
706 if (addr_mask)
707 vaddr = vaddr & VAddrAMask;
708
709 if (!validVirtualAddress(vaddr, addr_mask)) {
710 writeSfr(tc, vaddr, false, ct, true, VaOutOfRange, asi);
711 return new DataAccessException;
712 }
713
714
715 if ((!lsu_dm && !hpriv && !red) || AsiIsReal(asi)) {
716 real = true;
717 context = 0;
718 };
719
720 if (hpriv && (implicit || (!AsiIsAsIfUser(asi) && !AsiIsReal(asi)))) {
721 req->setPaddr(vaddr & PAddrImplMask);
722 return NoFault;
723 }
724
725 e = lookup(vaddr, part_id, real, context);
726
727 if (e == NULL || !e->valid) {
|
726 tc->setMiscReg(MISCREG_MMU_DTLB_TAG_ACCESS,
727 vaddr & ~BytesInPageMask | context);
| 728 writeTagAccess(tc, vaddr, context);
|
728 DPRINTF(TLB, "TLB: DTB Failed to find matching TLB entry\n");
729 if (real)
730 return new DataRealTranslationMiss;
731 else
732 return new FastDataAccessMMUMiss;
733
734 }
735
736
737 if (write && !e->pte.writable()) {
738 writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), OtherFault, asi);
739 return new FastDataAccessProtection;
740 }
741
742 if (e->pte.nofault() && !AsiIsNoFault(asi)) {
743 writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), LoadFromNfo, asi);
744 return new DataAccessException;
745 }
746
747 if (e->pte.sideffect())
748 req->setFlags(req->getFlags() | UNCACHEABLE);
749
750
751 if (!priv && e->pte.priv()) {
752 writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), PrivViolation, asi);
753 return new DataAccessException;
754 }
755
756 // cache translation date for next translation
757 cacheState = tlbdata;
758 if (!cacheValid) {
759 cacheEntry[1] = NULL;
760 cacheEntry[0] = NULL;
761 }
762
763 if (cacheEntry[0] != e && cacheEntry[1] != e) {
764 cacheEntry[1] = cacheEntry[0];
765 cacheEntry[0] = e;
766 cacheAsi[1] = cacheAsi[0];
767 cacheAsi[0] = asi;
768 if (implicit)
769 cacheAsi[0] = (ASI)0;
770 }
771 cacheValid = true;
772 req->setPaddr(e->pte.paddr() & ~(e->pte.size()-1) |
773 vaddr & e->pte.size()-1);
774 DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr());
775 return NoFault;
776 /** Normal flow ends here. */
777
778handleScratchRegAccess:
779 if (vaddr > 0x38 || (vaddr >= 0x20 && vaddr < 0x30 && !hpriv)) {
780 writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi);
781 return new DataAccessException;
782 }
783 goto regAccessOk;
784
785handleQueueRegAccess:
786 if (!priv && !hpriv) {
787 writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi);
788 return new PrivilegedAction;
789 }
790 if (!hpriv && vaddr & 0xF || vaddr > 0x3f8 || vaddr < 0x3c0) {
791 writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi);
792 return new DataAccessException;
793 }
794 goto regAccessOk;
795
796handleSparcErrorRegAccess:
797 if (!hpriv) {
798 if (priv) {
799 writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi);
800 return new DataAccessException;
801 } else {
802 writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi);
803 return new PrivilegedAction;
804 }
805 }
806 goto regAccessOk;
807
808
809regAccessOk:
810handleMmuRegAccess:
811 DPRINTF(TLB, "TLB: DTB Translating MM IPR access\n");
812 req->setMmapedIpr(true);
813 req->setPaddr(req->getVaddr());
814 return NoFault;
815};
816
817Tick
818DTB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
819{
820 Addr va = pkt->getAddr();
821 ASI asi = (ASI)pkt->req->getAsi();
822 uint64_t temp, data;
823 uint64_t tsbtemp, cnftemp;
824
825 DPRINTF(IPR, "Memory Mapped IPR Read: asi=%#X a=%#x\n",
826 (uint32_t)pkt->req->getAsi(), pkt->getAddr());
827
828 switch (asi) {
829 case ASI_LSU_CONTROL_REG:
830 assert(va == 0);
831 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_LSU_CTRL));
832 break;
833 case ASI_MMU:
834 switch (va) {
835 case 0x8:
836 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_P_CONTEXT));
837 break;
838 case 0x10:
839 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_S_CONTEXT));
840 break;
841 default:
842 goto doMmuReadError;
843 }
844 break;
845 case ASI_QUEUE:
846 pkt->set(tc->readMiscRegWithEffect(MISCREG_QUEUE_CPU_MONDO_HEAD +
847 (va >> 4) - 0x3c));
848 break;
849 case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0:
850 assert(va == 0);
851 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS0));
852 break;
853 case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1:
854 assert(va == 0);
855 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS1));
856 break;
857 case ASI_DMMU_CTXT_ZERO_CONFIG:
858 assert(va == 0);
859 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG));
860 break;
861 case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0:
862 assert(va == 0);
863 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS0));
864 break;
865 case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1:
866 assert(va == 0);
867 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS1));
868 break;
869 case ASI_IMMU_CTXT_ZERO_CONFIG:
870 assert(va == 0);
871 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG));
872 break;
873 case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0:
874 assert(va == 0);
875 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS0));
876 break;
877 case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1:
878 assert(va == 0);
879 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS1));
880 break;
881 case ASI_DMMU_CTXT_NONZERO_CONFIG:
882 assert(va == 0);
883 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG));
884 break;
885 case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0:
886 assert(va == 0);
887 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS0));
888 break;
889 case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1:
890 assert(va == 0);
891 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS1));
892 break;
893 case ASI_IMMU_CTXT_NONZERO_CONFIG:
894 assert(va == 0);
895 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG));
896 break;
897 case ASI_SPARC_ERROR_STATUS_REG:
898 warn("returning 0 for SPARC ERROR regsiter read\n");
899 pkt->set((uint64_t)0);
900 break;
901 case ASI_HYP_SCRATCHPAD:
902 case ASI_SCRATCHPAD:
903 pkt->set(tc->readMiscRegWithEffect(MISCREG_SCRATCHPAD_R0 + (va >> 3)));
904 break;
905 case ASI_IMMU:
906 switch (va) {
907 case 0x0:
908 temp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS);
909 pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48);
910 break;
911 case 0x18:
912 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_SFSR));
913 break;
914 case 0x30:
915 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS));
916 break;
917 default:
918 goto doMmuReadError;
919 }
920 break;
921 case ASI_DMMU:
922 switch (va) {
923 case 0x0:
924 temp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS);
925 pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48);
926 break;
927 case 0x18:
928 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_SFSR));
929 break;
930 case 0x20:
931 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_SFAR));
932 break;
933 case 0x30:
934 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS));
935 break;
936 case 0x80:
937 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID));
938 break;
939 default:
940 goto doMmuReadError;
941 }
942 break;
943 case ASI_DMMU_TSB_PS0_PTR_REG:
944 temp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS);
945 if (bits(temp,12,0) == 0) {
946 tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS0);
947 cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG);
948 } else {
949 tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS0);
950 cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG);
951 }
952 data = mbits(tsbtemp,63,13);
953 data |= temp >> (9 + bits(cnftemp,2,0) * 3) &
954 mbits((uint64_t)-1ll,12+bits(tsbtemp,3,0), 4);
955 pkt->set(data);
956 break;
957 case ASI_DMMU_TSB_PS1_PTR_REG:
958 temp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS);
959 if (bits(temp,12,0) == 0) {
960 tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS1);
961 cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG);
962 } else {
963 tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS1);
964 cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG);
965 }
966 data = mbits(tsbtemp,63,13);
967 if (bits(tsbtemp,12,12))
968 data |= ULL(1) << (13+bits(tsbtemp,3,0));
969 data |= temp >> (9 + bits(cnftemp,10,8) * 3) &
970 mbits((uint64_t)-1ll,12+bits(tsbtemp,3,0), 4);
971 pkt->set(data);
972 break;
973 case ASI_IMMU_TSB_PS0_PTR_REG:
974 temp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS);
975 if (bits(temp,12,0) == 0) {
976 tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS0);
977 cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG);
978 } else {
979 tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS0);
980 cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG);
981 }
982 data = mbits(tsbtemp,63,13);
983 data |= temp >> (9 + bits(cnftemp,2,0) * 3) &
984 mbits((uint64_t)-1ll,12+bits(tsbtemp,3,0), 4);
985 pkt->set(data);
986 break;
987 case ASI_IMMU_TSB_PS1_PTR_REG:
988 temp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS);
989 if (bits(temp,12,0) == 0) {
990 tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS1);
991 cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG);
992 } else {
993 tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS1);
994 cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG);
995 }
996 data = mbits(tsbtemp,63,13);
997 if (bits(tsbtemp,12,12))
998 data |= ULL(1) << (13+bits(tsbtemp,3,0));
999 data |= temp >> (9 + bits(cnftemp,10,8) * 3) &
1000 mbits((uint64_t)-1ll,12+bits(tsbtemp,3,0), 4);
1001 pkt->set(data);
1002 break;
1003
1004 default:
1005doMmuReadError:
1006 panic("need to impl DTB::doMmuRegRead() got asi=%#x, va=%#x\n",
1007 (uint32_t)asi, va);
1008 }
1009 pkt->result = Packet::Success;
1010 return tc->getCpuPtr()->cycles(1);
1011}
1012
1013Tick
1014DTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
1015{
1016 uint64_t data = gtoh(pkt->get<uint64_t>());
1017 Addr va = pkt->getAddr();
1018 ASI asi = (ASI)pkt->req->getAsi();
1019
1020 Addr ta_insert;
1021 Addr va_insert;
1022 Addr ct_insert;
1023 int part_insert;
1024 int entry_insert = -1;
1025 bool real_insert;
1026 bool ignore;
1027 int part_id;
1028 int ctx_id;
1029 PageTableEntry pte;
1030
1031 DPRINTF(IPR, "Memory Mapped IPR Write: asi=%#X a=%#x d=%#X\n",
1032 (uint32_t)asi, va, data);
1033
1034 switch (asi) {
1035 case ASI_LSU_CONTROL_REG:
1036 assert(va == 0);
1037 tc->setMiscRegWithEffect(MISCREG_MMU_LSU_CTRL, data);
1038 break;
1039 case ASI_MMU:
1040 switch (va) {
1041 case 0x8:
1042 tc->setMiscRegWithEffect(MISCREG_MMU_P_CONTEXT, data);
1043 break;
1044 case 0x10:
1045 tc->setMiscRegWithEffect(MISCREG_MMU_S_CONTEXT, data);
1046 break;
1047 default:
1048 goto doMmuWriteError;
1049 }
1050 break;
1051 case ASI_QUEUE:
1052 assert(mbits(data,13,6) == data);
1053 tc->setMiscRegWithEffect(MISCREG_QUEUE_CPU_MONDO_HEAD +
1054 (va >> 4) - 0x3c, data);
1055 break;
1056 case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0:
1057 assert(va == 0);
1058 tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS0, data);
1059 break;
1060 case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1:
1061 assert(va == 0);
1062 tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS1, data);
1063 break;
1064 case ASI_DMMU_CTXT_ZERO_CONFIG:
1065 assert(va == 0);
1066 tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG, data);
1067 break;
1068 case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0:
1069 assert(va == 0);
1070 tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS0, data);
1071 break;
1072 case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1:
1073 assert(va == 0);
1074 tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS1, data);
1075 break;
1076 case ASI_IMMU_CTXT_ZERO_CONFIG:
1077 assert(va == 0);
1078 tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG, data);
1079 break;
1080 case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0:
1081 assert(va == 0);
1082 tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS0, data);
1083 break;
1084 case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1:
1085 assert(va == 0);
1086 tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS1, data);
1087 break;
1088 case ASI_DMMU_CTXT_NONZERO_CONFIG:
1089 assert(va == 0);
1090 tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG, data);
1091 break;
1092 case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0:
1093 assert(va == 0);
1094 tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS0, data);
1095 break;
1096 case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1:
1097 assert(va == 0);
1098 tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS1, data);
1099 break;
1100 case ASI_IMMU_CTXT_NONZERO_CONFIG:
1101 assert(va == 0);
1102 tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG, data);
1103 break;
1104 case ASI_SPARC_ERROR_EN_REG:
1105 case ASI_SPARC_ERROR_STATUS_REG:
1106 warn("Ignoring write to SPARC ERROR regsiter\n");
1107 break;
1108 case ASI_HYP_SCRATCHPAD:
1109 case ASI_SCRATCHPAD:
1110 tc->setMiscRegWithEffect(MISCREG_SCRATCHPAD_R0 + (va >> 3), data);
1111 break;
1112 case ASI_IMMU:
1113 switch (va) {
1114 case 0x18:
1115 tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_SFSR, data);
1116 break;
1117 case 0x30:
| 729 DPRINTF(TLB, "TLB: DTB Failed to find matching TLB entry\n");
730 if (real)
731 return new DataRealTranslationMiss;
732 else
733 return new FastDataAccessMMUMiss;
734
735 }
736
737
738 if (write && !e->pte.writable()) {
739 writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), OtherFault, asi);
740 return new FastDataAccessProtection;
741 }
742
743 if (e->pte.nofault() && !AsiIsNoFault(asi)) {
744 writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), LoadFromNfo, asi);
745 return new DataAccessException;
746 }
747
748 if (e->pte.sideffect())
749 req->setFlags(req->getFlags() | UNCACHEABLE);
750
751
752 if (!priv && e->pte.priv()) {
753 writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), PrivViolation, asi);
754 return new DataAccessException;
755 }
756
757 // cache translation date for next translation
758 cacheState = tlbdata;
759 if (!cacheValid) {
760 cacheEntry[1] = NULL;
761 cacheEntry[0] = NULL;
762 }
763
764 if (cacheEntry[0] != e && cacheEntry[1] != e) {
765 cacheEntry[1] = cacheEntry[0];
766 cacheEntry[0] = e;
767 cacheAsi[1] = cacheAsi[0];
768 cacheAsi[0] = asi;
769 if (implicit)
770 cacheAsi[0] = (ASI)0;
771 }
772 cacheValid = true;
773 req->setPaddr(e->pte.paddr() & ~(e->pte.size()-1) |
774 vaddr & e->pte.size()-1);
775 DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr());
776 return NoFault;
777 /** Normal flow ends here. */
778
779handleScratchRegAccess:
780 if (vaddr > 0x38 || (vaddr >= 0x20 && vaddr < 0x30 && !hpriv)) {
781 writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi);
782 return new DataAccessException;
783 }
784 goto regAccessOk;
785
786handleQueueRegAccess:
787 if (!priv && !hpriv) {
788 writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi);
789 return new PrivilegedAction;
790 }
791 if (!hpriv && vaddr & 0xF || vaddr > 0x3f8 || vaddr < 0x3c0) {
792 writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi);
793 return new DataAccessException;
794 }
795 goto regAccessOk;
796
797handleSparcErrorRegAccess:
798 if (!hpriv) {
799 if (priv) {
800 writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi);
801 return new DataAccessException;
802 } else {
803 writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi);
804 return new PrivilegedAction;
805 }
806 }
807 goto regAccessOk;
808
809
810regAccessOk:
811handleMmuRegAccess:
812 DPRINTF(TLB, "TLB: DTB Translating MM IPR access\n");
813 req->setMmapedIpr(true);
814 req->setPaddr(req->getVaddr());
815 return NoFault;
816};
817
818Tick
819DTB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
820{
821 Addr va = pkt->getAddr();
822 ASI asi = (ASI)pkt->req->getAsi();
823 uint64_t temp, data;
824 uint64_t tsbtemp, cnftemp;
825
826 DPRINTF(IPR, "Memory Mapped IPR Read: asi=%#X a=%#x\n",
827 (uint32_t)pkt->req->getAsi(), pkt->getAddr());
828
829 switch (asi) {
830 case ASI_LSU_CONTROL_REG:
831 assert(va == 0);
832 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_LSU_CTRL));
833 break;
834 case ASI_MMU:
835 switch (va) {
836 case 0x8:
837 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_P_CONTEXT));
838 break;
839 case 0x10:
840 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_S_CONTEXT));
841 break;
842 default:
843 goto doMmuReadError;
844 }
845 break;
846 case ASI_QUEUE:
847 pkt->set(tc->readMiscRegWithEffect(MISCREG_QUEUE_CPU_MONDO_HEAD +
848 (va >> 4) - 0x3c));
849 break;
850 case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0:
851 assert(va == 0);
852 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS0));
853 break;
854 case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1:
855 assert(va == 0);
856 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS1));
857 break;
858 case ASI_DMMU_CTXT_ZERO_CONFIG:
859 assert(va == 0);
860 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG));
861 break;
862 case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0:
863 assert(va == 0);
864 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS0));
865 break;
866 case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1:
867 assert(va == 0);
868 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS1));
869 break;
870 case ASI_IMMU_CTXT_ZERO_CONFIG:
871 assert(va == 0);
872 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG));
873 break;
874 case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0:
875 assert(va == 0);
876 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS0));
877 break;
878 case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1:
879 assert(va == 0);
880 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS1));
881 break;
882 case ASI_DMMU_CTXT_NONZERO_CONFIG:
883 assert(va == 0);
884 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG));
885 break;
886 case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0:
887 assert(va == 0);
888 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS0));
889 break;
890 case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1:
891 assert(va == 0);
892 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS1));
893 break;
894 case ASI_IMMU_CTXT_NONZERO_CONFIG:
895 assert(va == 0);
896 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG));
897 break;
898 case ASI_SPARC_ERROR_STATUS_REG:
899 warn("returning 0 for SPARC ERROR regsiter read\n");
900 pkt->set((uint64_t)0);
901 break;
902 case ASI_HYP_SCRATCHPAD:
903 case ASI_SCRATCHPAD:
904 pkt->set(tc->readMiscRegWithEffect(MISCREG_SCRATCHPAD_R0 + (va >> 3)));
905 break;
906 case ASI_IMMU:
907 switch (va) {
908 case 0x0:
909 temp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS);
910 pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48);
911 break;
912 case 0x18:
913 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_SFSR));
914 break;
915 case 0x30:
916 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS));
917 break;
918 default:
919 goto doMmuReadError;
920 }
921 break;
922 case ASI_DMMU:
923 switch (va) {
924 case 0x0:
925 temp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS);
926 pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48);
927 break;
928 case 0x18:
929 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_SFSR));
930 break;
931 case 0x20:
932 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_SFAR));
933 break;
934 case 0x30:
935 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS));
936 break;
937 case 0x80:
938 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID));
939 break;
940 default:
941 goto doMmuReadError;
942 }
943 break;
944 case ASI_DMMU_TSB_PS0_PTR_REG:
945 temp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS);
946 if (bits(temp,12,0) == 0) {
947 tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS0);
948 cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG);
949 } else {
950 tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS0);
951 cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG);
952 }
953 data = mbits(tsbtemp,63,13);
954 data |= temp >> (9 + bits(cnftemp,2,0) * 3) &
955 mbits((uint64_t)-1ll,12+bits(tsbtemp,3,0), 4);
956 pkt->set(data);
957 break;
958 case ASI_DMMU_TSB_PS1_PTR_REG:
959 temp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS);
960 if (bits(temp,12,0) == 0) {
961 tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS1);
962 cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG);
963 } else {
964 tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS1);
965 cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG);
966 }
967 data = mbits(tsbtemp,63,13);
968 if (bits(tsbtemp,12,12))
969 data |= ULL(1) << (13+bits(tsbtemp,3,0));
970 data |= temp >> (9 + bits(cnftemp,10,8) * 3) &
971 mbits((uint64_t)-1ll,12+bits(tsbtemp,3,0), 4);
972 pkt->set(data);
973 break;
974 case ASI_IMMU_TSB_PS0_PTR_REG:
975 temp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS);
976 if (bits(temp,12,0) == 0) {
977 tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS0);
978 cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG);
979 } else {
980 tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS0);
981 cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG);
982 }
983 data = mbits(tsbtemp,63,13);
984 data |= temp >> (9 + bits(cnftemp,2,0) * 3) &
985 mbits((uint64_t)-1ll,12+bits(tsbtemp,3,0), 4);
986 pkt->set(data);
987 break;
988 case ASI_IMMU_TSB_PS1_PTR_REG:
989 temp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS);
990 if (bits(temp,12,0) == 0) {
991 tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS1);
992 cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG);
993 } else {
994 tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS1);
995 cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG);
996 }
997 data = mbits(tsbtemp,63,13);
998 if (bits(tsbtemp,12,12))
999 data |= ULL(1) << (13+bits(tsbtemp,3,0));
1000 data |= temp >> (9 + bits(cnftemp,10,8) * 3) &
1001 mbits((uint64_t)-1ll,12+bits(tsbtemp,3,0), 4);
1002 pkt->set(data);
1003 break;
1004
1005 default:
1006doMmuReadError:
1007 panic("need to impl DTB::doMmuRegRead() got asi=%#x, va=%#x\n",
1008 (uint32_t)asi, va);
1009 }
1010 pkt->result = Packet::Success;
1011 return tc->getCpuPtr()->cycles(1);
1012}
1013
1014Tick
1015DTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
1016{
1017 uint64_t data = gtoh(pkt->get<uint64_t>());
1018 Addr va = pkt->getAddr();
1019 ASI asi = (ASI)pkt->req->getAsi();
1020
1021 Addr ta_insert;
1022 Addr va_insert;
1023 Addr ct_insert;
1024 int part_insert;
1025 int entry_insert = -1;
1026 bool real_insert;
1027 bool ignore;
1028 int part_id;
1029 int ctx_id;
1030 PageTableEntry pte;
1031
1032 DPRINTF(IPR, "Memory Mapped IPR Write: asi=%#X a=%#x d=%#X\n",
1033 (uint32_t)asi, va, data);
1034
1035 switch (asi) {
1036 case ASI_LSU_CONTROL_REG:
1037 assert(va == 0);
1038 tc->setMiscRegWithEffect(MISCREG_MMU_LSU_CTRL, data);
1039 break;
1040 case ASI_MMU:
1041 switch (va) {
1042 case 0x8:
1043 tc->setMiscRegWithEffect(MISCREG_MMU_P_CONTEXT, data);
1044 break;
1045 case 0x10:
1046 tc->setMiscRegWithEffect(MISCREG_MMU_S_CONTEXT, data);
1047 break;
1048 default:
1049 goto doMmuWriteError;
1050 }
1051 break;
1052 case ASI_QUEUE:
1053 assert(mbits(data,13,6) == data);
1054 tc->setMiscRegWithEffect(MISCREG_QUEUE_CPU_MONDO_HEAD +
1055 (va >> 4) - 0x3c, data);
1056 break;
1057 case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0:
1058 assert(va == 0);
1059 tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS0, data);
1060 break;
1061 case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1:
1062 assert(va == 0);
1063 tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS1, data);
1064 break;
1065 case ASI_DMMU_CTXT_ZERO_CONFIG:
1066 assert(va == 0);
1067 tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG, data);
1068 break;
1069 case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0:
1070 assert(va == 0);
1071 tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS0, data);
1072 break;
1073 case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1:
1074 assert(va == 0);
1075 tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS1, data);
1076 break;
1077 case ASI_IMMU_CTXT_ZERO_CONFIG:
1078 assert(va == 0);
1079 tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG, data);
1080 break;
1081 case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0:
1082 assert(va == 0);
1083 tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS0, data);
1084 break;
1085 case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1:
1086 assert(va == 0);
1087 tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS1, data);
1088 break;
1089 case ASI_DMMU_CTXT_NONZERO_CONFIG:
1090 assert(va == 0);
1091 tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG, data);
1092 break;
1093 case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0:
1094 assert(va == 0);
1095 tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS0, data);
1096 break;
1097 case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1:
1098 assert(va == 0);
1099 tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS1, data);
1100 break;
1101 case ASI_IMMU_CTXT_NONZERO_CONFIG:
1102 assert(va == 0);
1103 tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG, data);
1104 break;
1105 case ASI_SPARC_ERROR_EN_REG:
1106 case ASI_SPARC_ERROR_STATUS_REG:
1107 warn("Ignoring write to SPARC ERROR regsiter\n");
1108 break;
1109 case ASI_HYP_SCRATCHPAD:
1110 case ASI_SCRATCHPAD:
1111 tc->setMiscRegWithEffect(MISCREG_SCRATCHPAD_R0 + (va >> 3), data);
1112 break;
1113 case ASI_IMMU:
1114 switch (va) {
1115 case 0x18:
1116 tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_SFSR, data);
1117 break;
1118 case 0x30:
|
| 1119 sext<59>(bits(data, 59,0));
|
1118 tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS, data);
1119 break;
1120 default:
1121 goto doMmuWriteError;
1122 }
1123 break;
1124 case ASI_ITLB_DATA_ACCESS_REG:
1125 entry_insert = bits(va, 8,3);
1126 case ASI_ITLB_DATA_IN_REG:
1127 assert(entry_insert != -1 || mbits(va,10,9) == va);
1128 ta_insert = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS);
1129 va_insert = mbits(ta_insert, 63,13);
1130 ct_insert = mbits(ta_insert, 12,0);
1131 part_insert = tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID);
1132 real_insert = bits(va, 9,9);
1133 pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v :
1134 PageTableEntry::sun4u);
1135 tc->getITBPtr()->insert(va_insert, part_insert, ct_insert, real_insert,
1136 pte, entry_insert);
1137 break;
1138 case ASI_DTLB_DATA_ACCESS_REG:
1139 entry_insert = bits(va, 8,3);
1140 case ASI_DTLB_DATA_IN_REG:
1141 assert(entry_insert != -1 || mbits(va,10,9) == va);
1142 ta_insert = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS);
1143 va_insert = mbits(ta_insert, 63,13);
1144 ct_insert = mbits(ta_insert, 12,0);
1145 part_insert = tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID);
1146 real_insert = bits(va, 9,9);
1147 pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v :
1148 PageTableEntry::sun4u);
1149 insert(va_insert, part_insert, ct_insert, real_insert, pte, entry_insert);
1150 break;
1151 case ASI_IMMU_DEMAP:
1152 ignore = false;
1153 ctx_id = -1;
1154 part_id = tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID);
1155 switch (bits(va,5,4)) {
1156 case 0:
1157 ctx_id = tc->readMiscRegWithEffect(MISCREG_MMU_P_CONTEXT);
1158 break;
1159 case 1:
1160 ignore = true;
1161 break;
1162 case 3:
1163 ctx_id = 0;
1164 break;
1165 default:
1166 ignore = true;
1167 }
1168
1169 switch(bits(va,7,6)) {
1170 case 0: // demap page
1171 if (!ignore)
1172 tc->getITBPtr()->demapPage(mbits(va,63,13), part_id,
1173 bits(va,9,9), ctx_id);
1174 break;
1175 case 1: //demap context
1176 if (!ignore)
1177 tc->getITBPtr()->demapContext(part_id, ctx_id);
1178 break;
1179 case 2:
1180 tc->getITBPtr()->demapAll(part_id);
1181 break;
1182 default:
1183 panic("Invalid type for IMMU demap\n");
1184 }
1185 break;
1186 case ASI_DMMU:
1187 switch (va) {
1188 case 0x18:
1189 tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_SFSR, data);
1190 break;
1191 case 0x30:
| 1120 tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS, data);
1121 break;
1122 default:
1123 goto doMmuWriteError;
1124 }
1125 break;
1126 case ASI_ITLB_DATA_ACCESS_REG:
1127 entry_insert = bits(va, 8,3);
1128 case ASI_ITLB_DATA_IN_REG:
1129 assert(entry_insert != -1 || mbits(va,10,9) == va);
1130 ta_insert = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS);
1131 va_insert = mbits(ta_insert, 63,13);
1132 ct_insert = mbits(ta_insert, 12,0);
1133 part_insert = tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID);
1134 real_insert = bits(va, 9,9);
1135 pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v :
1136 PageTableEntry::sun4u);
1137 tc->getITBPtr()->insert(va_insert, part_insert, ct_insert, real_insert,
1138 pte, entry_insert);
1139 break;
1140 case ASI_DTLB_DATA_ACCESS_REG:
1141 entry_insert = bits(va, 8,3);
1142 case ASI_DTLB_DATA_IN_REG:
1143 assert(entry_insert != -1 || mbits(va,10,9) == va);
1144 ta_insert = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS);
1145 va_insert = mbits(ta_insert, 63,13);
1146 ct_insert = mbits(ta_insert, 12,0);
1147 part_insert = tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID);
1148 real_insert = bits(va, 9,9);
1149 pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v :
1150 PageTableEntry::sun4u);
1151 insert(va_insert, part_insert, ct_insert, real_insert, pte, entry_insert);
1152 break;
1153 case ASI_IMMU_DEMAP:
1154 ignore = false;
1155 ctx_id = -1;
1156 part_id = tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID);
1157 switch (bits(va,5,4)) {
1158 case 0:
1159 ctx_id = tc->readMiscRegWithEffect(MISCREG_MMU_P_CONTEXT);
1160 break;
1161 case 1:
1162 ignore = true;
1163 break;
1164 case 3:
1165 ctx_id = 0;
1166 break;
1167 default:
1168 ignore = true;
1169 }
1170
1171 switch(bits(va,7,6)) {
1172 case 0: // demap page
1173 if (!ignore)
1174 tc->getITBPtr()->demapPage(mbits(va,63,13), part_id,
1175 bits(va,9,9), ctx_id);
1176 break;
1177 case 1: //demap context
1178 if (!ignore)
1179 tc->getITBPtr()->demapContext(part_id, ctx_id);
1180 break;
1181 case 2:
1182 tc->getITBPtr()->demapAll(part_id);
1183 break;
1184 default:
1185 panic("Invalid type for IMMU demap\n");
1186 }
1187 break;
1188 case ASI_DMMU:
1189 switch (va) {
1190 case 0x18:
1191 tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_SFSR, data);
1192 break;
1193 case 0x30:
|
| 1194 sext<59>(bits(data, 59,0));
|
1192 tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS, data);
1193 break;
1194 case 0x80:
1195 tc->setMiscRegWithEffect(MISCREG_MMU_PART_ID, data);
1196 break;
1197 default:
1198 goto doMmuWriteError;
1199 }
1200 break;
1201 case ASI_DMMU_DEMAP:
1202 ignore = false;
1203 ctx_id = -1;
1204 part_id = tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID);
1205 switch (bits(va,5,4)) {
1206 case 0:
1207 ctx_id = tc->readMiscRegWithEffect(MISCREG_MMU_P_CONTEXT);
1208 break;
1209 case 1:
1210 ctx_id = tc->readMiscRegWithEffect(MISCREG_MMU_S_CONTEXT);
1211 break;
1212 case 3:
1213 ctx_id = 0;
1214 break;
1215 default:
1216 ignore = true;
1217 }
1218
1219 switch(bits(va,7,6)) {
1220 case 0: // demap page
1221 if (!ignore)
1222 demapPage(mbits(va,63,13), part_id, bits(va,9,9), ctx_id);
1223 break;
1224 case 1: //demap context
1225 if (!ignore)
1226 demapContext(part_id, ctx_id);
1227 break;
1228 case 2:
1229 demapAll(part_id);
1230 break;
1231 default:
1232 panic("Invalid type for IMMU demap\n");
1233 }
1234 break;
1235 default:
1236doMmuWriteError:
1237 panic("need to impl DTB::doMmuRegWrite() got asi=%#x, va=%#x d=%#x\n",
1238 (uint32_t)pkt->req->getAsi(), pkt->getAddr(), data);
1239 }
1240 pkt->result = Packet::Success;
1241 return tc->getCpuPtr()->cycles(1);
1242}
1243
1244void
1245TLB::serialize(std::ostream &os)
1246{
1247 panic("Need to implement serialize tlb for SPARC\n");
1248}
1249
1250void
1251TLB::unserialize(Checkpoint *cp, const std::string §ion)
1252{
1253 panic("Need to implement unserialize tlb for SPARC\n");
1254}
1255
1256
1257DEFINE_SIM_OBJECT_CLASS_NAME("SparcTLB", TLB)
1258
1259BEGIN_DECLARE_SIM_OBJECT_PARAMS(ITB)
1260
1261 Param<int> size;
1262
1263END_DECLARE_SIM_OBJECT_PARAMS(ITB)
1264
1265BEGIN_INIT_SIM_OBJECT_PARAMS(ITB)
1266
1267 INIT_PARAM_DFLT(size, "TLB size", 48)
1268
1269END_INIT_SIM_OBJECT_PARAMS(ITB)
1270
1271
1272CREATE_SIM_OBJECT(ITB)
1273{
1274 return new ITB(getInstanceName(), size);
1275}
1276
1277REGISTER_SIM_OBJECT("SparcITB", ITB)
1278
1279BEGIN_DECLARE_SIM_OBJECT_PARAMS(DTB)
1280
1281 Param<int> size;
1282
1283END_DECLARE_SIM_OBJECT_PARAMS(DTB)
1284
1285BEGIN_INIT_SIM_OBJECT_PARAMS(DTB)
1286
1287 INIT_PARAM_DFLT(size, "TLB size", 64)
1288
1289END_INIT_SIM_OBJECT_PARAMS(DTB)
1290
1291
1292CREATE_SIM_OBJECT(DTB)
1293{
1294 return new DTB(getInstanceName(), size);
1295}
1296
1297REGISTER_SIM_OBJECT("SparcDTB", DTB)
1298}
| 1195 tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS, data);
1196 break;
1197 case 0x80:
1198 tc->setMiscRegWithEffect(MISCREG_MMU_PART_ID, data);
1199 break;
1200 default:
1201 goto doMmuWriteError;
1202 }
1203 break;
1204 case ASI_DMMU_DEMAP:
1205 ignore = false;
1206 ctx_id = -1;
1207 part_id = tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID);
1208 switch (bits(va,5,4)) {
1209 case 0:
1210 ctx_id = tc->readMiscRegWithEffect(MISCREG_MMU_P_CONTEXT);
1211 break;
1212 case 1:
1213 ctx_id = tc->readMiscRegWithEffect(MISCREG_MMU_S_CONTEXT);
1214 break;
1215 case 3:
1216 ctx_id = 0;
1217 break;
1218 default:
1219 ignore = true;
1220 }
1221
1222 switch(bits(va,7,6)) {
1223 case 0: // demap page
1224 if (!ignore)
1225 demapPage(mbits(va,63,13), part_id, bits(va,9,9), ctx_id);
1226 break;
1227 case 1: //demap context
1228 if (!ignore)
1229 demapContext(part_id, ctx_id);
1230 break;
1231 case 2:
1232 demapAll(part_id);
1233 break;
1234 default:
1235 panic("Invalid type for IMMU demap\n");
1236 }
1237 break;
1238 default:
1239doMmuWriteError:
1240 panic("need to impl DTB::doMmuRegWrite() got asi=%#x, va=%#x d=%#x\n",
1241 (uint32_t)pkt->req->getAsi(), pkt->getAddr(), data);
1242 }
1243 pkt->result = Packet::Success;
1244 return tc->getCpuPtr()->cycles(1);
1245}
1246
1247void
1248TLB::serialize(std::ostream &os)
1249{
1250 panic("Need to implement serialize tlb for SPARC\n");
1251}
1252
1253void
1254TLB::unserialize(Checkpoint *cp, const std::string §ion)
1255{
1256 panic("Need to implement unserialize tlb for SPARC\n");
1257}
1258
1259
1260DEFINE_SIM_OBJECT_CLASS_NAME("SparcTLB", TLB)
1261
1262BEGIN_DECLARE_SIM_OBJECT_PARAMS(ITB)
1263
1264 Param<int> size;
1265
1266END_DECLARE_SIM_OBJECT_PARAMS(ITB)
1267
1268BEGIN_INIT_SIM_OBJECT_PARAMS(ITB)
1269
1270 INIT_PARAM_DFLT(size, "TLB size", 48)
1271
1272END_INIT_SIM_OBJECT_PARAMS(ITB)
1273
1274
1275CREATE_SIM_OBJECT(ITB)
1276{
1277 return new ITB(getInstanceName(), size);
1278}
1279
1280REGISTER_SIM_OBJECT("SparcITB", ITB)
1281
1282BEGIN_DECLARE_SIM_OBJECT_PARAMS(DTB)
1283
1284 Param<int> size;
1285
1286END_DECLARE_SIM_OBJECT_PARAMS(DTB)
1287
1288BEGIN_INIT_SIM_OBJECT_PARAMS(DTB)
1289
1290 INIT_PARAM_DFLT(size, "TLB size", 64)
1291
1292END_INIT_SIM_OBJECT_PARAMS(DTB)
1293
1294
1295CREATE_SIM_OBJECT(DTB)
1296{
1297 return new DTB(getInstanceName(), size);
1298}
1299
1300REGISTER_SIM_OBJECT("SparcDTB", DTB)
1301}
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