1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Ali Saidi
29 */
30
31#include "arch/sparc/tlb.hh"
32
33#include <cstring>
34
35#include "arch/sparc/asi.hh"
36#include "arch/sparc/faults.hh"
37#include "arch/sparc/registers.hh"
38#include "base/bitfield.hh"
39#include "base/compiler.hh"
40#include "base/trace.hh"
41#include "cpu/base.hh"
42#include "cpu/thread_context.hh"
43#include "debug/IPR.hh"
44#include "debug/TLB.hh"
45#include "mem/packet_access.hh"
46#include "mem/request.hh"
47#include "sim/full_system.hh"
48#include "sim/system.hh"
49
50/* @todo remove some of the magic constants. -- ali
51 * */
52namespace SparcISA {
53
54TLB::TLB(const Params *p)
55 : BaseTLB(p), size(p->size), usedEntries(0), lastReplaced(0),
56 cacheState(0), cacheValid(false)
57{
58 // To make this work you'll have to change the hypervisor and OS
59 if (size > 64)
60 fatal("SPARC T1 TLB registers don't support more than 64 TLB entries");
61
62 tlb = new TlbEntry[size];
63 std::memset(tlb, 0, sizeof(TlbEntry) * size);
64
65 for (int x = 0; x < size; x++)
66 freeList.push_back(&tlb[x]);
67
68 c0_tsb_ps0 = 0;
69 c0_tsb_ps1 = 0;
70 c0_config = 0;
71 cx_tsb_ps0 = 0;
72 cx_tsb_ps1 = 0;
73 cx_config = 0;
74 sfsr = 0;
75 tag_access = 0;
76 sfar = 0;
77 cacheEntry[0] = NULL;
78 cacheEntry[1] = NULL;
79}
80
81void
82TLB::clearUsedBits()
83{
84 MapIter i;
85 for (i = lookupTable.begin(); i != lookupTable.end(); i++) {
86 TlbEntry *t = i->second;
87 if (!t->pte.locked()) {
88 t->used = false;
89 usedEntries--;
90 }
91 }
92}
93
94
95void
96TLB::insert(Addr va, int partition_id, int context_id, bool real,
97 const PageTableEntry& PTE, int entry)
98{
99 MapIter i;
100 TlbEntry *new_entry = NULL;
101// TlbRange tr;
102 int x;
103
104 cacheValid = false;
105 va &= ~(PTE.size()-1);
106 /* tr.va = va;
107 tr.size = PTE.size() - 1;
108 tr.contextId = context_id;
109 tr.partitionId = partition_id;
110 tr.real = real;
111*/
112
113 DPRINTF(TLB,
114 "TLB: Inserting Entry; va=%#x pa=%#x pid=%d cid=%d r=%d entryid=%d\n",
115 va, PTE.paddr(), partition_id, context_id, (int)real, entry);
116
117 // Demap any entry that conflicts
118 for (x = 0; x < size; x++) {
119 if (tlb[x].range.real == real &&
120 tlb[x].range.partitionId == partition_id &&
121 tlb[x].range.va < va + PTE.size() - 1 &&
122 tlb[x].range.va + tlb[x].range.size >= va &&
123 (real || tlb[x].range.contextId == context_id ))
124 {
125 if (tlb[x].valid) {
126 freeList.push_front(&tlb[x]);
127 DPRINTF(TLB, "TLB: Conflicting entry %#X , deleting it\n", x);
128
129 tlb[x].valid = false;
130 if (tlb[x].used) {
131 tlb[x].used = false;
132 usedEntries--;
133 }
134 lookupTable.erase(tlb[x].range);
135 }
136 }
137 }
138
139 if (entry != -1) {
140 assert(entry < size && entry >= 0);
141 new_entry = &tlb[entry];
142 } else {
143 if (!freeList.empty()) {
144 new_entry = freeList.front();
145 } else {
146 x = lastReplaced;
147 do {
148 ++x;
149 if (x == size)
150 x = 0;
151 if (x == lastReplaced)
152 goto insertAllLocked;
153 } while (tlb[x].pte.locked());
154 lastReplaced = x;
155 new_entry = &tlb[x];
156 }
157 }
158
159insertAllLocked:
160 // Update the last ently if their all locked
161 if (!new_entry) {
162 new_entry = &tlb[size-1];
163 }
164
165 freeList.remove(new_entry);
166 if (new_entry->valid && new_entry->used)
167 usedEntries--;
168 if (new_entry->valid)
169 lookupTable.erase(new_entry->range);
170
171
172 assert(PTE.valid());
173 new_entry->range.va = va;
174 new_entry->range.size = PTE.size() - 1;
175 new_entry->range.partitionId = partition_id;
176 new_entry->range.contextId = context_id;
177 new_entry->range.real = real;
178 new_entry->pte = PTE;
179 new_entry->used = true;;
180 new_entry->valid = true;
181 usedEntries++;
182
183 i = lookupTable.insert(new_entry->range, new_entry);
184 assert(i != lookupTable.end());
185
186 // If all entries have their used bit set, clear it on them all,
187 // but the one we just inserted
188 if (usedEntries == size) {
189 clearUsedBits();
190 new_entry->used = true;
191 usedEntries++;
192 }
193}
194
195
196TlbEntry*
197TLB::lookup(Addr va, int partition_id, bool real, int context_id,
198 bool update_used)
199{
200 MapIter i;
201 TlbRange tr;
202 TlbEntry *t;
203
204 DPRINTF(TLB, "TLB: Looking up entry va=%#x pid=%d cid=%d r=%d\n",
205 va, partition_id, context_id, real);
206 // Assemble full address structure
207 tr.va = va;
208 tr.size = 1;
209 tr.contextId = context_id;
210 tr.partitionId = partition_id;
211 tr.real = real;
212
213 // Try to find the entry
214 i = lookupTable.find(tr);
215 if (i == lookupTable.end()) {
216 DPRINTF(TLB, "TLB: No valid entry found\n");
217 return NULL;
218 }
219
220 // Mark the entries used bit and clear other used bits in needed
221 t = i->second;
222 DPRINTF(TLB, "TLB: Valid entry found pa: %#x size: %#x\n", t->pte.paddr(),
223 t->pte.size());
224
225 // Update the used bits only if this is a real access (not a fake
226 // one from virttophys()
227 if (!t->used && update_used) {
228 t->used = true;
229 usedEntries++;
230 if (usedEntries == size) {
231 clearUsedBits();
232 t->used = true;
233 usedEntries++;
234 }
235 }
236
237 return t;
238}
239
240void
241TLB::dumpAll()
242{
243 MapIter i;
244 for (int x = 0; x < size; x++) {
245 if (tlb[x].valid) {
246 DPRINTFN("%4d: %#2x:%#2x %c %#4x %#8x %#8x %#16x\n",
247 x, tlb[x].range.partitionId, tlb[x].range.contextId,
248 tlb[x].range.real ? 'R' : ' ', tlb[x].range.size,
249 tlb[x].range.va, tlb[x].pte.paddr(), tlb[x].pte());
250 }
251 }
252}
253
254void
255TLB::demapPage(Addr va, int partition_id, bool real, int context_id)
256{
257 TlbRange tr;
258 MapIter i;
259
260 DPRINTF(IPR, "TLB: Demapping Page va=%#x pid=%#d cid=%d r=%d\n",
261 va, partition_id, context_id, real);
262
263 cacheValid = false;
264
265 // Assemble full address structure
266 tr.va = va;
267 tr.size = 1;
268 tr.contextId = context_id;
269 tr.partitionId = partition_id;
270 tr.real = real;
271
272 // Demap any entry that conflicts
273 i = lookupTable.find(tr);
274 if (i != lookupTable.end()) {
275 DPRINTF(IPR, "TLB: Demapped page\n");
276 i->second->valid = false;
277 if (i->second->used) {
278 i->second->used = false;
279 usedEntries--;
280 }
281 freeList.push_front(i->second);
282 lookupTable.erase(i);
283 }
284}
285
286void
287TLB::demapContext(int partition_id, int context_id)
288{
289 DPRINTF(IPR, "TLB: Demapping Context pid=%#d cid=%d\n",
290 partition_id, context_id);
291 cacheValid = false;
292 for (int x = 0; x < size; x++) {
293 if (tlb[x].range.contextId == context_id &&
294 tlb[x].range.partitionId == partition_id) {
295 if (tlb[x].valid) {
296 freeList.push_front(&tlb[x]);
297 }
298 tlb[x].valid = false;
299 if (tlb[x].used) {
300 tlb[x].used = false;
301 usedEntries--;
302 }
303 lookupTable.erase(tlb[x].range);
304 }
305 }
306}
307
308void
309TLB::demapAll(int partition_id)
310{
311 DPRINTF(TLB, "TLB: Demapping All pid=%#d\n", partition_id);
312 cacheValid = false;
313 for (int x = 0; x < size; x++) {
314 if (tlb[x].valid && !tlb[x].pte.locked() &&
315 tlb[x].range.partitionId == partition_id) {
316 freeList.push_front(&tlb[x]);
317 tlb[x].valid = false;
318 if (tlb[x].used) {
319 tlb[x].used = false;
320 usedEntries--;
321 }
322 lookupTable.erase(tlb[x].range);
323 }
324 }
325}
326
327void
328TLB::flushAll()
329{
330 cacheValid = false;
331 lookupTable.clear();
332
333 for (int x = 0; x < size; x++) {
334 if (tlb[x].valid)
335 freeList.push_back(&tlb[x]);
336 tlb[x].valid = false;
337 tlb[x].used = false;
338 }
339 usedEntries = 0;
340}
341
342uint64_t
343TLB::TteRead(int entry)
344{
345 if (entry >= size)
346 panic("entry: %d\n", entry);
347
348 assert(entry < size);
349 if (tlb[entry].valid)
350 return tlb[entry].pte();
351 else
352 return (uint64_t)-1ll;
353}
354
355uint64_t
356TLB::TagRead(int entry)
357{
358 assert(entry < size);
359 uint64_t tag;
360 if (!tlb[entry].valid)
361 return (uint64_t)-1ll;
362
363 tag = tlb[entry].range.contextId;
364 tag |= tlb[entry].range.va;
365 tag |= (uint64_t)tlb[entry].range.partitionId << 61;
366 tag |= tlb[entry].range.real ? ULL(1) << 60 : 0;
367 tag |= (uint64_t)~tlb[entry].pte._size() << 56;
368 return tag;
369}
370
371bool
372TLB::validVirtualAddress(Addr va, bool am)
373{
374 if (am)
375 return true;
376 if (va >= StartVAddrHole && va <= EndVAddrHole)
377 return false;
378 return true;
379}
380
381void
382TLB::writeSfsr(bool write, ContextType ct, bool se, FaultTypes ft, int asi)
383{
384 if (sfsr & 0x1)
385 sfsr = 0x3;
386 else
387 sfsr = 1;
388
389 if (write)
390 sfsr |= 1 << 2;
391 sfsr |= ct << 4;
392 if (se)
393 sfsr |= 1 << 6;
394 sfsr |= ft << 7;
395 sfsr |= asi << 16;
396}
397
398void
399TLB::writeTagAccess(Addr va, int context)
400{
401 DPRINTF(TLB, "TLB: Writing Tag Access: va: %#X ctx: %#X value: %#X\n",
402 va, context, mbits(va, 63,13) | mbits(context,12,0));
403
404 tag_access = mbits(va, 63,13) | mbits(context,12,0);
405}
406
407void
408TLB::writeSfsr(Addr a, bool write, ContextType ct,
409 bool se, FaultTypes ft, int asi)
410{
411 DPRINTF(TLB, "TLB: Fault: A=%#x w=%d ct=%d ft=%d asi=%d\n",
412 a, (int)write, ct, ft, asi);
413 TLB::writeSfsr(write, ct, se, ft, asi);
414 sfar = a;
415}
416
417Fault
418TLB::translateInst(const RequestPtr &req, ThreadContext *tc)
419{
420 uint64_t tlbdata = tc->readMiscRegNoEffect(MISCREG_TLB_DATA);
421
422 Addr vaddr = req->getVaddr();
423 TlbEntry *e;
424
425 assert(req->getArchFlags() == ASI_IMPLICIT);
426
427 DPRINTF(TLB, "TLB: ITB Request to translate va=%#x size=%d\n",
428 vaddr, req->getSize());
429
430 // Be fast if we can!
431 if (cacheValid && cacheState == tlbdata) {
432 if (cacheEntry[0]) {
433 if (cacheEntry[0]->range.va < vaddr + sizeof(MachInst) &&
434 cacheEntry[0]->range.va + cacheEntry[0]->range.size >= vaddr) {
435 req->setPaddr(cacheEntry[0]->pte.translate(vaddr));
436 return NoFault;
437 }
438 } else {
439 req->setPaddr(vaddr & PAddrImplMask);
440 return NoFault;
441 }
442 }
443
444 bool hpriv = bits(tlbdata,0,0);
445 bool red = bits(tlbdata,1,1);
446 bool priv = bits(tlbdata,2,2);
447 bool addr_mask = bits(tlbdata,3,3);
448 bool lsu_im = bits(tlbdata,4,4);
449
450 int part_id = bits(tlbdata,15,8);
451 int tl = bits(tlbdata,18,16);
452 int pri_context = bits(tlbdata,47,32);
453 int context;
454 ContextType ct;
455 int asi;
456 bool real = false;
457
458 DPRINTF(TLB, "TLB: priv:%d hpriv:%d red:%d lsuim:%d part_id: %#X\n",
459 priv, hpriv, red, lsu_im, part_id);
460
461 if (tl > 0) {
462 asi = ASI_N;
463 ct = Nucleus;
464 context = 0;
465 } else {
466 asi = ASI_P;
467 ct = Primary;
468 context = pri_context;
469 }
470
471 if ( hpriv || red ) {
472 cacheValid = true;
473 cacheState = tlbdata;
474 cacheEntry[0] = NULL;
475 req->setPaddr(vaddr & PAddrImplMask);
476 return NoFault;
477 }
478
479 // If the access is unaligned trap
480 if (vaddr & 0x3) {
481 writeSfsr(false, ct, false, OtherFault, asi);
482 return std::make_shared<MemAddressNotAligned>();
483 }
484
485 if (addr_mask)
486 vaddr = vaddr & VAddrAMask;
487
488 if (!validVirtualAddress(vaddr, addr_mask)) {
489 writeSfsr(false, ct, false, VaOutOfRange, asi);
490 return std::make_shared<InstructionAccessException>();
491 }
492
493 if (!lsu_im) {
494 e = lookup(vaddr, part_id, true);
495 real = true;
496 context = 0;
497 } else {
498 e = lookup(vaddr, part_id, false, context);
499 }
500
501 if (e == NULL || !e->valid) {
502 writeTagAccess(vaddr, context);
503 if (real) {
504 return std::make_shared<InstructionRealTranslationMiss>();
505 } else {
506 if (FullSystem)
507 return std::make_shared<FastInstructionAccessMMUMiss>();
508 else
509 return std::make_shared<FastInstructionAccessMMUMiss>(
510 req->getVaddr());
511 }
512 }
513
514 // were not priviledged accesing priv page
515 if (!priv && e->pte.priv()) {
516 writeTagAccess(vaddr, context);
517 writeSfsr(false, ct, false, PrivViolation, asi);
518 return std::make_shared<InstructionAccessException>();
519 }
520
521 // cache translation date for next translation
522 cacheValid = true;
523 cacheState = tlbdata;
524 cacheEntry[0] = e;
525
526 req->setPaddr(e->pte.translate(vaddr));
527 DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr());
528 return NoFault;
529}
530
531Fault
532TLB::translateData(const RequestPtr &req, ThreadContext *tc, bool write)
533{
534 /*
535 * @todo this could really use some profiling and fixing to make
536 * it faster!
537 */
538 uint64_t tlbdata = tc->readMiscRegNoEffect(MISCREG_TLB_DATA);
539 Addr vaddr = req->getVaddr();
540 Addr size = req->getSize();
541 ASI asi;
542 asi = (ASI)req->getArchFlags();
543 bool implicit = false;
544 bool hpriv = bits(tlbdata,0,0);
545 bool unaligned = vaddr & (size - 1);
546
547 DPRINTF(TLB, "TLB: DTB Request to translate va=%#x size=%d asi=%#x\n",
548 vaddr, size, asi);
549
550 if (lookupTable.size() != 64 - freeList.size())
551 panic("Lookup table size: %d tlb size: %d\n", lookupTable.size(),
552 freeList.size());
553 if (asi == ASI_IMPLICIT)
554 implicit = true;
555
556 // Only use the fast path here if there doesn't need to be an unaligned
557 // trap later
558 if (!unaligned) {
559 if (hpriv && implicit) {
560 req->setPaddr(vaddr & PAddrImplMask);
561 return NoFault;
562 }
563
564 // Be fast if we can!
565 if (cacheValid && cacheState == tlbdata) {
566
567
568
569 if (cacheEntry[0]) {
570 TlbEntry *ce = cacheEntry[0];
571 Addr ce_va = ce->range.va;
572 if (cacheAsi[0] == asi &&
573 ce_va < vaddr + size && ce_va + ce->range.size > vaddr &&
574 (!write || ce->pte.writable())) {
575 req->setPaddr(ce->pte.translate(vaddr));
576 if (ce->pte.sideffect() || (ce->pte.paddr() >> 39) & 1) {
577 req->setFlags(
578 Request::UNCACHEABLE | Request::STRICT_ORDER);
579 }
580 DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr());
581 return NoFault;
582 } // if matched
583 } // if cache entry valid
584 if (cacheEntry[1]) {
585 TlbEntry *ce = cacheEntry[1];
586 Addr ce_va = ce->range.va;
587 if (cacheAsi[1] == asi &&
588 ce_va < vaddr + size && ce_va + ce->range.size > vaddr &&
589 (!write || ce->pte.writable())) {
590 req->setPaddr(ce->pte.translate(vaddr));
591 if (ce->pte.sideffect() || (ce->pte.paddr() >> 39) & 1) {
592 req->setFlags(
593 Request::UNCACHEABLE | Request::STRICT_ORDER);
594 }
595 DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr());
596 return NoFault;
597 } // if matched
598 } // if cache entry valid
599 }
600 }
601
602 bool red = bits(tlbdata,1,1);
603 bool priv = bits(tlbdata,2,2);
604 bool addr_mask = bits(tlbdata,3,3);
605 bool lsu_dm = bits(tlbdata,5,5);
606
607 int part_id = bits(tlbdata,15,8);
608 int tl = bits(tlbdata,18,16);
609 int pri_context = bits(tlbdata,47,32);
610 int sec_context = bits(tlbdata,63,48);
611
612 bool real = false;
613 ContextType ct = Primary;
614 int context = 0;
615
616 TlbEntry *e;
617
618 DPRINTF(TLB, "TLB: priv:%d hpriv:%d red:%d lsudm:%d part_id: %#X\n",
619 priv, hpriv, red, lsu_dm, part_id);
620
621 if (implicit) {
622 if (tl > 0) {
623 asi = ASI_N;
624 ct = Nucleus;
625 context = 0;
626 } else {
627 asi = ASI_P;
628 ct = Primary;
629 context = pri_context;
630 }
631 } else {
632 // We need to check for priv level/asi priv
633 if (!priv && !hpriv && !asiIsUnPriv(asi)) {
634 // It appears that context should be Nucleus in these cases?
635 writeSfsr(vaddr, write, Nucleus, false, IllegalAsi, asi);
636 return std::make_shared<PrivilegedAction>();
637 }
638
639 if (!hpriv && asiIsHPriv(asi)) {
640 writeSfsr(vaddr, write, Nucleus, false, IllegalAsi, asi);
641 return std::make_shared<DataAccessException>();
642 }
643
644 if (asiIsPrimary(asi)) {
645 context = pri_context;
646 ct = Primary;
647 } else if (asiIsSecondary(asi)) {
648 context = sec_context;
649 ct = Secondary;
650 } else if (asiIsNucleus(asi)) {
651 ct = Nucleus;
652 context = 0;
653 } else { // ????
654 ct = Primary;
655 context = pri_context;
656 }
657 }
658
659 if (!implicit && asi != ASI_P && asi != ASI_S) {
660 if (asiIsLittle(asi))
661 panic("Little Endian ASIs not supported\n");
662
663 //XXX It's unclear from looking at the documentation how a no fault
664 // load differs from a regular one, other than what happens concerning
665 // nfo and e bits in the TTE
666// if (asiIsNoFault(asi))
667// panic("No Fault ASIs not supported\n");
668
669 if (asiIsPartialStore(asi))
670 panic("Partial Store ASIs not supported\n");
671
672 if (asiIsCmt(asi))
673 panic("Cmt ASI registers not implmented\n");
674
675 if (asiIsInterrupt(asi))
676 goto handleIntRegAccess;
677 if (asiIsMmu(asi))
678 goto handleMmuRegAccess;
679 if (asiIsScratchPad(asi))
680 goto handleScratchRegAccess;
681 if (asiIsQueue(asi))
682 goto handleQueueRegAccess;
683 if (asiIsSparcError(asi))
684 goto handleSparcErrorRegAccess;
685
686 if (!asiIsReal(asi) && !asiIsNucleus(asi) && !asiIsAsIfUser(asi) &&
687 !asiIsTwin(asi) && !asiIsBlock(asi) && !asiIsNoFault(asi))
688 panic("Accessing ASI %#X. Should we?\n", asi);
689 }
690
691 // If the asi is unaligned trap
692 if (unaligned) {
693 writeSfsr(vaddr, false, ct, false, OtherFault, asi);
694 return std::make_shared<MemAddressNotAligned>();
695 }
696
697 if (addr_mask)
698 vaddr = vaddr & VAddrAMask;
699
700 if (!validVirtualAddress(vaddr, addr_mask)) {
701 writeSfsr(vaddr, false, ct, true, VaOutOfRange, asi);
702 return std::make_shared<DataAccessException>();
703 }
704
705 if ((!lsu_dm && !hpriv && !red) || asiIsReal(asi)) {
706 real = true;
707 context = 0;
708 }
709
710 if (hpriv && (implicit || (!asiIsAsIfUser(asi) && !asiIsReal(asi)))) {
711 req->setPaddr(vaddr & PAddrImplMask);
712 return NoFault;
713 }
714
715 e = lookup(vaddr, part_id, real, context);
716
717 if (e == NULL || !e->valid) {
718 writeTagAccess(vaddr, context);
719 DPRINTF(TLB, "TLB: DTB Failed to find matching TLB entry\n");
720 if (real) {
721 return std::make_shared<DataRealTranslationMiss>();
722 } else {
723 if (FullSystem)
724 return std::make_shared<FastDataAccessMMUMiss>();
725 else
726 return std::make_shared<FastDataAccessMMUMiss>(
727 req->getVaddr());
728 }
729
730 }
731
732 if (!priv && e->pte.priv()) {
733 writeTagAccess(vaddr, context);
734 writeSfsr(vaddr, write, ct, e->pte.sideffect(), PrivViolation, asi);
735 return std::make_shared<DataAccessException>();
736 }
737
738 if (write && !e->pte.writable()) {
739 writeTagAccess(vaddr, context);
740 writeSfsr(vaddr, write, ct, e->pte.sideffect(), OtherFault, asi);
741 return std::make_shared<FastDataAccessProtection>();
742 }
743
744 if (e->pte.nofault() && !asiIsNoFault(asi)) {
745 writeTagAccess(vaddr, context);
746 writeSfsr(vaddr, write, ct, e->pte.sideffect(), LoadFromNfo, asi);
747 return std::make_shared<DataAccessException>();
748 }
749
750 if (e->pte.sideffect() && asiIsNoFault(asi)) {
751 writeTagAccess(vaddr, context);
752 writeSfsr(vaddr, write, ct, e->pte.sideffect(), SideEffect, asi);
753 return std::make_shared<DataAccessException>();
754 }
755
756 if (e->pte.sideffect() || (e->pte.paddr() >> 39) & 1)
757 req->setFlags(Request::UNCACHEABLE | Request::STRICT_ORDER);
758
759 // cache translation date for next translation
760 cacheState = tlbdata;
761 if (!cacheValid) {
762 cacheEntry[1] = NULL;
763 cacheEntry[0] = NULL;
764 }
765
766 if (cacheEntry[0] != e && cacheEntry[1] != e) {
767 cacheEntry[1] = cacheEntry[0];
768 cacheEntry[0] = e;
769 cacheAsi[1] = cacheAsi[0];
770 cacheAsi[0] = asi;
771 if (implicit)
772 cacheAsi[0] = (ASI)0;
773 }
774 cacheValid = true;
775 req->setPaddr(e->pte.translate(vaddr));
776 DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr());
777 return NoFault;
778
779 /** Normal flow ends here. */
780handleIntRegAccess:
781 if (!hpriv) {
782 writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi);
783 if (priv)
784 return std::make_shared<DataAccessException>();
785 else
786 return std::make_shared<PrivilegedAction>();
787 }
788
789 if ((asi == ASI_SWVR_UDB_INTR_W && !write) ||
790 (asi == ASI_SWVR_UDB_INTR_R && write)) {
791 writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi);
792 return std::make_shared<DataAccessException>();
793 }
794
795 goto regAccessOk;
796
797
798handleScratchRegAccess:
799 if (vaddr > 0x38 || (vaddr >= 0x20 && vaddr < 0x30 && !hpriv)) {
800 writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi);
801 return std::make_shared<DataAccessException>();
802 }
803 goto regAccessOk;
804
805handleQueueRegAccess:
806 if (!priv && !hpriv) {
807 writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi);
808 return std::make_shared<PrivilegedAction>();
809 }
810 if ((!hpriv && vaddr & 0xF) || vaddr > 0x3f8 || vaddr < 0x3c0) {
811 writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi);
812 return std::make_shared<DataAccessException>();
813 }
814 goto regAccessOk;
815
816handleSparcErrorRegAccess:
817 if (!hpriv) {
818 writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi);
819 if (priv)
820 return std::make_shared<DataAccessException>();
821 else
822 return std::make_shared<PrivilegedAction>();
823 }
824 goto regAccessOk;
825
826
827regAccessOk:
828handleMmuRegAccess:
829 DPRINTF(TLB, "TLB: DTB Translating MM IPR access\n");
830 req->setFlags(Request::MMAPPED_IPR);
831 req->setPaddr(req->getVaddr());
832 return NoFault;
833};
834
835Fault
836TLB::translateAtomic(const RequestPtr &req, ThreadContext *tc, Mode mode)
837{
838 if (mode == Execute)
839 return translateInst(req, tc);
840 else
841 return translateData(req, tc, mode == Write);
842}
843
844void
845TLB::translateTiming(const RequestPtr &req, ThreadContext *tc,
846 Translation *translation, Mode mode)
847{
848 assert(translation);
849 translation->finish(translateAtomic(req, tc, mode), req, tc, mode);
850}
851
852Fault
853TLB::finalizePhysical(const RequestPtr &req,
854 ThreadContext *tc, Mode mode) const
855{
856 return NoFault;
857}
858
859Cycles
860TLB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
861{
862 Addr va = pkt->getAddr();
863 ASI asi = (ASI)pkt->req->getArchFlags();
864 uint64_t temp;
865
866 DPRINTF(IPR, "Memory Mapped IPR Read: asi=%#X a=%#x\n",
867 (uint32_t)pkt->req->getArchFlags(), pkt->getAddr());
868
869 TLB *itb = dynamic_cast<TLB *>(tc->getITBPtr());
870
871 switch (asi) {
872 case ASI_LSU_CONTROL_REG:
873 assert(va == 0);
| 1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Ali Saidi
29 */
30
31#include "arch/sparc/tlb.hh"
32
33#include <cstring>
34
35#include "arch/sparc/asi.hh"
36#include "arch/sparc/faults.hh"
37#include "arch/sparc/registers.hh"
38#include "base/bitfield.hh"
39#include "base/compiler.hh"
40#include "base/trace.hh"
41#include "cpu/base.hh"
42#include "cpu/thread_context.hh"
43#include "debug/IPR.hh"
44#include "debug/TLB.hh"
45#include "mem/packet_access.hh"
46#include "mem/request.hh"
47#include "sim/full_system.hh"
48#include "sim/system.hh"
49
50/* @todo remove some of the magic constants. -- ali
51 * */
52namespace SparcISA {
53
54TLB::TLB(const Params *p)
55 : BaseTLB(p), size(p->size), usedEntries(0), lastReplaced(0),
56 cacheState(0), cacheValid(false)
57{
58 // To make this work you'll have to change the hypervisor and OS
59 if (size > 64)
60 fatal("SPARC T1 TLB registers don't support more than 64 TLB entries");
61
62 tlb = new TlbEntry[size];
63 std::memset(tlb, 0, sizeof(TlbEntry) * size);
64
65 for (int x = 0; x < size; x++)
66 freeList.push_back(&tlb[x]);
67
68 c0_tsb_ps0 = 0;
69 c0_tsb_ps1 = 0;
70 c0_config = 0;
71 cx_tsb_ps0 = 0;
72 cx_tsb_ps1 = 0;
73 cx_config = 0;
74 sfsr = 0;
75 tag_access = 0;
76 sfar = 0;
77 cacheEntry[0] = NULL;
78 cacheEntry[1] = NULL;
79}
80
81void
82TLB::clearUsedBits()
83{
84 MapIter i;
85 for (i = lookupTable.begin(); i != lookupTable.end(); i++) {
86 TlbEntry *t = i->second;
87 if (!t->pte.locked()) {
88 t->used = false;
89 usedEntries--;
90 }
91 }
92}
93
94
95void
96TLB::insert(Addr va, int partition_id, int context_id, bool real,
97 const PageTableEntry& PTE, int entry)
98{
99 MapIter i;
100 TlbEntry *new_entry = NULL;
101// TlbRange tr;
102 int x;
103
104 cacheValid = false;
105 va &= ~(PTE.size()-1);
106 /* tr.va = va;
107 tr.size = PTE.size() - 1;
108 tr.contextId = context_id;
109 tr.partitionId = partition_id;
110 tr.real = real;
111*/
112
113 DPRINTF(TLB,
114 "TLB: Inserting Entry; va=%#x pa=%#x pid=%d cid=%d r=%d entryid=%d\n",
115 va, PTE.paddr(), partition_id, context_id, (int)real, entry);
116
117 // Demap any entry that conflicts
118 for (x = 0; x < size; x++) {
119 if (tlb[x].range.real == real &&
120 tlb[x].range.partitionId == partition_id &&
121 tlb[x].range.va < va + PTE.size() - 1 &&
122 tlb[x].range.va + tlb[x].range.size >= va &&
123 (real || tlb[x].range.contextId == context_id ))
124 {
125 if (tlb[x].valid) {
126 freeList.push_front(&tlb[x]);
127 DPRINTF(TLB, "TLB: Conflicting entry %#X , deleting it\n", x);
128
129 tlb[x].valid = false;
130 if (tlb[x].used) {
131 tlb[x].used = false;
132 usedEntries--;
133 }
134 lookupTable.erase(tlb[x].range);
135 }
136 }
137 }
138
139 if (entry != -1) {
140 assert(entry < size && entry >= 0);
141 new_entry = &tlb[entry];
142 } else {
143 if (!freeList.empty()) {
144 new_entry = freeList.front();
145 } else {
146 x = lastReplaced;
147 do {
148 ++x;
149 if (x == size)
150 x = 0;
151 if (x == lastReplaced)
152 goto insertAllLocked;
153 } while (tlb[x].pte.locked());
154 lastReplaced = x;
155 new_entry = &tlb[x];
156 }
157 }
158
159insertAllLocked:
160 // Update the last ently if their all locked
161 if (!new_entry) {
162 new_entry = &tlb[size-1];
163 }
164
165 freeList.remove(new_entry);
166 if (new_entry->valid && new_entry->used)
167 usedEntries--;
168 if (new_entry->valid)
169 lookupTable.erase(new_entry->range);
170
171
172 assert(PTE.valid());
173 new_entry->range.va = va;
174 new_entry->range.size = PTE.size() - 1;
175 new_entry->range.partitionId = partition_id;
176 new_entry->range.contextId = context_id;
177 new_entry->range.real = real;
178 new_entry->pte = PTE;
179 new_entry->used = true;;
180 new_entry->valid = true;
181 usedEntries++;
182
183 i = lookupTable.insert(new_entry->range, new_entry);
184 assert(i != lookupTable.end());
185
186 // If all entries have their used bit set, clear it on them all,
187 // but the one we just inserted
188 if (usedEntries == size) {
189 clearUsedBits();
190 new_entry->used = true;
191 usedEntries++;
192 }
193}
194
195
196TlbEntry*
197TLB::lookup(Addr va, int partition_id, bool real, int context_id,
198 bool update_used)
199{
200 MapIter i;
201 TlbRange tr;
202 TlbEntry *t;
203
204 DPRINTF(TLB, "TLB: Looking up entry va=%#x pid=%d cid=%d r=%d\n",
205 va, partition_id, context_id, real);
206 // Assemble full address structure
207 tr.va = va;
208 tr.size = 1;
209 tr.contextId = context_id;
210 tr.partitionId = partition_id;
211 tr.real = real;
212
213 // Try to find the entry
214 i = lookupTable.find(tr);
215 if (i == lookupTable.end()) {
216 DPRINTF(TLB, "TLB: No valid entry found\n");
217 return NULL;
218 }
219
220 // Mark the entries used bit and clear other used bits in needed
221 t = i->second;
222 DPRINTF(TLB, "TLB: Valid entry found pa: %#x size: %#x\n", t->pte.paddr(),
223 t->pte.size());
224
225 // Update the used bits only if this is a real access (not a fake
226 // one from virttophys()
227 if (!t->used && update_used) {
228 t->used = true;
229 usedEntries++;
230 if (usedEntries == size) {
231 clearUsedBits();
232 t->used = true;
233 usedEntries++;
234 }
235 }
236
237 return t;
238}
239
240void
241TLB::dumpAll()
242{
243 MapIter i;
244 for (int x = 0; x < size; x++) {
245 if (tlb[x].valid) {
246 DPRINTFN("%4d: %#2x:%#2x %c %#4x %#8x %#8x %#16x\n",
247 x, tlb[x].range.partitionId, tlb[x].range.contextId,
248 tlb[x].range.real ? 'R' : ' ', tlb[x].range.size,
249 tlb[x].range.va, tlb[x].pte.paddr(), tlb[x].pte());
250 }
251 }
252}
253
254void
255TLB::demapPage(Addr va, int partition_id, bool real, int context_id)
256{
257 TlbRange tr;
258 MapIter i;
259
260 DPRINTF(IPR, "TLB: Demapping Page va=%#x pid=%#d cid=%d r=%d\n",
261 va, partition_id, context_id, real);
262
263 cacheValid = false;
264
265 // Assemble full address structure
266 tr.va = va;
267 tr.size = 1;
268 tr.contextId = context_id;
269 tr.partitionId = partition_id;
270 tr.real = real;
271
272 // Demap any entry that conflicts
273 i = lookupTable.find(tr);
274 if (i != lookupTable.end()) {
275 DPRINTF(IPR, "TLB: Demapped page\n");
276 i->second->valid = false;
277 if (i->second->used) {
278 i->second->used = false;
279 usedEntries--;
280 }
281 freeList.push_front(i->second);
282 lookupTable.erase(i);
283 }
284}
285
286void
287TLB::demapContext(int partition_id, int context_id)
288{
289 DPRINTF(IPR, "TLB: Demapping Context pid=%#d cid=%d\n",
290 partition_id, context_id);
291 cacheValid = false;
292 for (int x = 0; x < size; x++) {
293 if (tlb[x].range.contextId == context_id &&
294 tlb[x].range.partitionId == partition_id) {
295 if (tlb[x].valid) {
296 freeList.push_front(&tlb[x]);
297 }
298 tlb[x].valid = false;
299 if (tlb[x].used) {
300 tlb[x].used = false;
301 usedEntries--;
302 }
303 lookupTable.erase(tlb[x].range);
304 }
305 }
306}
307
308void
309TLB::demapAll(int partition_id)
310{
311 DPRINTF(TLB, "TLB: Demapping All pid=%#d\n", partition_id);
312 cacheValid = false;
313 for (int x = 0; x < size; x++) {
314 if (tlb[x].valid && !tlb[x].pte.locked() &&
315 tlb[x].range.partitionId == partition_id) {
316 freeList.push_front(&tlb[x]);
317 tlb[x].valid = false;
318 if (tlb[x].used) {
319 tlb[x].used = false;
320 usedEntries--;
321 }
322 lookupTable.erase(tlb[x].range);
323 }
324 }
325}
326
327void
328TLB::flushAll()
329{
330 cacheValid = false;
331 lookupTable.clear();
332
333 for (int x = 0; x < size; x++) {
334 if (tlb[x].valid)
335 freeList.push_back(&tlb[x]);
336 tlb[x].valid = false;
337 tlb[x].used = false;
338 }
339 usedEntries = 0;
340}
341
342uint64_t
343TLB::TteRead(int entry)
344{
345 if (entry >= size)
346 panic("entry: %d\n", entry);
347
348 assert(entry < size);
349 if (tlb[entry].valid)
350 return tlb[entry].pte();
351 else
352 return (uint64_t)-1ll;
353}
354
355uint64_t
356TLB::TagRead(int entry)
357{
358 assert(entry < size);
359 uint64_t tag;
360 if (!tlb[entry].valid)
361 return (uint64_t)-1ll;
362
363 tag = tlb[entry].range.contextId;
364 tag |= tlb[entry].range.va;
365 tag |= (uint64_t)tlb[entry].range.partitionId << 61;
366 tag |= tlb[entry].range.real ? ULL(1) << 60 : 0;
367 tag |= (uint64_t)~tlb[entry].pte._size() << 56;
368 return tag;
369}
370
371bool
372TLB::validVirtualAddress(Addr va, bool am)
373{
374 if (am)
375 return true;
376 if (va >= StartVAddrHole && va <= EndVAddrHole)
377 return false;
378 return true;
379}
380
381void
382TLB::writeSfsr(bool write, ContextType ct, bool se, FaultTypes ft, int asi)
383{
384 if (sfsr & 0x1)
385 sfsr = 0x3;
386 else
387 sfsr = 1;
388
389 if (write)
390 sfsr |= 1 << 2;
391 sfsr |= ct << 4;
392 if (se)
393 sfsr |= 1 << 6;
394 sfsr |= ft << 7;
395 sfsr |= asi << 16;
396}
397
398void
399TLB::writeTagAccess(Addr va, int context)
400{
401 DPRINTF(TLB, "TLB: Writing Tag Access: va: %#X ctx: %#X value: %#X\n",
402 va, context, mbits(va, 63,13) | mbits(context,12,0));
403
404 tag_access = mbits(va, 63,13) | mbits(context,12,0);
405}
406
407void
408TLB::writeSfsr(Addr a, bool write, ContextType ct,
409 bool se, FaultTypes ft, int asi)
410{
411 DPRINTF(TLB, "TLB: Fault: A=%#x w=%d ct=%d ft=%d asi=%d\n",
412 a, (int)write, ct, ft, asi);
413 TLB::writeSfsr(write, ct, se, ft, asi);
414 sfar = a;
415}
416
417Fault
418TLB::translateInst(const RequestPtr &req, ThreadContext *tc)
419{
420 uint64_t tlbdata = tc->readMiscRegNoEffect(MISCREG_TLB_DATA);
421
422 Addr vaddr = req->getVaddr();
423 TlbEntry *e;
424
425 assert(req->getArchFlags() == ASI_IMPLICIT);
426
427 DPRINTF(TLB, "TLB: ITB Request to translate va=%#x size=%d\n",
428 vaddr, req->getSize());
429
430 // Be fast if we can!
431 if (cacheValid && cacheState == tlbdata) {
432 if (cacheEntry[0]) {
433 if (cacheEntry[0]->range.va < vaddr + sizeof(MachInst) &&
434 cacheEntry[0]->range.va + cacheEntry[0]->range.size >= vaddr) {
435 req->setPaddr(cacheEntry[0]->pte.translate(vaddr));
436 return NoFault;
437 }
438 } else {
439 req->setPaddr(vaddr & PAddrImplMask);
440 return NoFault;
441 }
442 }
443
444 bool hpriv = bits(tlbdata,0,0);
445 bool red = bits(tlbdata,1,1);
446 bool priv = bits(tlbdata,2,2);
447 bool addr_mask = bits(tlbdata,3,3);
448 bool lsu_im = bits(tlbdata,4,4);
449
450 int part_id = bits(tlbdata,15,8);
451 int tl = bits(tlbdata,18,16);
452 int pri_context = bits(tlbdata,47,32);
453 int context;
454 ContextType ct;
455 int asi;
456 bool real = false;
457
458 DPRINTF(TLB, "TLB: priv:%d hpriv:%d red:%d lsuim:%d part_id: %#X\n",
459 priv, hpriv, red, lsu_im, part_id);
460
461 if (tl > 0) {
462 asi = ASI_N;
463 ct = Nucleus;
464 context = 0;
465 } else {
466 asi = ASI_P;
467 ct = Primary;
468 context = pri_context;
469 }
470
471 if ( hpriv || red ) {
472 cacheValid = true;
473 cacheState = tlbdata;
474 cacheEntry[0] = NULL;
475 req->setPaddr(vaddr & PAddrImplMask);
476 return NoFault;
477 }
478
479 // If the access is unaligned trap
480 if (vaddr & 0x3) {
481 writeSfsr(false, ct, false, OtherFault, asi);
482 return std::make_shared<MemAddressNotAligned>();
483 }
484
485 if (addr_mask)
486 vaddr = vaddr & VAddrAMask;
487
488 if (!validVirtualAddress(vaddr, addr_mask)) {
489 writeSfsr(false, ct, false, VaOutOfRange, asi);
490 return std::make_shared<InstructionAccessException>();
491 }
492
493 if (!lsu_im) {
494 e = lookup(vaddr, part_id, true);
495 real = true;
496 context = 0;
497 } else {
498 e = lookup(vaddr, part_id, false, context);
499 }
500
501 if (e == NULL || !e->valid) {
502 writeTagAccess(vaddr, context);
503 if (real) {
504 return std::make_shared<InstructionRealTranslationMiss>();
505 } else {
506 if (FullSystem)
507 return std::make_shared<FastInstructionAccessMMUMiss>();
508 else
509 return std::make_shared<FastInstructionAccessMMUMiss>(
510 req->getVaddr());
511 }
512 }
513
514 // were not priviledged accesing priv page
515 if (!priv && e->pte.priv()) {
516 writeTagAccess(vaddr, context);
517 writeSfsr(false, ct, false, PrivViolation, asi);
518 return std::make_shared<InstructionAccessException>();
519 }
520
521 // cache translation date for next translation
522 cacheValid = true;
523 cacheState = tlbdata;
524 cacheEntry[0] = e;
525
526 req->setPaddr(e->pte.translate(vaddr));
527 DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr());
528 return NoFault;
529}
530
531Fault
532TLB::translateData(const RequestPtr &req, ThreadContext *tc, bool write)
533{
534 /*
535 * @todo this could really use some profiling and fixing to make
536 * it faster!
537 */
538 uint64_t tlbdata = tc->readMiscRegNoEffect(MISCREG_TLB_DATA);
539 Addr vaddr = req->getVaddr();
540 Addr size = req->getSize();
541 ASI asi;
542 asi = (ASI)req->getArchFlags();
543 bool implicit = false;
544 bool hpriv = bits(tlbdata,0,0);
545 bool unaligned = vaddr & (size - 1);
546
547 DPRINTF(TLB, "TLB: DTB Request to translate va=%#x size=%d asi=%#x\n",
548 vaddr, size, asi);
549
550 if (lookupTable.size() != 64 - freeList.size())
551 panic("Lookup table size: %d tlb size: %d\n", lookupTable.size(),
552 freeList.size());
553 if (asi == ASI_IMPLICIT)
554 implicit = true;
555
556 // Only use the fast path here if there doesn't need to be an unaligned
557 // trap later
558 if (!unaligned) {
559 if (hpriv && implicit) {
560 req->setPaddr(vaddr & PAddrImplMask);
561 return NoFault;
562 }
563
564 // Be fast if we can!
565 if (cacheValid && cacheState == tlbdata) {
566
567
568
569 if (cacheEntry[0]) {
570 TlbEntry *ce = cacheEntry[0];
571 Addr ce_va = ce->range.va;
572 if (cacheAsi[0] == asi &&
573 ce_va < vaddr + size && ce_va + ce->range.size > vaddr &&
574 (!write || ce->pte.writable())) {
575 req->setPaddr(ce->pte.translate(vaddr));
576 if (ce->pte.sideffect() || (ce->pte.paddr() >> 39) & 1) {
577 req->setFlags(
578 Request::UNCACHEABLE | Request::STRICT_ORDER);
579 }
580 DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr());
581 return NoFault;
582 } // if matched
583 } // if cache entry valid
584 if (cacheEntry[1]) {
585 TlbEntry *ce = cacheEntry[1];
586 Addr ce_va = ce->range.va;
587 if (cacheAsi[1] == asi &&
588 ce_va < vaddr + size && ce_va + ce->range.size > vaddr &&
589 (!write || ce->pte.writable())) {
590 req->setPaddr(ce->pte.translate(vaddr));
591 if (ce->pte.sideffect() || (ce->pte.paddr() >> 39) & 1) {
592 req->setFlags(
593 Request::UNCACHEABLE | Request::STRICT_ORDER);
594 }
595 DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr());
596 return NoFault;
597 } // if matched
598 } // if cache entry valid
599 }
600 }
601
602 bool red = bits(tlbdata,1,1);
603 bool priv = bits(tlbdata,2,2);
604 bool addr_mask = bits(tlbdata,3,3);
605 bool lsu_dm = bits(tlbdata,5,5);
606
607 int part_id = bits(tlbdata,15,8);
608 int tl = bits(tlbdata,18,16);
609 int pri_context = bits(tlbdata,47,32);
610 int sec_context = bits(tlbdata,63,48);
611
612 bool real = false;
613 ContextType ct = Primary;
614 int context = 0;
615
616 TlbEntry *e;
617
618 DPRINTF(TLB, "TLB: priv:%d hpriv:%d red:%d lsudm:%d part_id: %#X\n",
619 priv, hpriv, red, lsu_dm, part_id);
620
621 if (implicit) {
622 if (tl > 0) {
623 asi = ASI_N;
624 ct = Nucleus;
625 context = 0;
626 } else {
627 asi = ASI_P;
628 ct = Primary;
629 context = pri_context;
630 }
631 } else {
632 // We need to check for priv level/asi priv
633 if (!priv && !hpriv && !asiIsUnPriv(asi)) {
634 // It appears that context should be Nucleus in these cases?
635 writeSfsr(vaddr, write, Nucleus, false, IllegalAsi, asi);
636 return std::make_shared<PrivilegedAction>();
637 }
638
639 if (!hpriv && asiIsHPriv(asi)) {
640 writeSfsr(vaddr, write, Nucleus, false, IllegalAsi, asi);
641 return std::make_shared<DataAccessException>();
642 }
643
644 if (asiIsPrimary(asi)) {
645 context = pri_context;
646 ct = Primary;
647 } else if (asiIsSecondary(asi)) {
648 context = sec_context;
649 ct = Secondary;
650 } else if (asiIsNucleus(asi)) {
651 ct = Nucleus;
652 context = 0;
653 } else { // ????
654 ct = Primary;
655 context = pri_context;
656 }
657 }
658
659 if (!implicit && asi != ASI_P && asi != ASI_S) {
660 if (asiIsLittle(asi))
661 panic("Little Endian ASIs not supported\n");
662
663 //XXX It's unclear from looking at the documentation how a no fault
664 // load differs from a regular one, other than what happens concerning
665 // nfo and e bits in the TTE
666// if (asiIsNoFault(asi))
667// panic("No Fault ASIs not supported\n");
668
669 if (asiIsPartialStore(asi))
670 panic("Partial Store ASIs not supported\n");
671
672 if (asiIsCmt(asi))
673 panic("Cmt ASI registers not implmented\n");
674
675 if (asiIsInterrupt(asi))
676 goto handleIntRegAccess;
677 if (asiIsMmu(asi))
678 goto handleMmuRegAccess;
679 if (asiIsScratchPad(asi))
680 goto handleScratchRegAccess;
681 if (asiIsQueue(asi))
682 goto handleQueueRegAccess;
683 if (asiIsSparcError(asi))
684 goto handleSparcErrorRegAccess;
685
686 if (!asiIsReal(asi) && !asiIsNucleus(asi) && !asiIsAsIfUser(asi) &&
687 !asiIsTwin(asi) && !asiIsBlock(asi) && !asiIsNoFault(asi))
688 panic("Accessing ASI %#X. Should we?\n", asi);
689 }
690
691 // If the asi is unaligned trap
692 if (unaligned) {
693 writeSfsr(vaddr, false, ct, false, OtherFault, asi);
694 return std::make_shared<MemAddressNotAligned>();
695 }
696
697 if (addr_mask)
698 vaddr = vaddr & VAddrAMask;
699
700 if (!validVirtualAddress(vaddr, addr_mask)) {
701 writeSfsr(vaddr, false, ct, true, VaOutOfRange, asi);
702 return std::make_shared<DataAccessException>();
703 }
704
705 if ((!lsu_dm && !hpriv && !red) || asiIsReal(asi)) {
706 real = true;
707 context = 0;
708 }
709
710 if (hpriv && (implicit || (!asiIsAsIfUser(asi) && !asiIsReal(asi)))) {
711 req->setPaddr(vaddr & PAddrImplMask);
712 return NoFault;
713 }
714
715 e = lookup(vaddr, part_id, real, context);
716
717 if (e == NULL || !e->valid) {
718 writeTagAccess(vaddr, context);
719 DPRINTF(TLB, "TLB: DTB Failed to find matching TLB entry\n");
720 if (real) {
721 return std::make_shared<DataRealTranslationMiss>();
722 } else {
723 if (FullSystem)
724 return std::make_shared<FastDataAccessMMUMiss>();
725 else
726 return std::make_shared<FastDataAccessMMUMiss>(
727 req->getVaddr());
728 }
729
730 }
731
732 if (!priv && e->pte.priv()) {
733 writeTagAccess(vaddr, context);
734 writeSfsr(vaddr, write, ct, e->pte.sideffect(), PrivViolation, asi);
735 return std::make_shared<DataAccessException>();
736 }
737
738 if (write && !e->pte.writable()) {
739 writeTagAccess(vaddr, context);
740 writeSfsr(vaddr, write, ct, e->pte.sideffect(), OtherFault, asi);
741 return std::make_shared<FastDataAccessProtection>();
742 }
743
744 if (e->pte.nofault() && !asiIsNoFault(asi)) {
745 writeTagAccess(vaddr, context);
746 writeSfsr(vaddr, write, ct, e->pte.sideffect(), LoadFromNfo, asi);
747 return std::make_shared<DataAccessException>();
748 }
749
750 if (e->pte.sideffect() && asiIsNoFault(asi)) {
751 writeTagAccess(vaddr, context);
752 writeSfsr(vaddr, write, ct, e->pte.sideffect(), SideEffect, asi);
753 return std::make_shared<DataAccessException>();
754 }
755
756 if (e->pte.sideffect() || (e->pte.paddr() >> 39) & 1)
757 req->setFlags(Request::UNCACHEABLE | Request::STRICT_ORDER);
758
759 // cache translation date for next translation
760 cacheState = tlbdata;
761 if (!cacheValid) {
762 cacheEntry[1] = NULL;
763 cacheEntry[0] = NULL;
764 }
765
766 if (cacheEntry[0] != e && cacheEntry[1] != e) {
767 cacheEntry[1] = cacheEntry[0];
768 cacheEntry[0] = e;
769 cacheAsi[1] = cacheAsi[0];
770 cacheAsi[0] = asi;
771 if (implicit)
772 cacheAsi[0] = (ASI)0;
773 }
774 cacheValid = true;
775 req->setPaddr(e->pte.translate(vaddr));
776 DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr());
777 return NoFault;
778
779 /** Normal flow ends here. */
780handleIntRegAccess:
781 if (!hpriv) {
782 writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi);
783 if (priv)
784 return std::make_shared<DataAccessException>();
785 else
786 return std::make_shared<PrivilegedAction>();
787 }
788
789 if ((asi == ASI_SWVR_UDB_INTR_W && !write) ||
790 (asi == ASI_SWVR_UDB_INTR_R && write)) {
791 writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi);
792 return std::make_shared<DataAccessException>();
793 }
794
795 goto regAccessOk;
796
797
798handleScratchRegAccess:
799 if (vaddr > 0x38 || (vaddr >= 0x20 && vaddr < 0x30 && !hpriv)) {
800 writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi);
801 return std::make_shared<DataAccessException>();
802 }
803 goto regAccessOk;
804
805handleQueueRegAccess:
806 if (!priv && !hpriv) {
807 writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi);
808 return std::make_shared<PrivilegedAction>();
809 }
810 if ((!hpriv && vaddr & 0xF) || vaddr > 0x3f8 || vaddr < 0x3c0) {
811 writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi);
812 return std::make_shared<DataAccessException>();
813 }
814 goto regAccessOk;
815
816handleSparcErrorRegAccess:
817 if (!hpriv) {
818 writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi);
819 if (priv)
820 return std::make_shared<DataAccessException>();
821 else
822 return std::make_shared<PrivilegedAction>();
823 }
824 goto regAccessOk;
825
826
827regAccessOk:
828handleMmuRegAccess:
829 DPRINTF(TLB, "TLB: DTB Translating MM IPR access\n");
830 req->setFlags(Request::MMAPPED_IPR);
831 req->setPaddr(req->getVaddr());
832 return NoFault;
833};
834
835Fault
836TLB::translateAtomic(const RequestPtr &req, ThreadContext *tc, Mode mode)
837{
838 if (mode == Execute)
839 return translateInst(req, tc);
840 else
841 return translateData(req, tc, mode == Write);
842}
843
844void
845TLB::translateTiming(const RequestPtr &req, ThreadContext *tc,
846 Translation *translation, Mode mode)
847{
848 assert(translation);
849 translation->finish(translateAtomic(req, tc, mode), req, tc, mode);
850}
851
852Fault
853TLB::finalizePhysical(const RequestPtr &req,
854 ThreadContext *tc, Mode mode) const
855{
856 return NoFault;
857}
858
859Cycles
860TLB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
861{
862 Addr va = pkt->getAddr();
863 ASI asi = (ASI)pkt->req->getArchFlags();
864 uint64_t temp;
865
866 DPRINTF(IPR, "Memory Mapped IPR Read: asi=%#X a=%#x\n",
867 (uint32_t)pkt->req->getArchFlags(), pkt->getAddr());
868
869 TLB *itb = dynamic_cast<TLB *>(tc->getITBPtr());
870
871 switch (asi) {
872 case ASI_LSU_CONTROL_REG:
873 assert(va == 0);
|
874 pkt->set(tc->readMiscReg(MISCREG_MMU_LSU_CTRL));
| 874 pkt->setBE(tc->readMiscReg(MISCREG_MMU_LSU_CTRL));
|
875 break;
876 case ASI_MMU:
877 switch (va) {
878 case 0x8:
| 875 break;
876 case ASI_MMU:
877 switch (va) {
878 case 0x8:
|
879 pkt->set(tc->readMiscReg(MISCREG_MMU_P_CONTEXT));
| 879 pkt->setBE(tc->readMiscReg(MISCREG_MMU_P_CONTEXT));
|
880 break;
881 case 0x10:
| 880 break;
881 case 0x10:
|
882 pkt->set(tc->readMiscReg(MISCREG_MMU_S_CONTEXT));
| 882 pkt->setBE(tc->readMiscReg(MISCREG_MMU_S_CONTEXT));
|
883 break;
884 default:
885 goto doMmuReadError;
886 }
887 break;
888 case ASI_QUEUE:
| 883 break;
884 default:
885 goto doMmuReadError;
886 }
887 break;
888 case ASI_QUEUE:
|
889 pkt->set(tc->readMiscReg(MISCREG_QUEUE_CPU_MONDO_HEAD +
| 889 pkt->setBE(tc->readMiscReg(MISCREG_QUEUE_CPU_MONDO_HEAD +
|
890 (va >> 4) - 0x3c));
891 break;
892 case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0:
893 assert(va == 0);
| 890 (va >> 4) - 0x3c));
891 break;
892 case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0:
893 assert(va == 0);
|
894 pkt->set(c0_tsb_ps0);
| 894 pkt->setBE(c0_tsb_ps0);
|
895 break;
896 case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1:
897 assert(va == 0);
| 895 break;
896 case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1:
897 assert(va == 0);
|
898 pkt->set(c0_tsb_ps1);
| 898 pkt->setBE(c0_tsb_ps1);
|
899 break;
900 case ASI_DMMU_CTXT_ZERO_CONFIG:
901 assert(va == 0);
| 899 break;
900 case ASI_DMMU_CTXT_ZERO_CONFIG:
901 assert(va == 0);
|
902 pkt->set(c0_config);
| 902 pkt->setBE(c0_config);
|
903 break;
904 case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0:
905 assert(va == 0);
| 903 break;
904 case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0:
905 assert(va == 0);
|
906 pkt->set(itb->c0_tsb_ps0);
| 906 pkt->setBE(itb->c0_tsb_ps0);
|
907 break;
908 case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1:
909 assert(va == 0);
| 907 break;
908 case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1:
909 assert(va == 0);
|
910 pkt->set(itb->c0_tsb_ps1);
| 910 pkt->setBE(itb->c0_tsb_ps1);
|
911 break;
912 case ASI_IMMU_CTXT_ZERO_CONFIG:
913 assert(va == 0);
| 911 break;
912 case ASI_IMMU_CTXT_ZERO_CONFIG:
913 assert(va == 0);
|
914 pkt->set(itb->c0_config);
| 914 pkt->setBE(itb->c0_config);
|
915 break;
916 case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0:
917 assert(va == 0);
| 915 break;
916 case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0:
917 assert(va == 0);
|
918 pkt->set(cx_tsb_ps0);
| 918 pkt->setBE(cx_tsb_ps0);
|
919 break;
920 case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1:
921 assert(va == 0);
| 919 break;
920 case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1:
921 assert(va == 0);
|
922 pkt->set(cx_tsb_ps1);
| 922 pkt->setBE(cx_tsb_ps1);
|
923 break;
924 case ASI_DMMU_CTXT_NONZERO_CONFIG:
925 assert(va == 0);
| 923 break;
924 case ASI_DMMU_CTXT_NONZERO_CONFIG:
925 assert(va == 0);
|
926 pkt->set(cx_config);
| 926 pkt->setBE(cx_config);
|
927 break;
928 case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0:
929 assert(va == 0);
| 927 break;
928 case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0:
929 assert(va == 0);
|
930 pkt->set(itb->cx_tsb_ps0);
| 930 pkt->setBE(itb->cx_tsb_ps0);
|
931 break;
932 case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1:
933 assert(va == 0);
| 931 break;
932 case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1:
933 assert(va == 0);
|
934 pkt->set(itb->cx_tsb_ps1);
| 934 pkt->setBE(itb->cx_tsb_ps1);
|
935 break;
936 case ASI_IMMU_CTXT_NONZERO_CONFIG:
937 assert(va == 0);
| 935 break;
936 case ASI_IMMU_CTXT_NONZERO_CONFIG:
937 assert(va == 0);
|
938 pkt->set(itb->cx_config);
| 938 pkt->setBE(itb->cx_config);
|
939 break;
940 case ASI_SPARC_ERROR_STATUS_REG:
| 939 break;
940 case ASI_SPARC_ERROR_STATUS_REG:
|
941 pkt->set((uint64_t)0);
| 941 pkt->setBE((uint64_t)0);
|
942 break;
943 case ASI_HYP_SCRATCHPAD:
944 case ASI_SCRATCHPAD:
| 942 break;
943 case ASI_HYP_SCRATCHPAD:
944 case ASI_SCRATCHPAD:
|
945 pkt->set(tc->readMiscReg(MISCREG_SCRATCHPAD_R0 + (va >> 3)));
| 945 pkt->setBE(tc->readMiscReg(MISCREG_SCRATCHPAD_R0 + (va >> 3)));
|
946 break;
947 case ASI_IMMU:
948 switch (va) {
949 case 0x0:
950 temp = itb->tag_access;
| 946 break;
947 case ASI_IMMU:
948 switch (va) {
949 case 0x0:
950 temp = itb->tag_access;
|
951 pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48);
| 951 pkt->setBE(bits(temp,63,22) | bits(temp,12,0) << 48);
|
952 break;
953 case 0x18:
| 952 break;
953 case 0x18:
|
954 pkt->set(itb->sfsr);
| 954 pkt->setBE(itb->sfsr);
|
955 break;
956 case 0x30:
| 955 break;
956 case 0x30:
|
957 pkt->set(itb->tag_access);
| 957 pkt->setBE(itb->tag_access);
|
958 break;
959 default:
960 goto doMmuReadError;
961 }
962 break;
963 case ASI_DMMU:
964 switch (va) {
965 case 0x0:
966 temp = tag_access;
| 958 break;
959 default:
960 goto doMmuReadError;
961 }
962 break;
963 case ASI_DMMU:
964 switch (va) {
965 case 0x0:
966 temp = tag_access;
|
967 pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48);
| 967 pkt->setBE(bits(temp,63,22) | bits(temp,12,0) << 48);
|
968 break;
969 case 0x18:
| 968 break;
969 case 0x18:
|
970 pkt->set(sfsr);
| 970 pkt->setBE(sfsr);
|
971 break;
972 case 0x20:
| 971 break;
972 case 0x20:
|
973 pkt->set(sfar);
| 973 pkt->setBE(sfar);
|
974 break;
975 case 0x30:
| 974 break;
975 case 0x30:
|
976 pkt->set(tag_access);
| 976 pkt->setBE(tag_access);
|
977 break;
978 case 0x80:
| 977 break;
978 case 0x80:
|
979 pkt->set(tc->readMiscReg(MISCREG_MMU_PART_ID));
| 979 pkt->setBE(tc->readMiscReg(MISCREG_MMU_PART_ID));
|
980 break;
981 default:
982 goto doMmuReadError;
983 }
984 break;
985 case ASI_DMMU_TSB_PS0_PTR_REG:
| 980 break;
981 default:
982 goto doMmuReadError;
983 }
984 break;
985 case ASI_DMMU_TSB_PS0_PTR_REG:
|
986 pkt->set(MakeTsbPtr(Ps0,
| 986 pkt->setBE(MakeTsbPtr(Ps0,
|
987 tag_access,
988 c0_tsb_ps0,
989 c0_config,
990 cx_tsb_ps0,
991 cx_config));
992 break;
993 case ASI_DMMU_TSB_PS1_PTR_REG:
| 987 tag_access,
988 c0_tsb_ps0,
989 c0_config,
990 cx_tsb_ps0,
991 cx_config));
992 break;
993 case ASI_DMMU_TSB_PS1_PTR_REG:
|
994 pkt->set(MakeTsbPtr(Ps1,
| 994 pkt->setBE(MakeTsbPtr(Ps1,
|
995 tag_access,
996 c0_tsb_ps1,
997 c0_config,
998 cx_tsb_ps1,
999 cx_config));
1000 break;
1001 case ASI_IMMU_TSB_PS0_PTR_REG:
| 995 tag_access,
996 c0_tsb_ps1,
997 c0_config,
998 cx_tsb_ps1,
999 cx_config));
1000 break;
1001 case ASI_IMMU_TSB_PS0_PTR_REG:
|
1002 pkt->set(MakeTsbPtr(Ps0,
| 1002 pkt->setBE(MakeTsbPtr(Ps0,
|
1003 itb->tag_access,
1004 itb->c0_tsb_ps0,
1005 itb->c0_config,
1006 itb->cx_tsb_ps0,
1007 itb->cx_config));
1008 break;
1009 case ASI_IMMU_TSB_PS1_PTR_REG:
| 1003 itb->tag_access,
1004 itb->c0_tsb_ps0,
1005 itb->c0_config,
1006 itb->cx_tsb_ps0,
1007 itb->cx_config));
1008 break;
1009 case ASI_IMMU_TSB_PS1_PTR_REG:
|
1010 pkt->set(MakeTsbPtr(Ps1,
| 1010 pkt->setBE(MakeTsbPtr(Ps1,
|
1011 itb->tag_access,
1012 itb->c0_tsb_ps1,
1013 itb->c0_config,
1014 itb->cx_tsb_ps1,
1015 itb->cx_config));
1016 break;
1017 case ASI_SWVR_INTR_RECEIVE:
1018 {
1019 SparcISA::Interrupts * interrupts =
1020 dynamic_cast<SparcISA::Interrupts *>(
1021 tc->getCpuPtr()->getInterruptController(0));
| 1011 itb->tag_access,
1012 itb->c0_tsb_ps1,
1013 itb->c0_config,
1014 itb->cx_tsb_ps1,
1015 itb->cx_config));
1016 break;
1017 case ASI_SWVR_INTR_RECEIVE:
1018 {
1019 SparcISA::Interrupts * interrupts =
1020 dynamic_cast<SparcISA::Interrupts *>(
1021 tc->getCpuPtr()->getInterruptController(0));
|
1022 pkt->set(interrupts->get_vec(IT_INT_VEC));
| 1022 pkt->setBE(interrupts->get_vec(IT_INT_VEC));
|
1023 }
1024 break;
1025 case ASI_SWVR_UDB_INTR_R:
1026 {
1027 SparcISA::Interrupts * interrupts =
1028 dynamic_cast<SparcISA::Interrupts *>(
1029 tc->getCpuPtr()->getInterruptController(0));
1030 temp = findMsbSet(interrupts->get_vec(IT_INT_VEC));
1031 tc->getCpuPtr()->clearInterrupt(0, IT_INT_VEC, temp);
| 1023 }
1024 break;
1025 case ASI_SWVR_UDB_INTR_R:
1026 {
1027 SparcISA::Interrupts * interrupts =
1028 dynamic_cast<SparcISA::Interrupts *>(
1029 tc->getCpuPtr()->getInterruptController(0));
1030 temp = findMsbSet(interrupts->get_vec(IT_INT_VEC));
1031 tc->getCpuPtr()->clearInterrupt(0, IT_INT_VEC, temp);
|
1032 pkt->set(temp);
| 1032 pkt->setBE(temp);
|
1033 }
1034 break;
1035 default:
1036doMmuReadError:
1037 panic("need to impl DTB::doMmuRegRead() got asi=%#x, va=%#x\n",
1038 (uint32_t)asi, va);
1039 }
1040 pkt->makeAtomicResponse();
1041 return Cycles(1);
1042}
1043
1044Cycles
1045TLB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
1046{
| 1033 }
1034 break;
1035 default:
1036doMmuReadError:
1037 panic("need to impl DTB::doMmuRegRead() got asi=%#x, va=%#x\n",
1038 (uint32_t)asi, va);
1039 }
1040 pkt->makeAtomicResponse();
1041 return Cycles(1);
1042}
1043
1044Cycles
1045TLB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
1046{
|
1047 uint64_t data = pkt->get();
| 1047 uint64_t data = pkt->getBE<uint64_t>();
|
1048 Addr va = pkt->getAddr();
1049 ASI asi = (ASI)pkt->req->getArchFlags();
1050
1051 Addr ta_insert;
1052 Addr va_insert;
1053 Addr ct_insert;
1054 int part_insert;
1055 int entry_insert = -1;
1056 bool real_insert;
1057 bool ignore;
1058 int part_id;
1059 int ctx_id;
1060 PageTableEntry pte;
1061
1062 DPRINTF(IPR, "Memory Mapped IPR Write: asi=%#X a=%#x d=%#X\n",
1063 (uint32_t)asi, va, data);
1064
1065 TLB *itb = dynamic_cast<TLB *>(tc->getITBPtr());
1066
1067 switch (asi) {
1068 case ASI_LSU_CONTROL_REG:
1069 assert(va == 0);
1070 tc->setMiscReg(MISCREG_MMU_LSU_CTRL, data);
1071 break;
1072 case ASI_MMU:
1073 switch (va) {
1074 case 0x8:
1075 tc->setMiscReg(MISCREG_MMU_P_CONTEXT, data);
1076 break;
1077 case 0x10:
1078 tc->setMiscReg(MISCREG_MMU_S_CONTEXT, data);
1079 break;
1080 default:
1081 goto doMmuWriteError;
1082 }
1083 break;
1084 case ASI_QUEUE:
1085 assert(mbits(data,13,6) == data);
1086 tc->setMiscReg(MISCREG_QUEUE_CPU_MONDO_HEAD +
1087 (va >> 4) - 0x3c, data);
1088 break;
1089 case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0:
1090 assert(va == 0);
1091 c0_tsb_ps0 = data;
1092 break;
1093 case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1:
1094 assert(va == 0);
1095 c0_tsb_ps1 = data;
1096 break;
1097 case ASI_DMMU_CTXT_ZERO_CONFIG:
1098 assert(va == 0);
1099 c0_config = data;
1100 break;
1101 case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0:
1102 assert(va == 0);
1103 itb->c0_tsb_ps0 = data;
1104 break;
1105 case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1:
1106 assert(va == 0);
1107 itb->c0_tsb_ps1 = data;
1108 break;
1109 case ASI_IMMU_CTXT_ZERO_CONFIG:
1110 assert(va == 0);
1111 itb->c0_config = data;
1112 break;
1113 case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0:
1114 assert(va == 0);
1115 cx_tsb_ps0 = data;
1116 break;
1117 case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1:
1118 assert(va == 0);
1119 cx_tsb_ps1 = data;
1120 break;
1121 case ASI_DMMU_CTXT_NONZERO_CONFIG:
1122 assert(va == 0);
1123 cx_config = data;
1124 break;
1125 case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0:
1126 assert(va == 0);
1127 itb->cx_tsb_ps0 = data;
1128 break;
1129 case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1:
1130 assert(va == 0);
1131 itb->cx_tsb_ps1 = data;
1132 break;
1133 case ASI_IMMU_CTXT_NONZERO_CONFIG:
1134 assert(va == 0);
1135 itb->cx_config = data;
1136 break;
1137 case ASI_SPARC_ERROR_EN_REG:
1138 case ASI_SPARC_ERROR_STATUS_REG:
1139 inform("Ignoring write to SPARC ERROR regsiter\n");
1140 break;
1141 case ASI_HYP_SCRATCHPAD:
1142 case ASI_SCRATCHPAD:
1143 tc->setMiscReg(MISCREG_SCRATCHPAD_R0 + (va >> 3), data);
1144 break;
1145 case ASI_IMMU:
1146 switch (va) {
1147 case 0x18:
1148 itb->sfsr = data;
1149 break;
1150 case 0x30:
1151 sext<59>(bits(data, 59,0));
1152 itb->tag_access = data;
1153 break;
1154 default:
1155 goto doMmuWriteError;
1156 }
1157 break;
1158 case ASI_ITLB_DATA_ACCESS_REG:
1159 entry_insert = bits(va, 8,3);
1160 M5_FALLTHROUGH;
1161 case ASI_ITLB_DATA_IN_REG:
1162 assert(entry_insert != -1 || mbits(va,10,9) == va);
1163 ta_insert = itb->tag_access;
1164 va_insert = mbits(ta_insert, 63,13);
1165 ct_insert = mbits(ta_insert, 12,0);
1166 part_insert = tc->readMiscReg(MISCREG_MMU_PART_ID);
1167 real_insert = bits(va, 9,9);
1168 pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v :
1169 PageTableEntry::sun4u);
1170 itb->insert(va_insert, part_insert, ct_insert, real_insert,
1171 pte, entry_insert);
1172 break;
1173 case ASI_DTLB_DATA_ACCESS_REG:
1174 entry_insert = bits(va, 8,3);
1175 M5_FALLTHROUGH;
1176 case ASI_DTLB_DATA_IN_REG:
1177 assert(entry_insert != -1 || mbits(va,10,9) == va);
1178 ta_insert = tag_access;
1179 va_insert = mbits(ta_insert, 63,13);
1180 ct_insert = mbits(ta_insert, 12,0);
1181 part_insert = tc->readMiscReg(MISCREG_MMU_PART_ID);
1182 real_insert = bits(va, 9,9);
1183 pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v :
1184 PageTableEntry::sun4u);
1185 insert(va_insert, part_insert, ct_insert, real_insert, pte,
1186 entry_insert);
1187 break;
1188 case ASI_IMMU_DEMAP:
1189 ignore = false;
1190 ctx_id = -1;
1191 part_id = tc->readMiscReg(MISCREG_MMU_PART_ID);
1192 switch (bits(va,5,4)) {
1193 case 0:
1194 ctx_id = tc->readMiscReg(MISCREG_MMU_P_CONTEXT);
1195 break;
1196 case 1:
1197 ignore = true;
1198 break;
1199 case 3:
1200 ctx_id = 0;
1201 break;
1202 default:
1203 ignore = true;
1204 }
1205
1206 switch (bits(va,7,6)) {
1207 case 0: // demap page
1208 if (!ignore)
1209 itb->demapPage(mbits(va,63,13), part_id, bits(va,9,9), ctx_id);
1210 break;
1211 case 1: // demap context
1212 if (!ignore)
1213 itb->demapContext(part_id, ctx_id);
1214 break;
1215 case 2:
1216 itb->demapAll(part_id);
1217 break;
1218 default:
1219 panic("Invalid type for IMMU demap\n");
1220 }
1221 break;
1222 case ASI_DMMU:
1223 switch (va) {
1224 case 0x18:
1225 sfsr = data;
1226 break;
1227 case 0x30:
1228 sext<59>(bits(data, 59,0));
1229 tag_access = data;
1230 break;
1231 case 0x80:
1232 tc->setMiscReg(MISCREG_MMU_PART_ID, data);
1233 break;
1234 default:
1235 goto doMmuWriteError;
1236 }
1237 break;
1238 case ASI_DMMU_DEMAP:
1239 ignore = false;
1240 ctx_id = -1;
1241 part_id = tc->readMiscReg(MISCREG_MMU_PART_ID);
1242 switch (bits(va,5,4)) {
1243 case 0:
1244 ctx_id = tc->readMiscReg(MISCREG_MMU_P_CONTEXT);
1245 break;
1246 case 1:
1247 ctx_id = tc->readMiscReg(MISCREG_MMU_S_CONTEXT);
1248 break;
1249 case 3:
1250 ctx_id = 0;
1251 break;
1252 default:
1253 ignore = true;
1254 }
1255
1256 switch (bits(va,7,6)) {
1257 case 0: // demap page
1258 if (!ignore)
1259 demapPage(mbits(va,63,13), part_id, bits(va,9,9), ctx_id);
1260 break;
1261 case 1: // demap context
1262 if (!ignore)
1263 demapContext(part_id, ctx_id);
1264 break;
1265 case 2:
1266 demapAll(part_id);
1267 break;
1268 default:
1269 panic("Invalid type for IMMU demap\n");
1270 }
1271 break;
1272 case ASI_SWVR_INTR_RECEIVE:
1273 {
1274 int msb;
1275 // clear all the interrupts that aren't set in the write
1276 SparcISA::Interrupts * interrupts =
1277 dynamic_cast<SparcISA::Interrupts *>(
1278 tc->getCpuPtr()->getInterruptController(0));
1279 while (interrupts->get_vec(IT_INT_VEC) & data) {
1280 msb = findMsbSet(interrupts->get_vec(IT_INT_VEC) & data);
1281 tc->getCpuPtr()->clearInterrupt(0, IT_INT_VEC, msb);
1282 }
1283 }
1284 break;
1285 case ASI_SWVR_UDB_INTR_W:
1286 tc->getSystemPtr()->threadContexts[bits(data,12,8)]->getCpuPtr()->
1287 postInterrupt(0, bits(data, 5, 0), 0);
1288 break;
1289 default:
1290doMmuWriteError:
1291 panic("need to impl DTB::doMmuRegWrite() got asi=%#x, va=%#x d=%#x\n",
1292 (uint32_t)pkt->req->getArchFlags(), pkt->getAddr(), data);
1293 }
1294 pkt->makeAtomicResponse();
1295 return Cycles(1);
1296}
1297
1298void
1299TLB::GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs)
1300{
1301 uint64_t tag_access = mbits(addr,63,13) | mbits(ctx,12,0);
1302 TLB *itb = dynamic_cast<TLB *>(tc->getITBPtr());
1303 ptrs[0] = MakeTsbPtr(Ps0, tag_access,
1304 c0_tsb_ps0,
1305 c0_config,
1306 cx_tsb_ps0,
1307 cx_config);
1308 ptrs[1] = MakeTsbPtr(Ps1, tag_access,
1309 c0_tsb_ps1,
1310 c0_config,
1311 cx_tsb_ps1,
1312 cx_config);
1313 ptrs[2] = MakeTsbPtr(Ps0, tag_access,
1314 itb->c0_tsb_ps0,
1315 itb->c0_config,
1316 itb->cx_tsb_ps0,
1317 itb->cx_config);
1318 ptrs[3] = MakeTsbPtr(Ps1, tag_access,
1319 itb->c0_tsb_ps1,
1320 itb->c0_config,
1321 itb->cx_tsb_ps1,
1322 itb->cx_config);
1323}
1324
1325uint64_t
1326TLB::MakeTsbPtr(TsbPageSize ps, uint64_t tag_access, uint64_t c0_tsb,
1327 uint64_t c0_config, uint64_t cX_tsb, uint64_t cX_config)
1328{
1329 uint64_t tsb;
1330 uint64_t config;
1331
1332 if (bits(tag_access, 12,0) == 0) {
1333 tsb = c0_tsb;
1334 config = c0_config;
1335 } else {
1336 tsb = cX_tsb;
1337 config = cX_config;
1338 }
1339
1340 uint64_t ptr = mbits(tsb,63,13);
1341 bool split = bits(tsb,12,12);
1342 int tsb_size = bits(tsb,3,0);
1343 int page_size = (ps == Ps0) ? bits(config, 2,0) : bits(config,10,8);
1344
1345 if (ps == Ps1 && split)
1346 ptr |= ULL(1) << (13 + tsb_size);
1347 ptr |= (tag_access >> (9 + page_size * 3)) & mask(12+tsb_size, 4);
1348
1349 return ptr;
1350}
1351
1352void
1353TLB::serialize(CheckpointOut &cp) const
1354{
1355 SERIALIZE_SCALAR(size);
1356 SERIALIZE_SCALAR(usedEntries);
1357 SERIALIZE_SCALAR(lastReplaced);
1358
1359 // convert the pointer based free list into an index based one
1360 std::vector<int> free_list;
1361 for (const TlbEntry *entry : freeList)
1362 free_list.push_back(entry - tlb);
1363
1364 SERIALIZE_CONTAINER(free_list);
1365
1366 SERIALIZE_SCALAR(c0_tsb_ps0);
1367 SERIALIZE_SCALAR(c0_tsb_ps1);
1368 SERIALIZE_SCALAR(c0_config);
1369 SERIALIZE_SCALAR(cx_tsb_ps0);
1370 SERIALIZE_SCALAR(cx_tsb_ps1);
1371 SERIALIZE_SCALAR(cx_config);
1372 SERIALIZE_SCALAR(sfsr);
1373 SERIALIZE_SCALAR(tag_access);
1374 SERIALIZE_SCALAR(sfar);
1375
1376 for (int x = 0; x < size; x++) {
1377 ScopedCheckpointSection sec(cp, csprintf("PTE%d", x));
1378 tlb[x].serialize(cp);
1379 }
1380}
1381
1382void
1383TLB::unserialize(CheckpointIn &cp)
1384{
1385 int oldSize;
1386
1387 paramIn(cp, "size", oldSize);
1388 if (oldSize != size)
1389 panic("Don't support unserializing different sized TLBs\n");
1390 UNSERIALIZE_SCALAR(usedEntries);
1391 UNSERIALIZE_SCALAR(lastReplaced);
1392
1393 std::vector<int> free_list;
1394 UNSERIALIZE_CONTAINER(free_list);
1395 freeList.clear();
1396 for (int idx : free_list)
1397 freeList.push_back(&tlb[idx]);
1398
1399 UNSERIALIZE_SCALAR(c0_tsb_ps0);
1400 UNSERIALIZE_SCALAR(c0_tsb_ps1);
1401 UNSERIALIZE_SCALAR(c0_config);
1402 UNSERIALIZE_SCALAR(cx_tsb_ps0);
1403 UNSERIALIZE_SCALAR(cx_tsb_ps1);
1404 UNSERIALIZE_SCALAR(cx_config);
1405 UNSERIALIZE_SCALAR(sfsr);
1406 UNSERIALIZE_SCALAR(tag_access);
1407
1408 lookupTable.clear();
1409 for (int x = 0; x < size; x++) {
1410 ScopedCheckpointSection sec(cp, csprintf("PTE%d", x));
1411 tlb[x].unserialize(cp);
1412 if (tlb[x].valid)
1413 lookupTable.insert(tlb[x].range, &tlb[x]);
1414
1415 }
1416 UNSERIALIZE_SCALAR(sfar);
1417}
1418
1419} // namespace SparcISA
1420
1421SparcISA::TLB *
1422SparcTLBParams::create()
1423{
1424 return new SparcISA::TLB(this);
1425}
| 1048 Addr va = pkt->getAddr();
1049 ASI asi = (ASI)pkt->req->getArchFlags();
1050
1051 Addr ta_insert;
1052 Addr va_insert;
1053 Addr ct_insert;
1054 int part_insert;
1055 int entry_insert = -1;
1056 bool real_insert;
1057 bool ignore;
1058 int part_id;
1059 int ctx_id;
1060 PageTableEntry pte;
1061
1062 DPRINTF(IPR, "Memory Mapped IPR Write: asi=%#X a=%#x d=%#X\n",
1063 (uint32_t)asi, va, data);
1064
1065 TLB *itb = dynamic_cast<TLB *>(tc->getITBPtr());
1066
1067 switch (asi) {
1068 case ASI_LSU_CONTROL_REG:
1069 assert(va == 0);
1070 tc->setMiscReg(MISCREG_MMU_LSU_CTRL, data);
1071 break;
1072 case ASI_MMU:
1073 switch (va) {
1074 case 0x8:
1075 tc->setMiscReg(MISCREG_MMU_P_CONTEXT, data);
1076 break;
1077 case 0x10:
1078 tc->setMiscReg(MISCREG_MMU_S_CONTEXT, data);
1079 break;
1080 default:
1081 goto doMmuWriteError;
1082 }
1083 break;
1084 case ASI_QUEUE:
1085 assert(mbits(data,13,6) == data);
1086 tc->setMiscReg(MISCREG_QUEUE_CPU_MONDO_HEAD +
1087 (va >> 4) - 0x3c, data);
1088 break;
1089 case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0:
1090 assert(va == 0);
1091 c0_tsb_ps0 = data;
1092 break;
1093 case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1:
1094 assert(va == 0);
1095 c0_tsb_ps1 = data;
1096 break;
1097 case ASI_DMMU_CTXT_ZERO_CONFIG:
1098 assert(va == 0);
1099 c0_config = data;
1100 break;
1101 case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0:
1102 assert(va == 0);
1103 itb->c0_tsb_ps0 = data;
1104 break;
1105 case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1:
1106 assert(va == 0);
1107 itb->c0_tsb_ps1 = data;
1108 break;
1109 case ASI_IMMU_CTXT_ZERO_CONFIG:
1110 assert(va == 0);
1111 itb->c0_config = data;
1112 break;
1113 case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0:
1114 assert(va == 0);
1115 cx_tsb_ps0 = data;
1116 break;
1117 case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1:
1118 assert(va == 0);
1119 cx_tsb_ps1 = data;
1120 break;
1121 case ASI_DMMU_CTXT_NONZERO_CONFIG:
1122 assert(va == 0);
1123 cx_config = data;
1124 break;
1125 case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0:
1126 assert(va == 0);
1127 itb->cx_tsb_ps0 = data;
1128 break;
1129 case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1:
1130 assert(va == 0);
1131 itb->cx_tsb_ps1 = data;
1132 break;
1133 case ASI_IMMU_CTXT_NONZERO_CONFIG:
1134 assert(va == 0);
1135 itb->cx_config = data;
1136 break;
1137 case ASI_SPARC_ERROR_EN_REG:
1138 case ASI_SPARC_ERROR_STATUS_REG:
1139 inform("Ignoring write to SPARC ERROR regsiter\n");
1140 break;
1141 case ASI_HYP_SCRATCHPAD:
1142 case ASI_SCRATCHPAD:
1143 tc->setMiscReg(MISCREG_SCRATCHPAD_R0 + (va >> 3), data);
1144 break;
1145 case ASI_IMMU:
1146 switch (va) {
1147 case 0x18:
1148 itb->sfsr = data;
1149 break;
1150 case 0x30:
1151 sext<59>(bits(data, 59,0));
1152 itb->tag_access = data;
1153 break;
1154 default:
1155 goto doMmuWriteError;
1156 }
1157 break;
1158 case ASI_ITLB_DATA_ACCESS_REG:
1159 entry_insert = bits(va, 8,3);
1160 M5_FALLTHROUGH;
1161 case ASI_ITLB_DATA_IN_REG:
1162 assert(entry_insert != -1 || mbits(va,10,9) == va);
1163 ta_insert = itb->tag_access;
1164 va_insert = mbits(ta_insert, 63,13);
1165 ct_insert = mbits(ta_insert, 12,0);
1166 part_insert = tc->readMiscReg(MISCREG_MMU_PART_ID);
1167 real_insert = bits(va, 9,9);
1168 pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v :
1169 PageTableEntry::sun4u);
1170 itb->insert(va_insert, part_insert, ct_insert, real_insert,
1171 pte, entry_insert);
1172 break;
1173 case ASI_DTLB_DATA_ACCESS_REG:
1174 entry_insert = bits(va, 8,3);
1175 M5_FALLTHROUGH;
1176 case ASI_DTLB_DATA_IN_REG:
1177 assert(entry_insert != -1 || mbits(va,10,9) == va);
1178 ta_insert = tag_access;
1179 va_insert = mbits(ta_insert, 63,13);
1180 ct_insert = mbits(ta_insert, 12,0);
1181 part_insert = tc->readMiscReg(MISCREG_MMU_PART_ID);
1182 real_insert = bits(va, 9,9);
1183 pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v :
1184 PageTableEntry::sun4u);
1185 insert(va_insert, part_insert, ct_insert, real_insert, pte,
1186 entry_insert);
1187 break;
1188 case ASI_IMMU_DEMAP:
1189 ignore = false;
1190 ctx_id = -1;
1191 part_id = tc->readMiscReg(MISCREG_MMU_PART_ID);
1192 switch (bits(va,5,4)) {
1193 case 0:
1194 ctx_id = tc->readMiscReg(MISCREG_MMU_P_CONTEXT);
1195 break;
1196 case 1:
1197 ignore = true;
1198 break;
1199 case 3:
1200 ctx_id = 0;
1201 break;
1202 default:
1203 ignore = true;
1204 }
1205
1206 switch (bits(va,7,6)) {
1207 case 0: // demap page
1208 if (!ignore)
1209 itb->demapPage(mbits(va,63,13), part_id, bits(va,9,9), ctx_id);
1210 break;
1211 case 1: // demap context
1212 if (!ignore)
1213 itb->demapContext(part_id, ctx_id);
1214 break;
1215 case 2:
1216 itb->demapAll(part_id);
1217 break;
1218 default:
1219 panic("Invalid type for IMMU demap\n");
1220 }
1221 break;
1222 case ASI_DMMU:
1223 switch (va) {
1224 case 0x18:
1225 sfsr = data;
1226 break;
1227 case 0x30:
1228 sext<59>(bits(data, 59,0));
1229 tag_access = data;
1230 break;
1231 case 0x80:
1232 tc->setMiscReg(MISCREG_MMU_PART_ID, data);
1233 break;
1234 default:
1235 goto doMmuWriteError;
1236 }
1237 break;
1238 case ASI_DMMU_DEMAP:
1239 ignore = false;
1240 ctx_id = -1;
1241 part_id = tc->readMiscReg(MISCREG_MMU_PART_ID);
1242 switch (bits(va,5,4)) {
1243 case 0:
1244 ctx_id = tc->readMiscReg(MISCREG_MMU_P_CONTEXT);
1245 break;
1246 case 1:
1247 ctx_id = tc->readMiscReg(MISCREG_MMU_S_CONTEXT);
1248 break;
1249 case 3:
1250 ctx_id = 0;
1251 break;
1252 default:
1253 ignore = true;
1254 }
1255
1256 switch (bits(va,7,6)) {
1257 case 0: // demap page
1258 if (!ignore)
1259 demapPage(mbits(va,63,13), part_id, bits(va,9,9), ctx_id);
1260 break;
1261 case 1: // demap context
1262 if (!ignore)
1263 demapContext(part_id, ctx_id);
1264 break;
1265 case 2:
1266 demapAll(part_id);
1267 break;
1268 default:
1269 panic("Invalid type for IMMU demap\n");
1270 }
1271 break;
1272 case ASI_SWVR_INTR_RECEIVE:
1273 {
1274 int msb;
1275 // clear all the interrupts that aren't set in the write
1276 SparcISA::Interrupts * interrupts =
1277 dynamic_cast<SparcISA::Interrupts *>(
1278 tc->getCpuPtr()->getInterruptController(0));
1279 while (interrupts->get_vec(IT_INT_VEC) & data) {
1280 msb = findMsbSet(interrupts->get_vec(IT_INT_VEC) & data);
1281 tc->getCpuPtr()->clearInterrupt(0, IT_INT_VEC, msb);
1282 }
1283 }
1284 break;
1285 case ASI_SWVR_UDB_INTR_W:
1286 tc->getSystemPtr()->threadContexts[bits(data,12,8)]->getCpuPtr()->
1287 postInterrupt(0, bits(data, 5, 0), 0);
1288 break;
1289 default:
1290doMmuWriteError:
1291 panic("need to impl DTB::doMmuRegWrite() got asi=%#x, va=%#x d=%#x\n",
1292 (uint32_t)pkt->req->getArchFlags(), pkt->getAddr(), data);
1293 }
1294 pkt->makeAtomicResponse();
1295 return Cycles(1);
1296}
1297
1298void
1299TLB::GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs)
1300{
1301 uint64_t tag_access = mbits(addr,63,13) | mbits(ctx,12,0);
1302 TLB *itb = dynamic_cast<TLB *>(tc->getITBPtr());
1303 ptrs[0] = MakeTsbPtr(Ps0, tag_access,
1304 c0_tsb_ps0,
1305 c0_config,
1306 cx_tsb_ps0,
1307 cx_config);
1308 ptrs[1] = MakeTsbPtr(Ps1, tag_access,
1309 c0_tsb_ps1,
1310 c0_config,
1311 cx_tsb_ps1,
1312 cx_config);
1313 ptrs[2] = MakeTsbPtr(Ps0, tag_access,
1314 itb->c0_tsb_ps0,
1315 itb->c0_config,
1316 itb->cx_tsb_ps0,
1317 itb->cx_config);
1318 ptrs[3] = MakeTsbPtr(Ps1, tag_access,
1319 itb->c0_tsb_ps1,
1320 itb->c0_config,
1321 itb->cx_tsb_ps1,
1322 itb->cx_config);
1323}
1324
1325uint64_t
1326TLB::MakeTsbPtr(TsbPageSize ps, uint64_t tag_access, uint64_t c0_tsb,
1327 uint64_t c0_config, uint64_t cX_tsb, uint64_t cX_config)
1328{
1329 uint64_t tsb;
1330 uint64_t config;
1331
1332 if (bits(tag_access, 12,0) == 0) {
1333 tsb = c0_tsb;
1334 config = c0_config;
1335 } else {
1336 tsb = cX_tsb;
1337 config = cX_config;
1338 }
1339
1340 uint64_t ptr = mbits(tsb,63,13);
1341 bool split = bits(tsb,12,12);
1342 int tsb_size = bits(tsb,3,0);
1343 int page_size = (ps == Ps0) ? bits(config, 2,0) : bits(config,10,8);
1344
1345 if (ps == Ps1 && split)
1346 ptr |= ULL(1) << (13 + tsb_size);
1347 ptr |= (tag_access >> (9 + page_size * 3)) & mask(12+tsb_size, 4);
1348
1349 return ptr;
1350}
1351
1352void
1353TLB::serialize(CheckpointOut &cp) const
1354{
1355 SERIALIZE_SCALAR(size);
1356 SERIALIZE_SCALAR(usedEntries);
1357 SERIALIZE_SCALAR(lastReplaced);
1358
1359 // convert the pointer based free list into an index based one
1360 std::vector<int> free_list;
1361 for (const TlbEntry *entry : freeList)
1362 free_list.push_back(entry - tlb);
1363
1364 SERIALIZE_CONTAINER(free_list);
1365
1366 SERIALIZE_SCALAR(c0_tsb_ps0);
1367 SERIALIZE_SCALAR(c0_tsb_ps1);
1368 SERIALIZE_SCALAR(c0_config);
1369 SERIALIZE_SCALAR(cx_tsb_ps0);
1370 SERIALIZE_SCALAR(cx_tsb_ps1);
1371 SERIALIZE_SCALAR(cx_config);
1372 SERIALIZE_SCALAR(sfsr);
1373 SERIALIZE_SCALAR(tag_access);
1374 SERIALIZE_SCALAR(sfar);
1375
1376 for (int x = 0; x < size; x++) {
1377 ScopedCheckpointSection sec(cp, csprintf("PTE%d", x));
1378 tlb[x].serialize(cp);
1379 }
1380}
1381
1382void
1383TLB::unserialize(CheckpointIn &cp)
1384{
1385 int oldSize;
1386
1387 paramIn(cp, "size", oldSize);
1388 if (oldSize != size)
1389 panic("Don't support unserializing different sized TLBs\n");
1390 UNSERIALIZE_SCALAR(usedEntries);
1391 UNSERIALIZE_SCALAR(lastReplaced);
1392
1393 std::vector<int> free_list;
1394 UNSERIALIZE_CONTAINER(free_list);
1395 freeList.clear();
1396 for (int idx : free_list)
1397 freeList.push_back(&tlb[idx]);
1398
1399 UNSERIALIZE_SCALAR(c0_tsb_ps0);
1400 UNSERIALIZE_SCALAR(c0_tsb_ps1);
1401 UNSERIALIZE_SCALAR(c0_config);
1402 UNSERIALIZE_SCALAR(cx_tsb_ps0);
1403 UNSERIALIZE_SCALAR(cx_tsb_ps1);
1404 UNSERIALIZE_SCALAR(cx_config);
1405 UNSERIALIZE_SCALAR(sfsr);
1406 UNSERIALIZE_SCALAR(tag_access);
1407
1408 lookupTable.clear();
1409 for (int x = 0; x < size; x++) {
1410 ScopedCheckpointSection sec(cp, csprintf("PTE%d", x));
1411 tlb[x].unserialize(cp);
1412 if (tlb[x].valid)
1413 lookupTable.insert(tlb[x].range, &tlb[x]);
1414
1415 }
1416 UNSERIALIZE_SCALAR(sfar);
1417}
1418
1419} // namespace SparcISA
1420
1421SparcISA::TLB *
1422SparcTLBParams::create()
1423{
1424 return new SparcISA::TLB(this);
1425}
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