39#include "base/trace.hh"
40#include "cpu/base.hh"
41#include "cpu/thread_context.hh"
42#include "debug/IPR.hh"
43#include "debug/TLB.hh"
44#include "mem/packet_access.hh"
45#include "mem/request.hh"
46#include "sim/full_system.hh"
47#include "sim/system.hh"
48
49/* @todo remove some of the magic constants. -- ali
50 * */
51namespace SparcISA {
52
53TLB::TLB(const Params *p)
54 : BaseTLB(p), size(p->size), usedEntries(0), lastReplaced(0),
55 cacheState(0), cacheValid(false)
56{
57 // To make this work you'll have to change the hypervisor and OS
58 if (size > 64)
59 fatal("SPARC T1 TLB registers don't support more than 64 TLB entries");
60
61 tlb = new TlbEntry[size];
62 std::memset(tlb, 0, sizeof(TlbEntry) * size);
63
64 for (int x = 0; x < size; x++)
65 freeList.push_back(&tlb[x]);
66
67 c0_tsb_ps0 = 0;
68 c0_tsb_ps1 = 0;
69 c0_config = 0;
70 cx_tsb_ps0 = 0;
71 cx_tsb_ps1 = 0;
72 cx_config = 0;
73 sfsr = 0;
74 tag_access = 0;
75 sfar = 0;
76 cacheEntry[0] = NULL;
77 cacheEntry[1] = NULL;
78}
79
80void
81TLB::clearUsedBits()
82{
83 MapIter i;
84 for (i = lookupTable.begin(); i != lookupTable.end(); i++) {
85 TlbEntry *t = i->second;
86 if (!t->pte.locked()) {
87 t->used = false;
88 usedEntries--;
89 }
90 }
91}
92
93
94void
95TLB::insert(Addr va, int partition_id, int context_id, bool real,
96 const PageTableEntry& PTE, int entry)
97{
98 MapIter i;
99 TlbEntry *new_entry = NULL;
100// TlbRange tr;
101 int x;
102
103 cacheValid = false;
104 va &= ~(PTE.size()-1);
105 /* tr.va = va;
106 tr.size = PTE.size() - 1;
107 tr.contextId = context_id;
108 tr.partitionId = partition_id;
109 tr.real = real;
110*/
111
112 DPRINTF(TLB,
113 "TLB: Inserting Entry; va=%#x pa=%#x pid=%d cid=%d r=%d entryid=%d\n",
114 va, PTE.paddr(), partition_id, context_id, (int)real, entry);
115
116 // Demap any entry that conflicts
117 for (x = 0; x < size; x++) {
118 if (tlb[x].range.real == real &&
119 tlb[x].range.partitionId == partition_id &&
120 tlb[x].range.va < va + PTE.size() - 1 &&
121 tlb[x].range.va + tlb[x].range.size >= va &&
122 (real || tlb[x].range.contextId == context_id ))
123 {
124 if (tlb[x].valid) {
125 freeList.push_front(&tlb[x]);
126 DPRINTF(TLB, "TLB: Conflicting entry %#X , deleting it\n", x);
127
128 tlb[x].valid = false;
129 if (tlb[x].used) {
130 tlb[x].used = false;
131 usedEntries--;
132 }
133 lookupTable.erase(tlb[x].range);
134 }
135 }
136 }
137
138 if (entry != -1) {
139 assert(entry < size && entry >= 0);
140 new_entry = &tlb[entry];
141 } else {
142 if (!freeList.empty()) {
143 new_entry = freeList.front();
144 } else {
145 x = lastReplaced;
146 do {
147 ++x;
148 if (x == size)
149 x = 0;
150 if (x == lastReplaced)
151 goto insertAllLocked;
152 } while (tlb[x].pte.locked());
153 lastReplaced = x;
154 new_entry = &tlb[x];
155 }
156 }
157
158insertAllLocked:
159 // Update the last ently if their all locked
160 if (!new_entry) {
161 new_entry = &tlb[size-1];
162 }
163
164 freeList.remove(new_entry);
165 if (new_entry->valid && new_entry->used)
166 usedEntries--;
167 if (new_entry->valid)
168 lookupTable.erase(new_entry->range);
169
170
171 assert(PTE.valid());
172 new_entry->range.va = va;
173 new_entry->range.size = PTE.size() - 1;
174 new_entry->range.partitionId = partition_id;
175 new_entry->range.contextId = context_id;
176 new_entry->range.real = real;
177 new_entry->pte = PTE;
178 new_entry->used = true;;
179 new_entry->valid = true;
180 usedEntries++;
181
182 i = lookupTable.insert(new_entry->range, new_entry);
183 assert(i != lookupTable.end());
184
185 // If all entries have their used bit set, clear it on them all,
186 // but the one we just inserted
187 if (usedEntries == size) {
188 clearUsedBits();
189 new_entry->used = true;
190 usedEntries++;
191 }
192}
193
194
195TlbEntry*
196TLB::lookup(Addr va, int partition_id, bool real, int context_id,
197 bool update_used)
198{
199 MapIter i;
200 TlbRange tr;
201 TlbEntry *t;
202
203 DPRINTF(TLB, "TLB: Looking up entry va=%#x pid=%d cid=%d r=%d\n",
204 va, partition_id, context_id, real);
205 // Assemble full address structure
206 tr.va = va;
207 tr.size = 1;
208 tr.contextId = context_id;
209 tr.partitionId = partition_id;
210 tr.real = real;
211
212 // Try to find the entry
213 i = lookupTable.find(tr);
214 if (i == lookupTable.end()) {
215 DPRINTF(TLB, "TLB: No valid entry found\n");
216 return NULL;
217 }
218
219 // Mark the entries used bit and clear other used bits in needed
220 t = i->second;
221 DPRINTF(TLB, "TLB: Valid entry found pa: %#x size: %#x\n", t->pte.paddr(),
222 t->pte.size());
223
224 // Update the used bits only if this is a real access (not a fake
225 // one from virttophys()
226 if (!t->used && update_used) {
227 t->used = true;
228 usedEntries++;
229 if (usedEntries == size) {
230 clearUsedBits();
231 t->used = true;
232 usedEntries++;
233 }
234 }
235
236 return t;
237}
238
239void
240TLB::dumpAll()
241{
242 MapIter i;
243 for (int x = 0; x < size; x++) {
244 if (tlb[x].valid) {
245 DPRINTFN("%4d: %#2x:%#2x %c %#4x %#8x %#8x %#16x\n",
246 x, tlb[x].range.partitionId, tlb[x].range.contextId,
247 tlb[x].range.real ? 'R' : ' ', tlb[x].range.size,
248 tlb[x].range.va, tlb[x].pte.paddr(), tlb[x].pte());
249 }
250 }
251}
252
253void
254TLB::demapPage(Addr va, int partition_id, bool real, int context_id)
255{
256 TlbRange tr;
257 MapIter i;
258
259 DPRINTF(IPR, "TLB: Demapping Page va=%#x pid=%#d cid=%d r=%d\n",
260 va, partition_id, context_id, real);
261
262 cacheValid = false;
263
264 // Assemble full address structure
265 tr.va = va;
266 tr.size = 1;
267 tr.contextId = context_id;
268 tr.partitionId = partition_id;
269 tr.real = real;
270
271 // Demap any entry that conflicts
272 i = lookupTable.find(tr);
273 if (i != lookupTable.end()) {
274 DPRINTF(IPR, "TLB: Demapped page\n");
275 i->second->valid = false;
276 if (i->second->used) {
277 i->second->used = false;
278 usedEntries--;
279 }
280 freeList.push_front(i->second);
281 lookupTable.erase(i);
282 }
283}
284
285void
286TLB::demapContext(int partition_id, int context_id)
287{
288 DPRINTF(IPR, "TLB: Demapping Context pid=%#d cid=%d\n",
289 partition_id, context_id);
290 cacheValid = false;
291 for (int x = 0; x < size; x++) {
292 if (tlb[x].range.contextId == context_id &&
293 tlb[x].range.partitionId == partition_id) {
294 if (tlb[x].valid) {
295 freeList.push_front(&tlb[x]);
296 }
297 tlb[x].valid = false;
298 if (tlb[x].used) {
299 tlb[x].used = false;
300 usedEntries--;
301 }
302 lookupTable.erase(tlb[x].range);
303 }
304 }
305}
306
307void
308TLB::demapAll(int partition_id)
309{
310 DPRINTF(TLB, "TLB: Demapping All pid=%#d\n", partition_id);
311 cacheValid = false;
312 for (int x = 0; x < size; x++) {
313 if (tlb[x].valid && !tlb[x].pte.locked() &&
314 tlb[x].range.partitionId == partition_id) {
315 freeList.push_front(&tlb[x]);
316 tlb[x].valid = false;
317 if (tlb[x].used) {
318 tlb[x].used = false;
319 usedEntries--;
320 }
321 lookupTable.erase(tlb[x].range);
322 }
323 }
324}
325
326void
327TLB::flushAll()
328{
329 cacheValid = false;
330 lookupTable.clear();
331
332 for (int x = 0; x < size; x++) {
333 if (tlb[x].valid)
334 freeList.push_back(&tlb[x]);
335 tlb[x].valid = false;
336 tlb[x].used = false;
337 }
338 usedEntries = 0;
339}
340
341uint64_t
342TLB::TteRead(int entry)
343{
344 if (entry >= size)
345 panic("entry: %d\n", entry);
346
347 assert(entry < size);
348 if (tlb[entry].valid)
349 return tlb[entry].pte();
350 else
351 return (uint64_t)-1ll;
352}
353
354uint64_t
355TLB::TagRead(int entry)
356{
357 assert(entry < size);
358 uint64_t tag;
359 if (!tlb[entry].valid)
360 return (uint64_t)-1ll;
361
362 tag = tlb[entry].range.contextId;
363 tag |= tlb[entry].range.va;
364 tag |= (uint64_t)tlb[entry].range.partitionId << 61;
365 tag |= tlb[entry].range.real ? ULL(1) << 60 : 0;
366 tag |= (uint64_t)~tlb[entry].pte._size() << 56;
367 return tag;
368}
369
370bool
371TLB::validVirtualAddress(Addr va, bool am)
372{
373 if (am)
374 return true;
375 if (va >= StartVAddrHole && va <= EndVAddrHole)
376 return false;
377 return true;
378}
379
380void
381TLB::writeSfsr(bool write, ContextType ct, bool se, FaultTypes ft, int asi)
382{
383 if (sfsr & 0x1)
384 sfsr = 0x3;
385 else
386 sfsr = 1;
387
388 if (write)
389 sfsr |= 1 << 2;
390 sfsr |= ct << 4;
391 if (se)
392 sfsr |= 1 << 6;
393 sfsr |= ft << 7;
394 sfsr |= asi << 16;
395}
396
397void
398TLB::writeTagAccess(Addr va, int context)
399{
400 DPRINTF(TLB, "TLB: Writing Tag Access: va: %#X ctx: %#X value: %#X\n",
401 va, context, mbits(va, 63,13) | mbits(context,12,0));
402
403 tag_access = mbits(va, 63,13) | mbits(context,12,0);
404}
405
406void
407TLB::writeSfsr(Addr a, bool write, ContextType ct,
408 bool se, FaultTypes ft, int asi)
409{
410 DPRINTF(TLB, "TLB: Fault: A=%#x w=%d ct=%d ft=%d asi=%d\n",
411 a, (int)write, ct, ft, asi);
412 TLB::writeSfsr(write, ct, se, ft, asi);
413 sfar = a;
414}
415
416Fault
417TLB::translateInst(RequestPtr req, ThreadContext *tc)
418{
419 uint64_t tlbdata = tc->readMiscRegNoEffect(MISCREG_TLB_DATA);
420
421 Addr vaddr = req->getVaddr();
422 TlbEntry *e;
423
424 assert(req->getArchFlags() == ASI_IMPLICIT);
425
426 DPRINTF(TLB, "TLB: ITB Request to translate va=%#x size=%d\n",
427 vaddr, req->getSize());
428
429 // Be fast if we can!
430 if (cacheValid && cacheState == tlbdata) {
431 if (cacheEntry[0]) {
432 if (cacheEntry[0]->range.va < vaddr + sizeof(MachInst) &&
433 cacheEntry[0]->range.va + cacheEntry[0]->range.size >= vaddr) {
434 req->setPaddr(cacheEntry[0]->pte.translate(vaddr));
435 return NoFault;
436 }
437 } else {
438 req->setPaddr(vaddr & PAddrImplMask);
439 return NoFault;
440 }
441 }
442
443 bool hpriv = bits(tlbdata,0,0);
444 bool red = bits(tlbdata,1,1);
445 bool priv = bits(tlbdata,2,2);
446 bool addr_mask = bits(tlbdata,3,3);
447 bool lsu_im = bits(tlbdata,4,4);
448
449 int part_id = bits(tlbdata,15,8);
450 int tl = bits(tlbdata,18,16);
451 int pri_context = bits(tlbdata,47,32);
452 int context;
453 ContextType ct;
454 int asi;
455 bool real = false;
456
457 DPRINTF(TLB, "TLB: priv:%d hpriv:%d red:%d lsuim:%d part_id: %#X\n",
458 priv, hpriv, red, lsu_im, part_id);
459
460 if (tl > 0) {
461 asi = ASI_N;
462 ct = Nucleus;
463 context = 0;
464 } else {
465 asi = ASI_P;
466 ct = Primary;
467 context = pri_context;
468 }
469
470 if ( hpriv || red ) {
471 cacheValid = true;
472 cacheState = tlbdata;
473 cacheEntry[0] = NULL;
474 req->setPaddr(vaddr & PAddrImplMask);
475 return NoFault;
476 }
477
478 // If the access is unaligned trap
479 if (vaddr & 0x3) {
480 writeSfsr(false, ct, false, OtherFault, asi);
481 return std::make_shared<MemAddressNotAligned>();
482 }
483
484 if (addr_mask)
485 vaddr = vaddr & VAddrAMask;
486
487 if (!validVirtualAddress(vaddr, addr_mask)) {
488 writeSfsr(false, ct, false, VaOutOfRange, asi);
489 return std::make_shared<InstructionAccessException>();
490 }
491
492 if (!lsu_im) {
493 e = lookup(vaddr, part_id, true);
494 real = true;
495 context = 0;
496 } else {
497 e = lookup(vaddr, part_id, false, context);
498 }
499
500 if (e == NULL || !e->valid) {
501 writeTagAccess(vaddr, context);
502 if (real) {
503 return std::make_shared<InstructionRealTranslationMiss>();
504 } else {
505 if (FullSystem)
506 return std::make_shared<FastInstructionAccessMMUMiss>();
507 else
508 return std::make_shared<FastInstructionAccessMMUMiss>(
509 req->getVaddr());
510 }
511 }
512
513 // were not priviledged accesing priv page
514 if (!priv && e->pte.priv()) {
515 writeTagAccess(vaddr, context);
516 writeSfsr(false, ct, false, PrivViolation, asi);
517 return std::make_shared<InstructionAccessException>();
518 }
519
520 // cache translation date for next translation
521 cacheValid = true;
522 cacheState = tlbdata;
523 cacheEntry[0] = e;
524
525 req->setPaddr(e->pte.translate(vaddr));
526 DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr());
527 return NoFault;
528}
529
530Fault
531TLB::translateData(RequestPtr req, ThreadContext *tc, bool write)
532{
533 /*
534 * @todo this could really use some profiling and fixing to make
535 * it faster!
536 */
537 uint64_t tlbdata = tc->readMiscRegNoEffect(MISCREG_TLB_DATA);
538 Addr vaddr = req->getVaddr();
539 Addr size = req->getSize();
540 ASI asi;
541 asi = (ASI)req->getArchFlags();
542 bool implicit = false;
543 bool hpriv = bits(tlbdata,0,0);
544 bool unaligned = vaddr & (size - 1);
545
546 DPRINTF(TLB, "TLB: DTB Request to translate va=%#x size=%d asi=%#x\n",
547 vaddr, size, asi);
548
549 if (lookupTable.size() != 64 - freeList.size())
550 panic("Lookup table size: %d tlb size: %d\n", lookupTable.size(),
551 freeList.size());
552 if (asi == ASI_IMPLICIT)
553 implicit = true;
554
555 // Only use the fast path here if there doesn't need to be an unaligned
556 // trap later
557 if (!unaligned) {
558 if (hpriv && implicit) {
559 req->setPaddr(vaddr & PAddrImplMask);
560 return NoFault;
561 }
562
563 // Be fast if we can!
564 if (cacheValid && cacheState == tlbdata) {
565
566
567
568 if (cacheEntry[0]) {
569 TlbEntry *ce = cacheEntry[0];
570 Addr ce_va = ce->range.va;
571 if (cacheAsi[0] == asi &&
572 ce_va < vaddr + size && ce_va + ce->range.size > vaddr &&
573 (!write || ce->pte.writable())) {
574 req->setPaddr(ce->pte.translate(vaddr));
575 if (ce->pte.sideffect() || (ce->pte.paddr() >> 39) & 1) {
576 req->setFlags(
577 Request::UNCACHEABLE | Request::STRICT_ORDER);
578 }
579 DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr());
580 return NoFault;
581 } // if matched
582 } // if cache entry valid
583 if (cacheEntry[1]) {
584 TlbEntry *ce = cacheEntry[1];
585 Addr ce_va = ce->range.va;
586 if (cacheAsi[1] == asi &&
587 ce_va < vaddr + size && ce_va + ce->range.size > vaddr &&
588 (!write || ce->pte.writable())) {
589 req->setPaddr(ce->pte.translate(vaddr));
590 if (ce->pte.sideffect() || (ce->pte.paddr() >> 39) & 1) {
591 req->setFlags(
592 Request::UNCACHEABLE | Request::STRICT_ORDER);
593 }
594 DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr());
595 return NoFault;
596 } // if matched
597 } // if cache entry valid
598 }
599 }
600
601 bool red = bits(tlbdata,1,1);
602 bool priv = bits(tlbdata,2,2);
603 bool addr_mask = bits(tlbdata,3,3);
604 bool lsu_dm = bits(tlbdata,5,5);
605
606 int part_id = bits(tlbdata,15,8);
607 int tl = bits(tlbdata,18,16);
608 int pri_context = bits(tlbdata,47,32);
609 int sec_context = bits(tlbdata,63,48);
610
611 bool real = false;
612 ContextType ct = Primary;
613 int context = 0;
614
615 TlbEntry *e;
616
617 DPRINTF(TLB, "TLB: priv:%d hpriv:%d red:%d lsudm:%d part_id: %#X\n",
618 priv, hpriv, red, lsu_dm, part_id);
619
620 if (implicit) {
621 if (tl > 0) {
622 asi = ASI_N;
623 ct = Nucleus;
624 context = 0;
625 } else {
626 asi = ASI_P;
627 ct = Primary;
628 context = pri_context;
629 }
630 } else {
631 // We need to check for priv level/asi priv
632 if (!priv && !hpriv && !asiIsUnPriv(asi)) {
633 // It appears that context should be Nucleus in these cases?
634 writeSfsr(vaddr, write, Nucleus, false, IllegalAsi, asi);
635 return std::make_shared<PrivilegedAction>();
636 }
637
638 if (!hpriv && asiIsHPriv(asi)) {
639 writeSfsr(vaddr, write, Nucleus, false, IllegalAsi, asi);
640 return std::make_shared<DataAccessException>();
641 }
642
643 if (asiIsPrimary(asi)) {
644 context = pri_context;
645 ct = Primary;
646 } else if (asiIsSecondary(asi)) {
647 context = sec_context;
648 ct = Secondary;
649 } else if (asiIsNucleus(asi)) {
650 ct = Nucleus;
651 context = 0;
652 } else { // ????
653 ct = Primary;
654 context = pri_context;
655 }
656 }
657
658 if (!implicit && asi != ASI_P && asi != ASI_S) {
659 if (asiIsLittle(asi))
660 panic("Little Endian ASIs not supported\n");
661
662 //XXX It's unclear from looking at the documentation how a no fault
663 // load differs from a regular one, other than what happens concerning
664 // nfo and e bits in the TTE
665// if (asiIsNoFault(asi))
666// panic("No Fault ASIs not supported\n");
667
668 if (asiIsPartialStore(asi))
669 panic("Partial Store ASIs not supported\n");
670
671 if (asiIsCmt(asi))
672 panic("Cmt ASI registers not implmented\n");
673
674 if (asiIsInterrupt(asi))
675 goto handleIntRegAccess;
676 if (asiIsMmu(asi))
677 goto handleMmuRegAccess;
678 if (asiIsScratchPad(asi))
679 goto handleScratchRegAccess;
680 if (asiIsQueue(asi))
681 goto handleQueueRegAccess;
682 if (asiIsSparcError(asi))
683 goto handleSparcErrorRegAccess;
684
685 if (!asiIsReal(asi) && !asiIsNucleus(asi) && !asiIsAsIfUser(asi) &&
686 !asiIsTwin(asi) && !asiIsBlock(asi) && !asiIsNoFault(asi))
687 panic("Accessing ASI %#X. Should we?\n", asi);
688 }
689
690 // If the asi is unaligned trap
691 if (unaligned) {
692 writeSfsr(vaddr, false, ct, false, OtherFault, asi);
693 return std::make_shared<MemAddressNotAligned>();
694 }
695
696 if (addr_mask)
697 vaddr = vaddr & VAddrAMask;
698
699 if (!validVirtualAddress(vaddr, addr_mask)) {
700 writeSfsr(vaddr, false, ct, true, VaOutOfRange, asi);
701 return std::make_shared<DataAccessException>();
702 }
703
704 if ((!lsu_dm && !hpriv && !red) || asiIsReal(asi)) {
705 real = true;
706 context = 0;
707 }
708
709 if (hpriv && (implicit || (!asiIsAsIfUser(asi) && !asiIsReal(asi)))) {
710 req->setPaddr(vaddr & PAddrImplMask);
711 return NoFault;
712 }
713
714 e = lookup(vaddr, part_id, real, context);
715
716 if (e == NULL || !e->valid) {
717 writeTagAccess(vaddr, context);
718 DPRINTF(TLB, "TLB: DTB Failed to find matching TLB entry\n");
719 if (real) {
720 return std::make_shared<DataRealTranslationMiss>();
721 } else {
722 if (FullSystem)
723 return std::make_shared<FastDataAccessMMUMiss>();
724 else
725 return std::make_shared<FastDataAccessMMUMiss>(
726 req->getVaddr());
727 }
728
729 }
730
731 if (!priv && e->pte.priv()) {
732 writeTagAccess(vaddr, context);
733 writeSfsr(vaddr, write, ct, e->pte.sideffect(), PrivViolation, asi);
734 return std::make_shared<DataAccessException>();
735 }
736
737 if (write && !e->pte.writable()) {
738 writeTagAccess(vaddr, context);
739 writeSfsr(vaddr, write, ct, e->pte.sideffect(), OtherFault, asi);
740 return std::make_shared<FastDataAccessProtection>();
741 }
742
743 if (e->pte.nofault() && !asiIsNoFault(asi)) {
744 writeTagAccess(vaddr, context);
745 writeSfsr(vaddr, write, ct, e->pte.sideffect(), LoadFromNfo, asi);
746 return std::make_shared<DataAccessException>();
747 }
748
749 if (e->pte.sideffect() && asiIsNoFault(asi)) {
750 writeTagAccess(vaddr, context);
751 writeSfsr(vaddr, write, ct, e->pte.sideffect(), SideEffect, asi);
752 return std::make_shared<DataAccessException>();
753 }
754
755 if (e->pte.sideffect() || (e->pte.paddr() >> 39) & 1)
756 req->setFlags(Request::UNCACHEABLE | Request::STRICT_ORDER);
757
758 // cache translation date for next translation
759 cacheState = tlbdata;
760 if (!cacheValid) {
761 cacheEntry[1] = NULL;
762 cacheEntry[0] = NULL;
763 }
764
765 if (cacheEntry[0] != e && cacheEntry[1] != e) {
766 cacheEntry[1] = cacheEntry[0];
767 cacheEntry[0] = e;
768 cacheAsi[1] = cacheAsi[0];
769 cacheAsi[0] = asi;
770 if (implicit)
771 cacheAsi[0] = (ASI)0;
772 }
773 cacheValid = true;
774 req->setPaddr(e->pte.translate(vaddr));
775 DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr());
776 return NoFault;
777
778 /** Normal flow ends here. */
779handleIntRegAccess:
780 if (!hpriv) {
781 writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi);
782 if (priv)
783 return std::make_shared<DataAccessException>();
784 else
785 return std::make_shared<PrivilegedAction>();
786 }
787
788 if ((asi == ASI_SWVR_UDB_INTR_W && !write) ||
789 (asi == ASI_SWVR_UDB_INTR_R && write)) {
790 writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi);
791 return std::make_shared<DataAccessException>();
792 }
793
794 goto regAccessOk;
795
796
797handleScratchRegAccess:
798 if (vaddr > 0x38 || (vaddr >= 0x20 && vaddr < 0x30 && !hpriv)) {
799 writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi);
800 return std::make_shared<DataAccessException>();
801 }
802 goto regAccessOk;
803
804handleQueueRegAccess:
805 if (!priv && !hpriv) {
806 writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi);
807 return std::make_shared<PrivilegedAction>();
808 }
809 if ((!hpriv && vaddr & 0xF) || vaddr > 0x3f8 || vaddr < 0x3c0) {
810 writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi);
811 return std::make_shared<DataAccessException>();
812 }
813 goto regAccessOk;
814
815handleSparcErrorRegAccess:
816 if (!hpriv) {
817 writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi);
818 if (priv)
819 return std::make_shared<DataAccessException>();
820 else
821 return std::make_shared<PrivilegedAction>();
822 }
823 goto regAccessOk;
824
825
826regAccessOk:
827handleMmuRegAccess:
828 DPRINTF(TLB, "TLB: DTB Translating MM IPR access\n");
829 req->setFlags(Request::MMAPPED_IPR);
830 req->setPaddr(req->getVaddr());
831 return NoFault;
832};
833
834Fault
835TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)
836{
837 if (mode == Execute)
838 return translateInst(req, tc);
839 else
840 return translateData(req, tc, mode == Write);
841}
842
843void
844TLB::translateTiming(RequestPtr req, ThreadContext *tc,
845 Translation *translation, Mode mode)
846{
847 assert(translation);
848 translation->finish(translateAtomic(req, tc, mode), req, tc, mode);
849}
850
851Fault
852TLB::finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const
853{
854 return NoFault;
855}
856
857Cycles
858TLB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
859{
860 Addr va = pkt->getAddr();
861 ASI asi = (ASI)pkt->req->getArchFlags();
862 uint64_t temp;
863
864 DPRINTF(IPR, "Memory Mapped IPR Read: asi=%#X a=%#x\n",
865 (uint32_t)pkt->req->getArchFlags(), pkt->getAddr());
866
867 TLB *itb = dynamic_cast<TLB *>(tc->getITBPtr());
868
869 switch (asi) {
870 case ASI_LSU_CONTROL_REG:
871 assert(va == 0);
872 pkt->set(tc->readMiscReg(MISCREG_MMU_LSU_CTRL));
873 break;
874 case ASI_MMU:
875 switch (va) {
876 case 0x8:
877 pkt->set(tc->readMiscReg(MISCREG_MMU_P_CONTEXT));
878 break;
879 case 0x10:
880 pkt->set(tc->readMiscReg(MISCREG_MMU_S_CONTEXT));
881 break;
882 default:
883 goto doMmuReadError;
884 }
885 break;
886 case ASI_QUEUE:
887 pkt->set(tc->readMiscReg(MISCREG_QUEUE_CPU_MONDO_HEAD +
888 (va >> 4) - 0x3c));
889 break;
890 case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0:
891 assert(va == 0);
892 pkt->set(c0_tsb_ps0);
893 break;
894 case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1:
895 assert(va == 0);
896 pkt->set(c0_tsb_ps1);
897 break;
898 case ASI_DMMU_CTXT_ZERO_CONFIG:
899 assert(va == 0);
900 pkt->set(c0_config);
901 break;
902 case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0:
903 assert(va == 0);
904 pkt->set(itb->c0_tsb_ps0);
905 break;
906 case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1:
907 assert(va == 0);
908 pkt->set(itb->c0_tsb_ps1);
909 break;
910 case ASI_IMMU_CTXT_ZERO_CONFIG:
911 assert(va == 0);
912 pkt->set(itb->c0_config);
913 break;
914 case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0:
915 assert(va == 0);
916 pkt->set(cx_tsb_ps0);
917 break;
918 case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1:
919 assert(va == 0);
920 pkt->set(cx_tsb_ps1);
921 break;
922 case ASI_DMMU_CTXT_NONZERO_CONFIG:
923 assert(va == 0);
924 pkt->set(cx_config);
925 break;
926 case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0:
927 assert(va == 0);
928 pkt->set(itb->cx_tsb_ps0);
929 break;
930 case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1:
931 assert(va == 0);
932 pkt->set(itb->cx_tsb_ps1);
933 break;
934 case ASI_IMMU_CTXT_NONZERO_CONFIG:
935 assert(va == 0);
936 pkt->set(itb->cx_config);
937 break;
938 case ASI_SPARC_ERROR_STATUS_REG:
939 pkt->set((uint64_t)0);
940 break;
941 case ASI_HYP_SCRATCHPAD:
942 case ASI_SCRATCHPAD:
943 pkt->set(tc->readMiscReg(MISCREG_SCRATCHPAD_R0 + (va >> 3)));
944 break;
945 case ASI_IMMU:
946 switch (va) {
947 case 0x0:
948 temp = itb->tag_access;
949 pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48);
950 break;
951 case 0x18:
952 pkt->set(itb->sfsr);
953 break;
954 case 0x30:
955 pkt->set(itb->tag_access);
956 break;
957 default:
958 goto doMmuReadError;
959 }
960 break;
961 case ASI_DMMU:
962 switch (va) {
963 case 0x0:
964 temp = tag_access;
965 pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48);
966 break;
967 case 0x18:
968 pkt->set(sfsr);
969 break;
970 case 0x20:
971 pkt->set(sfar);
972 break;
973 case 0x30:
974 pkt->set(tag_access);
975 break;
976 case 0x80:
977 pkt->set(tc->readMiscReg(MISCREG_MMU_PART_ID));
978 break;
979 default:
980 goto doMmuReadError;
981 }
982 break;
983 case ASI_DMMU_TSB_PS0_PTR_REG:
984 pkt->set(MakeTsbPtr(Ps0,
985 tag_access,
986 c0_tsb_ps0,
987 c0_config,
988 cx_tsb_ps0,
989 cx_config));
990 break;
991 case ASI_DMMU_TSB_PS1_PTR_REG:
992 pkt->set(MakeTsbPtr(Ps1,
993 tag_access,
994 c0_tsb_ps1,
995 c0_config,
996 cx_tsb_ps1,
997 cx_config));
998 break;
999 case ASI_IMMU_TSB_PS0_PTR_REG:
1000 pkt->set(MakeTsbPtr(Ps0,
1001 itb->tag_access,
1002 itb->c0_tsb_ps0,
1003 itb->c0_config,
1004 itb->cx_tsb_ps0,
1005 itb->cx_config));
1006 break;
1007 case ASI_IMMU_TSB_PS1_PTR_REG:
1008 pkt->set(MakeTsbPtr(Ps1,
1009 itb->tag_access,
1010 itb->c0_tsb_ps1,
1011 itb->c0_config,
1012 itb->cx_tsb_ps1,
1013 itb->cx_config));
1014 break;
1015 case ASI_SWVR_INTR_RECEIVE:
1016 {
1017 SparcISA::Interrupts * interrupts =
1018 dynamic_cast<SparcISA::Interrupts *>(
1019 tc->getCpuPtr()->getInterruptController(0));
1020 pkt->set(interrupts->get_vec(IT_INT_VEC));
1021 }
1022 break;
1023 case ASI_SWVR_UDB_INTR_R:
1024 {
1025 SparcISA::Interrupts * interrupts =
1026 dynamic_cast<SparcISA::Interrupts *>(
1027 tc->getCpuPtr()->getInterruptController(0));
1028 temp = findMsbSet(interrupts->get_vec(IT_INT_VEC));
1029 tc->getCpuPtr()->clearInterrupt(0, IT_INT_VEC, temp);
1030 pkt->set(temp);
1031 }
1032 break;
1033 default:
1034doMmuReadError:
1035 panic("need to impl DTB::doMmuRegRead() got asi=%#x, va=%#x\n",
1036 (uint32_t)asi, va);
1037 }
1038 pkt->makeAtomicResponse();
1039 return Cycles(1);
1040}
1041
1042Cycles
1043TLB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
1044{
1045 uint64_t data = pkt->get<uint64_t>();
1046 Addr va = pkt->getAddr();
1047 ASI asi = (ASI)pkt->req->getArchFlags();
1048
1049 Addr ta_insert;
1050 Addr va_insert;
1051 Addr ct_insert;
1052 int part_insert;
1053 int entry_insert = -1;
1054 bool real_insert;
1055 bool ignore;
1056 int part_id;
1057 int ctx_id;
1058 PageTableEntry pte;
1059
1060 DPRINTF(IPR, "Memory Mapped IPR Write: asi=%#X a=%#x d=%#X\n",
1061 (uint32_t)asi, va, data);
1062
1063 TLB *itb = dynamic_cast<TLB *>(tc->getITBPtr());
1064
1065 switch (asi) {
1066 case ASI_LSU_CONTROL_REG:
1067 assert(va == 0);
1068 tc->setMiscReg(MISCREG_MMU_LSU_CTRL, data);
1069 break;
1070 case ASI_MMU:
1071 switch (va) {
1072 case 0x8:
1073 tc->setMiscReg(MISCREG_MMU_P_CONTEXT, data);
1074 break;
1075 case 0x10:
1076 tc->setMiscReg(MISCREG_MMU_S_CONTEXT, data);
1077 break;
1078 default:
1079 goto doMmuWriteError;
1080 }
1081 break;
1082 case ASI_QUEUE:
1083 assert(mbits(data,13,6) == data);
1084 tc->setMiscReg(MISCREG_QUEUE_CPU_MONDO_HEAD +
1085 (va >> 4) - 0x3c, data);
1086 break;
1087 case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0:
1088 assert(va == 0);
1089 c0_tsb_ps0 = data;
1090 break;
1091 case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1:
1092 assert(va == 0);
1093 c0_tsb_ps1 = data;
1094 break;
1095 case ASI_DMMU_CTXT_ZERO_CONFIG:
1096 assert(va == 0);
1097 c0_config = data;
1098 break;
1099 case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0:
1100 assert(va == 0);
1101 itb->c0_tsb_ps0 = data;
1102 break;
1103 case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1:
1104 assert(va == 0);
1105 itb->c0_tsb_ps1 = data;
1106 break;
1107 case ASI_IMMU_CTXT_ZERO_CONFIG:
1108 assert(va == 0);
1109 itb->c0_config = data;
1110 break;
1111 case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0:
1112 assert(va == 0);
1113 cx_tsb_ps0 = data;
1114 break;
1115 case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1:
1116 assert(va == 0);
1117 cx_tsb_ps1 = data;
1118 break;
1119 case ASI_DMMU_CTXT_NONZERO_CONFIG:
1120 assert(va == 0);
1121 cx_config = data;
1122 break;
1123 case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0:
1124 assert(va == 0);
1125 itb->cx_tsb_ps0 = data;
1126 break;
1127 case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1:
1128 assert(va == 0);
1129 itb->cx_tsb_ps1 = data;
1130 break;
1131 case ASI_IMMU_CTXT_NONZERO_CONFIG:
1132 assert(va == 0);
1133 itb->cx_config = data;
1134 break;
1135 case ASI_SPARC_ERROR_EN_REG:
1136 case ASI_SPARC_ERROR_STATUS_REG:
1137 inform("Ignoring write to SPARC ERROR regsiter\n");
1138 break;
1139 case ASI_HYP_SCRATCHPAD:
1140 case ASI_SCRATCHPAD:
1141 tc->setMiscReg(MISCREG_SCRATCHPAD_R0 + (va >> 3), data);
1142 break;
1143 case ASI_IMMU:
1144 switch (va) {
1145 case 0x18:
1146 itb->sfsr = data;
1147 break;
1148 case 0x30:
1149 sext<59>(bits(data, 59,0));
1150 itb->tag_access = data;
1151 break;
1152 default:
1153 goto doMmuWriteError;
1154 }
1155 break;
1156 case ASI_ITLB_DATA_ACCESS_REG:
1157 entry_insert = bits(va, 8,3);
| 40#include "base/trace.hh"
41#include "cpu/base.hh"
42#include "cpu/thread_context.hh"
43#include "debug/IPR.hh"
44#include "debug/TLB.hh"
45#include "mem/packet_access.hh"
46#include "mem/request.hh"
47#include "sim/full_system.hh"
48#include "sim/system.hh"
49
50/* @todo remove some of the magic constants. -- ali
51 * */
52namespace SparcISA {
53
54TLB::TLB(const Params *p)
55 : BaseTLB(p), size(p->size), usedEntries(0), lastReplaced(0),
56 cacheState(0), cacheValid(false)
57{
58 // To make this work you'll have to change the hypervisor and OS
59 if (size > 64)
60 fatal("SPARC T1 TLB registers don't support more than 64 TLB entries");
61
62 tlb = new TlbEntry[size];
63 std::memset(tlb, 0, sizeof(TlbEntry) * size);
64
65 for (int x = 0; x < size; x++)
66 freeList.push_back(&tlb[x]);
67
68 c0_tsb_ps0 = 0;
69 c0_tsb_ps1 = 0;
70 c0_config = 0;
71 cx_tsb_ps0 = 0;
72 cx_tsb_ps1 = 0;
73 cx_config = 0;
74 sfsr = 0;
75 tag_access = 0;
76 sfar = 0;
77 cacheEntry[0] = NULL;
78 cacheEntry[1] = NULL;
79}
80
81void
82TLB::clearUsedBits()
83{
84 MapIter i;
85 for (i = lookupTable.begin(); i != lookupTable.end(); i++) {
86 TlbEntry *t = i->second;
87 if (!t->pte.locked()) {
88 t->used = false;
89 usedEntries--;
90 }
91 }
92}
93
94
95void
96TLB::insert(Addr va, int partition_id, int context_id, bool real,
97 const PageTableEntry& PTE, int entry)
98{
99 MapIter i;
100 TlbEntry *new_entry = NULL;
101// TlbRange tr;
102 int x;
103
104 cacheValid = false;
105 va &= ~(PTE.size()-1);
106 /* tr.va = va;
107 tr.size = PTE.size() - 1;
108 tr.contextId = context_id;
109 tr.partitionId = partition_id;
110 tr.real = real;
111*/
112
113 DPRINTF(TLB,
114 "TLB: Inserting Entry; va=%#x pa=%#x pid=%d cid=%d r=%d entryid=%d\n",
115 va, PTE.paddr(), partition_id, context_id, (int)real, entry);
116
117 // Demap any entry that conflicts
118 for (x = 0; x < size; x++) {
119 if (tlb[x].range.real == real &&
120 tlb[x].range.partitionId == partition_id &&
121 tlb[x].range.va < va + PTE.size() - 1 &&
122 tlb[x].range.va + tlb[x].range.size >= va &&
123 (real || tlb[x].range.contextId == context_id ))
124 {
125 if (tlb[x].valid) {
126 freeList.push_front(&tlb[x]);
127 DPRINTF(TLB, "TLB: Conflicting entry %#X , deleting it\n", x);
128
129 tlb[x].valid = false;
130 if (tlb[x].used) {
131 tlb[x].used = false;
132 usedEntries--;
133 }
134 lookupTable.erase(tlb[x].range);
135 }
136 }
137 }
138
139 if (entry != -1) {
140 assert(entry < size && entry >= 0);
141 new_entry = &tlb[entry];
142 } else {
143 if (!freeList.empty()) {
144 new_entry = freeList.front();
145 } else {
146 x = lastReplaced;
147 do {
148 ++x;
149 if (x == size)
150 x = 0;
151 if (x == lastReplaced)
152 goto insertAllLocked;
153 } while (tlb[x].pte.locked());
154 lastReplaced = x;
155 new_entry = &tlb[x];
156 }
157 }
158
159insertAllLocked:
160 // Update the last ently if their all locked
161 if (!new_entry) {
162 new_entry = &tlb[size-1];
163 }
164
165 freeList.remove(new_entry);
166 if (new_entry->valid && new_entry->used)
167 usedEntries--;
168 if (new_entry->valid)
169 lookupTable.erase(new_entry->range);
170
171
172 assert(PTE.valid());
173 new_entry->range.va = va;
174 new_entry->range.size = PTE.size() - 1;
175 new_entry->range.partitionId = partition_id;
176 new_entry->range.contextId = context_id;
177 new_entry->range.real = real;
178 new_entry->pte = PTE;
179 new_entry->used = true;;
180 new_entry->valid = true;
181 usedEntries++;
182
183 i = lookupTable.insert(new_entry->range, new_entry);
184 assert(i != lookupTable.end());
185
186 // If all entries have their used bit set, clear it on them all,
187 // but the one we just inserted
188 if (usedEntries == size) {
189 clearUsedBits();
190 new_entry->used = true;
191 usedEntries++;
192 }
193}
194
195
196TlbEntry*
197TLB::lookup(Addr va, int partition_id, bool real, int context_id,
198 bool update_used)
199{
200 MapIter i;
201 TlbRange tr;
202 TlbEntry *t;
203
204 DPRINTF(TLB, "TLB: Looking up entry va=%#x pid=%d cid=%d r=%d\n",
205 va, partition_id, context_id, real);
206 // Assemble full address structure
207 tr.va = va;
208 tr.size = 1;
209 tr.contextId = context_id;
210 tr.partitionId = partition_id;
211 tr.real = real;
212
213 // Try to find the entry
214 i = lookupTable.find(tr);
215 if (i == lookupTable.end()) {
216 DPRINTF(TLB, "TLB: No valid entry found\n");
217 return NULL;
218 }
219
220 // Mark the entries used bit and clear other used bits in needed
221 t = i->second;
222 DPRINTF(TLB, "TLB: Valid entry found pa: %#x size: %#x\n", t->pte.paddr(),
223 t->pte.size());
224
225 // Update the used bits only if this is a real access (not a fake
226 // one from virttophys()
227 if (!t->used && update_used) {
228 t->used = true;
229 usedEntries++;
230 if (usedEntries == size) {
231 clearUsedBits();
232 t->used = true;
233 usedEntries++;
234 }
235 }
236
237 return t;
238}
239
240void
241TLB::dumpAll()
242{
243 MapIter i;
244 for (int x = 0; x < size; x++) {
245 if (tlb[x].valid) {
246 DPRINTFN("%4d: %#2x:%#2x %c %#4x %#8x %#8x %#16x\n",
247 x, tlb[x].range.partitionId, tlb[x].range.contextId,
248 tlb[x].range.real ? 'R' : ' ', tlb[x].range.size,
249 tlb[x].range.va, tlb[x].pte.paddr(), tlb[x].pte());
250 }
251 }
252}
253
254void
255TLB::demapPage(Addr va, int partition_id, bool real, int context_id)
256{
257 TlbRange tr;
258 MapIter i;
259
260 DPRINTF(IPR, "TLB: Demapping Page va=%#x pid=%#d cid=%d r=%d\n",
261 va, partition_id, context_id, real);
262
263 cacheValid = false;
264
265 // Assemble full address structure
266 tr.va = va;
267 tr.size = 1;
268 tr.contextId = context_id;
269 tr.partitionId = partition_id;
270 tr.real = real;
271
272 // Demap any entry that conflicts
273 i = lookupTable.find(tr);
274 if (i != lookupTable.end()) {
275 DPRINTF(IPR, "TLB: Demapped page\n");
276 i->second->valid = false;
277 if (i->second->used) {
278 i->second->used = false;
279 usedEntries--;
280 }
281 freeList.push_front(i->second);
282 lookupTable.erase(i);
283 }
284}
285
286void
287TLB::demapContext(int partition_id, int context_id)
288{
289 DPRINTF(IPR, "TLB: Demapping Context pid=%#d cid=%d\n",
290 partition_id, context_id);
291 cacheValid = false;
292 for (int x = 0; x < size; x++) {
293 if (tlb[x].range.contextId == context_id &&
294 tlb[x].range.partitionId == partition_id) {
295 if (tlb[x].valid) {
296 freeList.push_front(&tlb[x]);
297 }
298 tlb[x].valid = false;
299 if (tlb[x].used) {
300 tlb[x].used = false;
301 usedEntries--;
302 }
303 lookupTable.erase(tlb[x].range);
304 }
305 }
306}
307
308void
309TLB::demapAll(int partition_id)
310{
311 DPRINTF(TLB, "TLB: Demapping All pid=%#d\n", partition_id);
312 cacheValid = false;
313 for (int x = 0; x < size; x++) {
314 if (tlb[x].valid && !tlb[x].pte.locked() &&
315 tlb[x].range.partitionId == partition_id) {
316 freeList.push_front(&tlb[x]);
317 tlb[x].valid = false;
318 if (tlb[x].used) {
319 tlb[x].used = false;
320 usedEntries--;
321 }
322 lookupTable.erase(tlb[x].range);
323 }
324 }
325}
326
327void
328TLB::flushAll()
329{
330 cacheValid = false;
331 lookupTable.clear();
332
333 for (int x = 0; x < size; x++) {
334 if (tlb[x].valid)
335 freeList.push_back(&tlb[x]);
336 tlb[x].valid = false;
337 tlb[x].used = false;
338 }
339 usedEntries = 0;
340}
341
342uint64_t
343TLB::TteRead(int entry)
344{
345 if (entry >= size)
346 panic("entry: %d\n", entry);
347
348 assert(entry < size);
349 if (tlb[entry].valid)
350 return tlb[entry].pte();
351 else
352 return (uint64_t)-1ll;
353}
354
355uint64_t
356TLB::TagRead(int entry)
357{
358 assert(entry < size);
359 uint64_t tag;
360 if (!tlb[entry].valid)
361 return (uint64_t)-1ll;
362
363 tag = tlb[entry].range.contextId;
364 tag |= tlb[entry].range.va;
365 tag |= (uint64_t)tlb[entry].range.partitionId << 61;
366 tag |= tlb[entry].range.real ? ULL(1) << 60 : 0;
367 tag |= (uint64_t)~tlb[entry].pte._size() << 56;
368 return tag;
369}
370
371bool
372TLB::validVirtualAddress(Addr va, bool am)
373{
374 if (am)
375 return true;
376 if (va >= StartVAddrHole && va <= EndVAddrHole)
377 return false;
378 return true;
379}
380
381void
382TLB::writeSfsr(bool write, ContextType ct, bool se, FaultTypes ft, int asi)
383{
384 if (sfsr & 0x1)
385 sfsr = 0x3;
386 else
387 sfsr = 1;
388
389 if (write)
390 sfsr |= 1 << 2;
391 sfsr |= ct << 4;
392 if (se)
393 sfsr |= 1 << 6;
394 sfsr |= ft << 7;
395 sfsr |= asi << 16;
396}
397
398void
399TLB::writeTagAccess(Addr va, int context)
400{
401 DPRINTF(TLB, "TLB: Writing Tag Access: va: %#X ctx: %#X value: %#X\n",
402 va, context, mbits(va, 63,13) | mbits(context,12,0));
403
404 tag_access = mbits(va, 63,13) | mbits(context,12,0);
405}
406
407void
408TLB::writeSfsr(Addr a, bool write, ContextType ct,
409 bool se, FaultTypes ft, int asi)
410{
411 DPRINTF(TLB, "TLB: Fault: A=%#x w=%d ct=%d ft=%d asi=%d\n",
412 a, (int)write, ct, ft, asi);
413 TLB::writeSfsr(write, ct, se, ft, asi);
414 sfar = a;
415}
416
417Fault
418TLB::translateInst(RequestPtr req, ThreadContext *tc)
419{
420 uint64_t tlbdata = tc->readMiscRegNoEffect(MISCREG_TLB_DATA);
421
422 Addr vaddr = req->getVaddr();
423 TlbEntry *e;
424
425 assert(req->getArchFlags() == ASI_IMPLICIT);
426
427 DPRINTF(TLB, "TLB: ITB Request to translate va=%#x size=%d\n",
428 vaddr, req->getSize());
429
430 // Be fast if we can!
431 if (cacheValid && cacheState == tlbdata) {
432 if (cacheEntry[0]) {
433 if (cacheEntry[0]->range.va < vaddr + sizeof(MachInst) &&
434 cacheEntry[0]->range.va + cacheEntry[0]->range.size >= vaddr) {
435 req->setPaddr(cacheEntry[0]->pte.translate(vaddr));
436 return NoFault;
437 }
438 } else {
439 req->setPaddr(vaddr & PAddrImplMask);
440 return NoFault;
441 }
442 }
443
444 bool hpriv = bits(tlbdata,0,0);
445 bool red = bits(tlbdata,1,1);
446 bool priv = bits(tlbdata,2,2);
447 bool addr_mask = bits(tlbdata,3,3);
448 bool lsu_im = bits(tlbdata,4,4);
449
450 int part_id = bits(tlbdata,15,8);
451 int tl = bits(tlbdata,18,16);
452 int pri_context = bits(tlbdata,47,32);
453 int context;
454 ContextType ct;
455 int asi;
456 bool real = false;
457
458 DPRINTF(TLB, "TLB: priv:%d hpriv:%d red:%d lsuim:%d part_id: %#X\n",
459 priv, hpriv, red, lsu_im, part_id);
460
461 if (tl > 0) {
462 asi = ASI_N;
463 ct = Nucleus;
464 context = 0;
465 } else {
466 asi = ASI_P;
467 ct = Primary;
468 context = pri_context;
469 }
470
471 if ( hpriv || red ) {
472 cacheValid = true;
473 cacheState = tlbdata;
474 cacheEntry[0] = NULL;
475 req->setPaddr(vaddr & PAddrImplMask);
476 return NoFault;
477 }
478
479 // If the access is unaligned trap
480 if (vaddr & 0x3) {
481 writeSfsr(false, ct, false, OtherFault, asi);
482 return std::make_shared<MemAddressNotAligned>();
483 }
484
485 if (addr_mask)
486 vaddr = vaddr & VAddrAMask;
487
488 if (!validVirtualAddress(vaddr, addr_mask)) {
489 writeSfsr(false, ct, false, VaOutOfRange, asi);
490 return std::make_shared<InstructionAccessException>();
491 }
492
493 if (!lsu_im) {
494 e = lookup(vaddr, part_id, true);
495 real = true;
496 context = 0;
497 } else {
498 e = lookup(vaddr, part_id, false, context);
499 }
500
501 if (e == NULL || !e->valid) {
502 writeTagAccess(vaddr, context);
503 if (real) {
504 return std::make_shared<InstructionRealTranslationMiss>();
505 } else {
506 if (FullSystem)
507 return std::make_shared<FastInstructionAccessMMUMiss>();
508 else
509 return std::make_shared<FastInstructionAccessMMUMiss>(
510 req->getVaddr());
511 }
512 }
513
514 // were not priviledged accesing priv page
515 if (!priv && e->pte.priv()) {
516 writeTagAccess(vaddr, context);
517 writeSfsr(false, ct, false, PrivViolation, asi);
518 return std::make_shared<InstructionAccessException>();
519 }
520
521 // cache translation date for next translation
522 cacheValid = true;
523 cacheState = tlbdata;
524 cacheEntry[0] = e;
525
526 req->setPaddr(e->pte.translate(vaddr));
527 DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr());
528 return NoFault;
529}
530
531Fault
532TLB::translateData(RequestPtr req, ThreadContext *tc, bool write)
533{
534 /*
535 * @todo this could really use some profiling and fixing to make
536 * it faster!
537 */
538 uint64_t tlbdata = tc->readMiscRegNoEffect(MISCREG_TLB_DATA);
539 Addr vaddr = req->getVaddr();
540 Addr size = req->getSize();
541 ASI asi;
542 asi = (ASI)req->getArchFlags();
543 bool implicit = false;
544 bool hpriv = bits(tlbdata,0,0);
545 bool unaligned = vaddr & (size - 1);
546
547 DPRINTF(TLB, "TLB: DTB Request to translate va=%#x size=%d asi=%#x\n",
548 vaddr, size, asi);
549
550 if (lookupTable.size() != 64 - freeList.size())
551 panic("Lookup table size: %d tlb size: %d\n", lookupTable.size(),
552 freeList.size());
553 if (asi == ASI_IMPLICIT)
554 implicit = true;
555
556 // Only use the fast path here if there doesn't need to be an unaligned
557 // trap later
558 if (!unaligned) {
559 if (hpriv && implicit) {
560 req->setPaddr(vaddr & PAddrImplMask);
561 return NoFault;
562 }
563
564 // Be fast if we can!
565 if (cacheValid && cacheState == tlbdata) {
566
567
568
569 if (cacheEntry[0]) {
570 TlbEntry *ce = cacheEntry[0];
571 Addr ce_va = ce->range.va;
572 if (cacheAsi[0] == asi &&
573 ce_va < vaddr + size && ce_va + ce->range.size > vaddr &&
574 (!write || ce->pte.writable())) {
575 req->setPaddr(ce->pte.translate(vaddr));
576 if (ce->pte.sideffect() || (ce->pte.paddr() >> 39) & 1) {
577 req->setFlags(
578 Request::UNCACHEABLE | Request::STRICT_ORDER);
579 }
580 DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr());
581 return NoFault;
582 } // if matched
583 } // if cache entry valid
584 if (cacheEntry[1]) {
585 TlbEntry *ce = cacheEntry[1];
586 Addr ce_va = ce->range.va;
587 if (cacheAsi[1] == asi &&
588 ce_va < vaddr + size && ce_va + ce->range.size > vaddr &&
589 (!write || ce->pte.writable())) {
590 req->setPaddr(ce->pte.translate(vaddr));
591 if (ce->pte.sideffect() || (ce->pte.paddr() >> 39) & 1) {
592 req->setFlags(
593 Request::UNCACHEABLE | Request::STRICT_ORDER);
594 }
595 DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr());
596 return NoFault;
597 } // if matched
598 } // if cache entry valid
599 }
600 }
601
602 bool red = bits(tlbdata,1,1);
603 bool priv = bits(tlbdata,2,2);
604 bool addr_mask = bits(tlbdata,3,3);
605 bool lsu_dm = bits(tlbdata,5,5);
606
607 int part_id = bits(tlbdata,15,8);
608 int tl = bits(tlbdata,18,16);
609 int pri_context = bits(tlbdata,47,32);
610 int sec_context = bits(tlbdata,63,48);
611
612 bool real = false;
613 ContextType ct = Primary;
614 int context = 0;
615
616 TlbEntry *e;
617
618 DPRINTF(TLB, "TLB: priv:%d hpriv:%d red:%d lsudm:%d part_id: %#X\n",
619 priv, hpriv, red, lsu_dm, part_id);
620
621 if (implicit) {
622 if (tl > 0) {
623 asi = ASI_N;
624 ct = Nucleus;
625 context = 0;
626 } else {
627 asi = ASI_P;
628 ct = Primary;
629 context = pri_context;
630 }
631 } else {
632 // We need to check for priv level/asi priv
633 if (!priv && !hpriv && !asiIsUnPriv(asi)) {
634 // It appears that context should be Nucleus in these cases?
635 writeSfsr(vaddr, write, Nucleus, false, IllegalAsi, asi);
636 return std::make_shared<PrivilegedAction>();
637 }
638
639 if (!hpriv && asiIsHPriv(asi)) {
640 writeSfsr(vaddr, write, Nucleus, false, IllegalAsi, asi);
641 return std::make_shared<DataAccessException>();
642 }
643
644 if (asiIsPrimary(asi)) {
645 context = pri_context;
646 ct = Primary;
647 } else if (asiIsSecondary(asi)) {
648 context = sec_context;
649 ct = Secondary;
650 } else if (asiIsNucleus(asi)) {
651 ct = Nucleus;
652 context = 0;
653 } else { // ????
654 ct = Primary;
655 context = pri_context;
656 }
657 }
658
659 if (!implicit && asi != ASI_P && asi != ASI_S) {
660 if (asiIsLittle(asi))
661 panic("Little Endian ASIs not supported\n");
662
663 //XXX It's unclear from looking at the documentation how a no fault
664 // load differs from a regular one, other than what happens concerning
665 // nfo and e bits in the TTE
666// if (asiIsNoFault(asi))
667// panic("No Fault ASIs not supported\n");
668
669 if (asiIsPartialStore(asi))
670 panic("Partial Store ASIs not supported\n");
671
672 if (asiIsCmt(asi))
673 panic("Cmt ASI registers not implmented\n");
674
675 if (asiIsInterrupt(asi))
676 goto handleIntRegAccess;
677 if (asiIsMmu(asi))
678 goto handleMmuRegAccess;
679 if (asiIsScratchPad(asi))
680 goto handleScratchRegAccess;
681 if (asiIsQueue(asi))
682 goto handleQueueRegAccess;
683 if (asiIsSparcError(asi))
684 goto handleSparcErrorRegAccess;
685
686 if (!asiIsReal(asi) && !asiIsNucleus(asi) && !asiIsAsIfUser(asi) &&
687 !asiIsTwin(asi) && !asiIsBlock(asi) && !asiIsNoFault(asi))
688 panic("Accessing ASI %#X. Should we?\n", asi);
689 }
690
691 // If the asi is unaligned trap
692 if (unaligned) {
693 writeSfsr(vaddr, false, ct, false, OtherFault, asi);
694 return std::make_shared<MemAddressNotAligned>();
695 }
696
697 if (addr_mask)
698 vaddr = vaddr & VAddrAMask;
699
700 if (!validVirtualAddress(vaddr, addr_mask)) {
701 writeSfsr(vaddr, false, ct, true, VaOutOfRange, asi);
702 return std::make_shared<DataAccessException>();
703 }
704
705 if ((!lsu_dm && !hpriv && !red) || asiIsReal(asi)) {
706 real = true;
707 context = 0;
708 }
709
710 if (hpriv && (implicit || (!asiIsAsIfUser(asi) && !asiIsReal(asi)))) {
711 req->setPaddr(vaddr & PAddrImplMask);
712 return NoFault;
713 }
714
715 e = lookup(vaddr, part_id, real, context);
716
717 if (e == NULL || !e->valid) {
718 writeTagAccess(vaddr, context);
719 DPRINTF(TLB, "TLB: DTB Failed to find matching TLB entry\n");
720 if (real) {
721 return std::make_shared<DataRealTranslationMiss>();
722 } else {
723 if (FullSystem)
724 return std::make_shared<FastDataAccessMMUMiss>();
725 else
726 return std::make_shared<FastDataAccessMMUMiss>(
727 req->getVaddr());
728 }
729
730 }
731
732 if (!priv && e->pte.priv()) {
733 writeTagAccess(vaddr, context);
734 writeSfsr(vaddr, write, ct, e->pte.sideffect(), PrivViolation, asi);
735 return std::make_shared<DataAccessException>();
736 }
737
738 if (write && !e->pte.writable()) {
739 writeTagAccess(vaddr, context);
740 writeSfsr(vaddr, write, ct, e->pte.sideffect(), OtherFault, asi);
741 return std::make_shared<FastDataAccessProtection>();
742 }
743
744 if (e->pte.nofault() && !asiIsNoFault(asi)) {
745 writeTagAccess(vaddr, context);
746 writeSfsr(vaddr, write, ct, e->pte.sideffect(), LoadFromNfo, asi);
747 return std::make_shared<DataAccessException>();
748 }
749
750 if (e->pte.sideffect() && asiIsNoFault(asi)) {
751 writeTagAccess(vaddr, context);
752 writeSfsr(vaddr, write, ct, e->pte.sideffect(), SideEffect, asi);
753 return std::make_shared<DataAccessException>();
754 }
755
756 if (e->pte.sideffect() || (e->pte.paddr() >> 39) & 1)
757 req->setFlags(Request::UNCACHEABLE | Request::STRICT_ORDER);
758
759 // cache translation date for next translation
760 cacheState = tlbdata;
761 if (!cacheValid) {
762 cacheEntry[1] = NULL;
763 cacheEntry[0] = NULL;
764 }
765
766 if (cacheEntry[0] != e && cacheEntry[1] != e) {
767 cacheEntry[1] = cacheEntry[0];
768 cacheEntry[0] = e;
769 cacheAsi[1] = cacheAsi[0];
770 cacheAsi[0] = asi;
771 if (implicit)
772 cacheAsi[0] = (ASI)0;
773 }
774 cacheValid = true;
775 req->setPaddr(e->pte.translate(vaddr));
776 DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr());
777 return NoFault;
778
779 /** Normal flow ends here. */
780handleIntRegAccess:
781 if (!hpriv) {
782 writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi);
783 if (priv)
784 return std::make_shared<DataAccessException>();
785 else
786 return std::make_shared<PrivilegedAction>();
787 }
788
789 if ((asi == ASI_SWVR_UDB_INTR_W && !write) ||
790 (asi == ASI_SWVR_UDB_INTR_R && write)) {
791 writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi);
792 return std::make_shared<DataAccessException>();
793 }
794
795 goto regAccessOk;
796
797
798handleScratchRegAccess:
799 if (vaddr > 0x38 || (vaddr >= 0x20 && vaddr < 0x30 && !hpriv)) {
800 writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi);
801 return std::make_shared<DataAccessException>();
802 }
803 goto regAccessOk;
804
805handleQueueRegAccess:
806 if (!priv && !hpriv) {
807 writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi);
808 return std::make_shared<PrivilegedAction>();
809 }
810 if ((!hpriv && vaddr & 0xF) || vaddr > 0x3f8 || vaddr < 0x3c0) {
811 writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi);
812 return std::make_shared<DataAccessException>();
813 }
814 goto regAccessOk;
815
816handleSparcErrorRegAccess:
817 if (!hpriv) {
818 writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi);
819 if (priv)
820 return std::make_shared<DataAccessException>();
821 else
822 return std::make_shared<PrivilegedAction>();
823 }
824 goto regAccessOk;
825
826
827regAccessOk:
828handleMmuRegAccess:
829 DPRINTF(TLB, "TLB: DTB Translating MM IPR access\n");
830 req->setFlags(Request::MMAPPED_IPR);
831 req->setPaddr(req->getVaddr());
832 return NoFault;
833};
834
835Fault
836TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)
837{
838 if (mode == Execute)
839 return translateInst(req, tc);
840 else
841 return translateData(req, tc, mode == Write);
842}
843
844void
845TLB::translateTiming(RequestPtr req, ThreadContext *tc,
846 Translation *translation, Mode mode)
847{
848 assert(translation);
849 translation->finish(translateAtomic(req, tc, mode), req, tc, mode);
850}
851
852Fault
853TLB::finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const
854{
855 return NoFault;
856}
857
858Cycles
859TLB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
860{
861 Addr va = pkt->getAddr();
862 ASI asi = (ASI)pkt->req->getArchFlags();
863 uint64_t temp;
864
865 DPRINTF(IPR, "Memory Mapped IPR Read: asi=%#X a=%#x\n",
866 (uint32_t)pkt->req->getArchFlags(), pkt->getAddr());
867
868 TLB *itb = dynamic_cast<TLB *>(tc->getITBPtr());
869
870 switch (asi) {
871 case ASI_LSU_CONTROL_REG:
872 assert(va == 0);
873 pkt->set(tc->readMiscReg(MISCREG_MMU_LSU_CTRL));
874 break;
875 case ASI_MMU:
876 switch (va) {
877 case 0x8:
878 pkt->set(tc->readMiscReg(MISCREG_MMU_P_CONTEXT));
879 break;
880 case 0x10:
881 pkt->set(tc->readMiscReg(MISCREG_MMU_S_CONTEXT));
882 break;
883 default:
884 goto doMmuReadError;
885 }
886 break;
887 case ASI_QUEUE:
888 pkt->set(tc->readMiscReg(MISCREG_QUEUE_CPU_MONDO_HEAD +
889 (va >> 4) - 0x3c));
890 break;
891 case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0:
892 assert(va == 0);
893 pkt->set(c0_tsb_ps0);
894 break;
895 case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1:
896 assert(va == 0);
897 pkt->set(c0_tsb_ps1);
898 break;
899 case ASI_DMMU_CTXT_ZERO_CONFIG:
900 assert(va == 0);
901 pkt->set(c0_config);
902 break;
903 case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0:
904 assert(va == 0);
905 pkt->set(itb->c0_tsb_ps0);
906 break;
907 case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1:
908 assert(va == 0);
909 pkt->set(itb->c0_tsb_ps1);
910 break;
911 case ASI_IMMU_CTXT_ZERO_CONFIG:
912 assert(va == 0);
913 pkt->set(itb->c0_config);
914 break;
915 case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0:
916 assert(va == 0);
917 pkt->set(cx_tsb_ps0);
918 break;
919 case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1:
920 assert(va == 0);
921 pkt->set(cx_tsb_ps1);
922 break;
923 case ASI_DMMU_CTXT_NONZERO_CONFIG:
924 assert(va == 0);
925 pkt->set(cx_config);
926 break;
927 case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0:
928 assert(va == 0);
929 pkt->set(itb->cx_tsb_ps0);
930 break;
931 case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1:
932 assert(va == 0);
933 pkt->set(itb->cx_tsb_ps1);
934 break;
935 case ASI_IMMU_CTXT_NONZERO_CONFIG:
936 assert(va == 0);
937 pkt->set(itb->cx_config);
938 break;
939 case ASI_SPARC_ERROR_STATUS_REG:
940 pkt->set((uint64_t)0);
941 break;
942 case ASI_HYP_SCRATCHPAD:
943 case ASI_SCRATCHPAD:
944 pkt->set(tc->readMiscReg(MISCREG_SCRATCHPAD_R0 + (va >> 3)));
945 break;
946 case ASI_IMMU:
947 switch (va) {
948 case 0x0:
949 temp = itb->tag_access;
950 pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48);
951 break;
952 case 0x18:
953 pkt->set(itb->sfsr);
954 break;
955 case 0x30:
956 pkt->set(itb->tag_access);
957 break;
958 default:
959 goto doMmuReadError;
960 }
961 break;
962 case ASI_DMMU:
963 switch (va) {
964 case 0x0:
965 temp = tag_access;
966 pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48);
967 break;
968 case 0x18:
969 pkt->set(sfsr);
970 break;
971 case 0x20:
972 pkt->set(sfar);
973 break;
974 case 0x30:
975 pkt->set(tag_access);
976 break;
977 case 0x80:
978 pkt->set(tc->readMiscReg(MISCREG_MMU_PART_ID));
979 break;
980 default:
981 goto doMmuReadError;
982 }
983 break;
984 case ASI_DMMU_TSB_PS0_PTR_REG:
985 pkt->set(MakeTsbPtr(Ps0,
986 tag_access,
987 c0_tsb_ps0,
988 c0_config,
989 cx_tsb_ps0,
990 cx_config));
991 break;
992 case ASI_DMMU_TSB_PS1_PTR_REG:
993 pkt->set(MakeTsbPtr(Ps1,
994 tag_access,
995 c0_tsb_ps1,
996 c0_config,
997 cx_tsb_ps1,
998 cx_config));
999 break;
1000 case ASI_IMMU_TSB_PS0_PTR_REG:
1001 pkt->set(MakeTsbPtr(Ps0,
1002 itb->tag_access,
1003 itb->c0_tsb_ps0,
1004 itb->c0_config,
1005 itb->cx_tsb_ps0,
1006 itb->cx_config));
1007 break;
1008 case ASI_IMMU_TSB_PS1_PTR_REG:
1009 pkt->set(MakeTsbPtr(Ps1,
1010 itb->tag_access,
1011 itb->c0_tsb_ps1,
1012 itb->c0_config,
1013 itb->cx_tsb_ps1,
1014 itb->cx_config));
1015 break;
1016 case ASI_SWVR_INTR_RECEIVE:
1017 {
1018 SparcISA::Interrupts * interrupts =
1019 dynamic_cast<SparcISA::Interrupts *>(
1020 tc->getCpuPtr()->getInterruptController(0));
1021 pkt->set(interrupts->get_vec(IT_INT_VEC));
1022 }
1023 break;
1024 case ASI_SWVR_UDB_INTR_R:
1025 {
1026 SparcISA::Interrupts * interrupts =
1027 dynamic_cast<SparcISA::Interrupts *>(
1028 tc->getCpuPtr()->getInterruptController(0));
1029 temp = findMsbSet(interrupts->get_vec(IT_INT_VEC));
1030 tc->getCpuPtr()->clearInterrupt(0, IT_INT_VEC, temp);
1031 pkt->set(temp);
1032 }
1033 break;
1034 default:
1035doMmuReadError:
1036 panic("need to impl DTB::doMmuRegRead() got asi=%#x, va=%#x\n",
1037 (uint32_t)asi, va);
1038 }
1039 pkt->makeAtomicResponse();
1040 return Cycles(1);
1041}
1042
1043Cycles
1044TLB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
1045{
1046 uint64_t data = pkt->get<uint64_t>();
1047 Addr va = pkt->getAddr();
1048 ASI asi = (ASI)pkt->req->getArchFlags();
1049
1050 Addr ta_insert;
1051 Addr va_insert;
1052 Addr ct_insert;
1053 int part_insert;
1054 int entry_insert = -1;
1055 bool real_insert;
1056 bool ignore;
1057 int part_id;
1058 int ctx_id;
1059 PageTableEntry pte;
1060
1061 DPRINTF(IPR, "Memory Mapped IPR Write: asi=%#X a=%#x d=%#X\n",
1062 (uint32_t)asi, va, data);
1063
1064 TLB *itb = dynamic_cast<TLB *>(tc->getITBPtr());
1065
1066 switch (asi) {
1067 case ASI_LSU_CONTROL_REG:
1068 assert(va == 0);
1069 tc->setMiscReg(MISCREG_MMU_LSU_CTRL, data);
1070 break;
1071 case ASI_MMU:
1072 switch (va) {
1073 case 0x8:
1074 tc->setMiscReg(MISCREG_MMU_P_CONTEXT, data);
1075 break;
1076 case 0x10:
1077 tc->setMiscReg(MISCREG_MMU_S_CONTEXT, data);
1078 break;
1079 default:
1080 goto doMmuWriteError;
1081 }
1082 break;
1083 case ASI_QUEUE:
1084 assert(mbits(data,13,6) == data);
1085 tc->setMiscReg(MISCREG_QUEUE_CPU_MONDO_HEAD +
1086 (va >> 4) - 0x3c, data);
1087 break;
1088 case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0:
1089 assert(va == 0);
1090 c0_tsb_ps0 = data;
1091 break;
1092 case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1:
1093 assert(va == 0);
1094 c0_tsb_ps1 = data;
1095 break;
1096 case ASI_DMMU_CTXT_ZERO_CONFIG:
1097 assert(va == 0);
1098 c0_config = data;
1099 break;
1100 case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0:
1101 assert(va == 0);
1102 itb->c0_tsb_ps0 = data;
1103 break;
1104 case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1:
1105 assert(va == 0);
1106 itb->c0_tsb_ps1 = data;
1107 break;
1108 case ASI_IMMU_CTXT_ZERO_CONFIG:
1109 assert(va == 0);
1110 itb->c0_config = data;
1111 break;
1112 case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0:
1113 assert(va == 0);
1114 cx_tsb_ps0 = data;
1115 break;
1116 case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1:
1117 assert(va == 0);
1118 cx_tsb_ps1 = data;
1119 break;
1120 case ASI_DMMU_CTXT_NONZERO_CONFIG:
1121 assert(va == 0);
1122 cx_config = data;
1123 break;
1124 case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0:
1125 assert(va == 0);
1126 itb->cx_tsb_ps0 = data;
1127 break;
1128 case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1:
1129 assert(va == 0);
1130 itb->cx_tsb_ps1 = data;
1131 break;
1132 case ASI_IMMU_CTXT_NONZERO_CONFIG:
1133 assert(va == 0);
1134 itb->cx_config = data;
1135 break;
1136 case ASI_SPARC_ERROR_EN_REG:
1137 case ASI_SPARC_ERROR_STATUS_REG:
1138 inform("Ignoring write to SPARC ERROR regsiter\n");
1139 break;
1140 case ASI_HYP_SCRATCHPAD:
1141 case ASI_SCRATCHPAD:
1142 tc->setMiscReg(MISCREG_SCRATCHPAD_R0 + (va >> 3), data);
1143 break;
1144 case ASI_IMMU:
1145 switch (va) {
1146 case 0x18:
1147 itb->sfsr = data;
1148 break;
1149 case 0x30:
1150 sext<59>(bits(data, 59,0));
1151 itb->tag_access = data;
1152 break;
1153 default:
1154 goto doMmuWriteError;
1155 }
1156 break;
1157 case ASI_ITLB_DATA_ACCESS_REG:
1158 entry_insert = bits(va, 8,3);
|
1172 case ASI_DTLB_DATA_IN_REG:
1173 assert(entry_insert != -1 || mbits(va,10,9) == va);
1174 ta_insert = tag_access;
1175 va_insert = mbits(ta_insert, 63,13);
1176 ct_insert = mbits(ta_insert, 12,0);
1177 part_insert = tc->readMiscReg(MISCREG_MMU_PART_ID);
1178 real_insert = bits(va, 9,9);
1179 pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v :
1180 PageTableEntry::sun4u);
1181 insert(va_insert, part_insert, ct_insert, real_insert, pte,
1182 entry_insert);
1183 break;
1184 case ASI_IMMU_DEMAP:
1185 ignore = false;
1186 ctx_id = -1;
1187 part_id = tc->readMiscReg(MISCREG_MMU_PART_ID);
1188 switch (bits(va,5,4)) {
1189 case 0:
1190 ctx_id = tc->readMiscReg(MISCREG_MMU_P_CONTEXT);
1191 break;
1192 case 1:
1193 ignore = true;
1194 break;
1195 case 3:
1196 ctx_id = 0;
1197 break;
1198 default:
1199 ignore = true;
1200 }
1201
1202 switch (bits(va,7,6)) {
1203 case 0: // demap page
1204 if (!ignore)
1205 itb->demapPage(mbits(va,63,13), part_id, bits(va,9,9), ctx_id);
1206 break;
1207 case 1: // demap context
1208 if (!ignore)
1209 itb->demapContext(part_id, ctx_id);
1210 break;
1211 case 2:
1212 itb->demapAll(part_id);
1213 break;
1214 default:
1215 panic("Invalid type for IMMU demap\n");
1216 }
1217 break;
1218 case ASI_DMMU:
1219 switch (va) {
1220 case 0x18:
1221 sfsr = data;
1222 break;
1223 case 0x30:
1224 sext<59>(bits(data, 59,0));
1225 tag_access = data;
1226 break;
1227 case 0x80:
1228 tc->setMiscReg(MISCREG_MMU_PART_ID, data);
1229 break;
1230 default:
1231 goto doMmuWriteError;
1232 }
1233 break;
1234 case ASI_DMMU_DEMAP:
1235 ignore = false;
1236 ctx_id = -1;
1237 part_id = tc->readMiscReg(MISCREG_MMU_PART_ID);
1238 switch (bits(va,5,4)) {
1239 case 0:
1240 ctx_id = tc->readMiscReg(MISCREG_MMU_P_CONTEXT);
1241 break;
1242 case 1:
1243 ctx_id = tc->readMiscReg(MISCREG_MMU_S_CONTEXT);
1244 break;
1245 case 3:
1246 ctx_id = 0;
1247 break;
1248 default:
1249 ignore = true;
1250 }
1251
1252 switch (bits(va,7,6)) {
1253 case 0: // demap page
1254 if (!ignore)
1255 demapPage(mbits(va,63,13), part_id, bits(va,9,9), ctx_id);
1256 break;
1257 case 1: // demap context
1258 if (!ignore)
1259 demapContext(part_id, ctx_id);
1260 break;
1261 case 2:
1262 demapAll(part_id);
1263 break;
1264 default:
1265 panic("Invalid type for IMMU demap\n");
1266 }
1267 break;
1268 case ASI_SWVR_INTR_RECEIVE:
1269 {
1270 int msb;
1271 // clear all the interrupts that aren't set in the write
1272 SparcISA::Interrupts * interrupts =
1273 dynamic_cast<SparcISA::Interrupts *>(
1274 tc->getCpuPtr()->getInterruptController(0));
1275 while (interrupts->get_vec(IT_INT_VEC) & data) {
1276 msb = findMsbSet(interrupts->get_vec(IT_INT_VEC) & data);
1277 tc->getCpuPtr()->clearInterrupt(0, IT_INT_VEC, msb);
1278 }
1279 }
1280 break;
1281 case ASI_SWVR_UDB_INTR_W:
1282 tc->getSystemPtr()->threadContexts[bits(data,12,8)]->getCpuPtr()->
1283 postInterrupt(0, bits(data, 5, 0), 0);
1284 break;
1285 default:
1286doMmuWriteError:
1287 panic("need to impl DTB::doMmuRegWrite() got asi=%#x, va=%#x d=%#x\n",
1288 (uint32_t)pkt->req->getArchFlags(), pkt->getAddr(), data);
1289 }
1290 pkt->makeAtomicResponse();
1291 return Cycles(1);
1292}
1293
1294void
1295TLB::GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs)
1296{
1297 uint64_t tag_access = mbits(addr,63,13) | mbits(ctx,12,0);
1298 TLB *itb = dynamic_cast<TLB *>(tc->getITBPtr());
1299 ptrs[0] = MakeTsbPtr(Ps0, tag_access,
1300 c0_tsb_ps0,
1301 c0_config,
1302 cx_tsb_ps0,
1303 cx_config);
1304 ptrs[1] = MakeTsbPtr(Ps1, tag_access,
1305 c0_tsb_ps1,
1306 c0_config,
1307 cx_tsb_ps1,
1308 cx_config);
1309 ptrs[2] = MakeTsbPtr(Ps0, tag_access,
1310 itb->c0_tsb_ps0,
1311 itb->c0_config,
1312 itb->cx_tsb_ps0,
1313 itb->cx_config);
1314 ptrs[3] = MakeTsbPtr(Ps1, tag_access,
1315 itb->c0_tsb_ps1,
1316 itb->c0_config,
1317 itb->cx_tsb_ps1,
1318 itb->cx_config);
1319}
1320
1321uint64_t
1322TLB::MakeTsbPtr(TsbPageSize ps, uint64_t tag_access, uint64_t c0_tsb,
1323 uint64_t c0_config, uint64_t cX_tsb, uint64_t cX_config)
1324{
1325 uint64_t tsb;
1326 uint64_t config;
1327
1328 if (bits(tag_access, 12,0) == 0) {
1329 tsb = c0_tsb;
1330 config = c0_config;
1331 } else {
1332 tsb = cX_tsb;
1333 config = cX_config;
1334 }
1335
1336 uint64_t ptr = mbits(tsb,63,13);
1337 bool split = bits(tsb,12,12);
1338 int tsb_size = bits(tsb,3,0);
1339 int page_size = (ps == Ps0) ? bits(config, 2,0) : bits(config,10,8);
1340
1341 if (ps == Ps1 && split)
1342 ptr |= ULL(1) << (13 + tsb_size);
1343 ptr |= (tag_access >> (9 + page_size * 3)) & mask(12+tsb_size, 4);
1344
1345 return ptr;
1346}
1347
1348void
1349TLB::serialize(CheckpointOut &cp) const
1350{
1351 SERIALIZE_SCALAR(size);
1352 SERIALIZE_SCALAR(usedEntries);
1353 SERIALIZE_SCALAR(lastReplaced);
1354
1355 // convert the pointer based free list into an index based one
1356 std::vector<int> free_list;
1357 for (const TlbEntry *entry : freeList)
1358 free_list.push_back(entry - tlb);
1359
1360 SERIALIZE_CONTAINER(free_list);
1361
1362 SERIALIZE_SCALAR(c0_tsb_ps0);
1363 SERIALIZE_SCALAR(c0_tsb_ps1);
1364 SERIALIZE_SCALAR(c0_config);
1365 SERIALIZE_SCALAR(cx_tsb_ps0);
1366 SERIALIZE_SCALAR(cx_tsb_ps1);
1367 SERIALIZE_SCALAR(cx_config);
1368 SERIALIZE_SCALAR(sfsr);
1369 SERIALIZE_SCALAR(tag_access);
1370 SERIALIZE_SCALAR(sfar);
1371
1372 for (int x = 0; x < size; x++) {
1373 ScopedCheckpointSection sec(cp, csprintf("PTE%d", x));
1374 tlb[x].serialize(cp);
1375 }
1376}
1377
1378void
1379TLB::unserialize(CheckpointIn &cp)
1380{
1381 int oldSize;
1382
1383 paramIn(cp, "size", oldSize);
1384 if (oldSize != size)
1385 panic("Don't support unserializing different sized TLBs\n");
1386 UNSERIALIZE_SCALAR(usedEntries);
1387 UNSERIALIZE_SCALAR(lastReplaced);
1388
1389 std::vector<int> free_list;
1390 UNSERIALIZE_CONTAINER(free_list);
1391 freeList.clear();
1392 for (int idx : free_list)
1393 freeList.push_back(&tlb[idx]);
1394
1395 UNSERIALIZE_SCALAR(c0_tsb_ps0);
1396 UNSERIALIZE_SCALAR(c0_tsb_ps1);
1397 UNSERIALIZE_SCALAR(c0_config);
1398 UNSERIALIZE_SCALAR(cx_tsb_ps0);
1399 UNSERIALIZE_SCALAR(cx_tsb_ps1);
1400 UNSERIALIZE_SCALAR(cx_config);
1401 UNSERIALIZE_SCALAR(sfsr);
1402 UNSERIALIZE_SCALAR(tag_access);
1403
1404 lookupTable.clear();
1405 for (int x = 0; x < size; x++) {
1406 ScopedCheckpointSection sec(cp, csprintf("PTE%d", x));
1407 tlb[x].unserialize(cp);
1408 if (tlb[x].valid)
1409 lookupTable.insert(tlb[x].range, &tlb[x]);
1410
1411 }
1412 UNSERIALIZE_SCALAR(sfar);
1413}
1414
1415} // namespace SparcISA
1416
1417SparcISA::TLB *
1418SparcTLBParams::create()
1419{
1420 return new SparcISA::TLB(this);
1421}
| 1175 case ASI_DTLB_DATA_IN_REG:
1176 assert(entry_insert != -1 || mbits(va,10,9) == va);
1177 ta_insert = tag_access;
1178 va_insert = mbits(ta_insert, 63,13);
1179 ct_insert = mbits(ta_insert, 12,0);
1180 part_insert = tc->readMiscReg(MISCREG_MMU_PART_ID);
1181 real_insert = bits(va, 9,9);
1182 pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v :
1183 PageTableEntry::sun4u);
1184 insert(va_insert, part_insert, ct_insert, real_insert, pte,
1185 entry_insert);
1186 break;
1187 case ASI_IMMU_DEMAP:
1188 ignore = false;
1189 ctx_id = -1;
1190 part_id = tc->readMiscReg(MISCREG_MMU_PART_ID);
1191 switch (bits(va,5,4)) {
1192 case 0:
1193 ctx_id = tc->readMiscReg(MISCREG_MMU_P_CONTEXT);
1194 break;
1195 case 1:
1196 ignore = true;
1197 break;
1198 case 3:
1199 ctx_id = 0;
1200 break;
1201 default:
1202 ignore = true;
1203 }
1204
1205 switch (bits(va,7,6)) {
1206 case 0: // demap page
1207 if (!ignore)
1208 itb->demapPage(mbits(va,63,13), part_id, bits(va,9,9), ctx_id);
1209 break;
1210 case 1: // demap context
1211 if (!ignore)
1212 itb->demapContext(part_id, ctx_id);
1213 break;
1214 case 2:
1215 itb->demapAll(part_id);
1216 break;
1217 default:
1218 panic("Invalid type for IMMU demap\n");
1219 }
1220 break;
1221 case ASI_DMMU:
1222 switch (va) {
1223 case 0x18:
1224 sfsr = data;
1225 break;
1226 case 0x30:
1227 sext<59>(bits(data, 59,0));
1228 tag_access = data;
1229 break;
1230 case 0x80:
1231 tc->setMiscReg(MISCREG_MMU_PART_ID, data);
1232 break;
1233 default:
1234 goto doMmuWriteError;
1235 }
1236 break;
1237 case ASI_DMMU_DEMAP:
1238 ignore = false;
1239 ctx_id = -1;
1240 part_id = tc->readMiscReg(MISCREG_MMU_PART_ID);
1241 switch (bits(va,5,4)) {
1242 case 0:
1243 ctx_id = tc->readMiscReg(MISCREG_MMU_P_CONTEXT);
1244 break;
1245 case 1:
1246 ctx_id = tc->readMiscReg(MISCREG_MMU_S_CONTEXT);
1247 break;
1248 case 3:
1249 ctx_id = 0;
1250 break;
1251 default:
1252 ignore = true;
1253 }
1254
1255 switch (bits(va,7,6)) {
1256 case 0: // demap page
1257 if (!ignore)
1258 demapPage(mbits(va,63,13), part_id, bits(va,9,9), ctx_id);
1259 break;
1260 case 1: // demap context
1261 if (!ignore)
1262 demapContext(part_id, ctx_id);
1263 break;
1264 case 2:
1265 demapAll(part_id);
1266 break;
1267 default:
1268 panic("Invalid type for IMMU demap\n");
1269 }
1270 break;
1271 case ASI_SWVR_INTR_RECEIVE:
1272 {
1273 int msb;
1274 // clear all the interrupts that aren't set in the write
1275 SparcISA::Interrupts * interrupts =
1276 dynamic_cast<SparcISA::Interrupts *>(
1277 tc->getCpuPtr()->getInterruptController(0));
1278 while (interrupts->get_vec(IT_INT_VEC) & data) {
1279 msb = findMsbSet(interrupts->get_vec(IT_INT_VEC) & data);
1280 tc->getCpuPtr()->clearInterrupt(0, IT_INT_VEC, msb);
1281 }
1282 }
1283 break;
1284 case ASI_SWVR_UDB_INTR_W:
1285 tc->getSystemPtr()->threadContexts[bits(data,12,8)]->getCpuPtr()->
1286 postInterrupt(0, bits(data, 5, 0), 0);
1287 break;
1288 default:
1289doMmuWriteError:
1290 panic("need to impl DTB::doMmuRegWrite() got asi=%#x, va=%#x d=%#x\n",
1291 (uint32_t)pkt->req->getArchFlags(), pkt->getAddr(), data);
1292 }
1293 pkt->makeAtomicResponse();
1294 return Cycles(1);
1295}
1296
1297void
1298TLB::GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs)
1299{
1300 uint64_t tag_access = mbits(addr,63,13) | mbits(ctx,12,0);
1301 TLB *itb = dynamic_cast<TLB *>(tc->getITBPtr());
1302 ptrs[0] = MakeTsbPtr(Ps0, tag_access,
1303 c0_tsb_ps0,
1304 c0_config,
1305 cx_tsb_ps0,
1306 cx_config);
1307 ptrs[1] = MakeTsbPtr(Ps1, tag_access,
1308 c0_tsb_ps1,
1309 c0_config,
1310 cx_tsb_ps1,
1311 cx_config);
1312 ptrs[2] = MakeTsbPtr(Ps0, tag_access,
1313 itb->c0_tsb_ps0,
1314 itb->c0_config,
1315 itb->cx_tsb_ps0,
1316 itb->cx_config);
1317 ptrs[3] = MakeTsbPtr(Ps1, tag_access,
1318 itb->c0_tsb_ps1,
1319 itb->c0_config,
1320 itb->cx_tsb_ps1,
1321 itb->cx_config);
1322}
1323
1324uint64_t
1325TLB::MakeTsbPtr(TsbPageSize ps, uint64_t tag_access, uint64_t c0_tsb,
1326 uint64_t c0_config, uint64_t cX_tsb, uint64_t cX_config)
1327{
1328 uint64_t tsb;
1329 uint64_t config;
1330
1331 if (bits(tag_access, 12,0) == 0) {
1332 tsb = c0_tsb;
1333 config = c0_config;
1334 } else {
1335 tsb = cX_tsb;
1336 config = cX_config;
1337 }
1338
1339 uint64_t ptr = mbits(tsb,63,13);
1340 bool split = bits(tsb,12,12);
1341 int tsb_size = bits(tsb,3,0);
1342 int page_size = (ps == Ps0) ? bits(config, 2,0) : bits(config,10,8);
1343
1344 if (ps == Ps1 && split)
1345 ptr |= ULL(1) << (13 + tsb_size);
1346 ptr |= (tag_access >> (9 + page_size * 3)) & mask(12+tsb_size, 4);
1347
1348 return ptr;
1349}
1350
1351void
1352TLB::serialize(CheckpointOut &cp) const
1353{
1354 SERIALIZE_SCALAR(size);
1355 SERIALIZE_SCALAR(usedEntries);
1356 SERIALIZE_SCALAR(lastReplaced);
1357
1358 // convert the pointer based free list into an index based one
1359 std::vector<int> free_list;
1360 for (const TlbEntry *entry : freeList)
1361 free_list.push_back(entry - tlb);
1362
1363 SERIALIZE_CONTAINER(free_list);
1364
1365 SERIALIZE_SCALAR(c0_tsb_ps0);
1366 SERIALIZE_SCALAR(c0_tsb_ps1);
1367 SERIALIZE_SCALAR(c0_config);
1368 SERIALIZE_SCALAR(cx_tsb_ps0);
1369 SERIALIZE_SCALAR(cx_tsb_ps1);
1370 SERIALIZE_SCALAR(cx_config);
1371 SERIALIZE_SCALAR(sfsr);
1372 SERIALIZE_SCALAR(tag_access);
1373 SERIALIZE_SCALAR(sfar);
1374
1375 for (int x = 0; x < size; x++) {
1376 ScopedCheckpointSection sec(cp, csprintf("PTE%d", x));
1377 tlb[x].serialize(cp);
1378 }
1379}
1380
1381void
1382TLB::unserialize(CheckpointIn &cp)
1383{
1384 int oldSize;
1385
1386 paramIn(cp, "size", oldSize);
1387 if (oldSize != size)
1388 panic("Don't support unserializing different sized TLBs\n");
1389 UNSERIALIZE_SCALAR(usedEntries);
1390 UNSERIALIZE_SCALAR(lastReplaced);
1391
1392 std::vector<int> free_list;
1393 UNSERIALIZE_CONTAINER(free_list);
1394 freeList.clear();
1395 for (int idx : free_list)
1396 freeList.push_back(&tlb[idx]);
1397
1398 UNSERIALIZE_SCALAR(c0_tsb_ps0);
1399 UNSERIALIZE_SCALAR(c0_tsb_ps1);
1400 UNSERIALIZE_SCALAR(c0_config);
1401 UNSERIALIZE_SCALAR(cx_tsb_ps0);
1402 UNSERIALIZE_SCALAR(cx_tsb_ps1);
1403 UNSERIALIZE_SCALAR(cx_config);
1404 UNSERIALIZE_SCALAR(sfsr);
1405 UNSERIALIZE_SCALAR(tag_access);
1406
1407 lookupTable.clear();
1408 for (int x = 0; x < size; x++) {
1409 ScopedCheckpointSection sec(cp, csprintf("PTE%d", x));
1410 tlb[x].unserialize(cp);
1411 if (tlb[x].valid)
1412 lookupTable.insert(tlb[x].range, &tlb[x]);
1413
1414 }
1415 UNSERIALIZE_SCALAR(sfar);
1416}
1417
1418} // namespace SparcISA
1419
1420SparcISA::TLB *
1421SparcTLBParams::create()
1422{
1423 return new SparcISA::TLB(this);
1424}
|