tlb.cc (9738:304a37519d11) | tlb.cc (9912:3de4393f5649) |
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1/* 2 * Copyright (c) 2001-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 406 unchanged lines hidden (view full) --- 415Fault 416TLB::translateInst(RequestPtr req, ThreadContext *tc) 417{ 418 uint64_t tlbdata = tc->readMiscRegNoEffect(MISCREG_TLB_DATA); 419 420 Addr vaddr = req->getVaddr(); 421 TlbEntry *e; 422 | 1/* 2 * Copyright (c) 2001-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 406 unchanged lines hidden (view full) --- 415Fault 416TLB::translateInst(RequestPtr req, ThreadContext *tc) 417{ 418 uint64_t tlbdata = tc->readMiscRegNoEffect(MISCREG_TLB_DATA); 419 420 Addr vaddr = req->getVaddr(); 421 TlbEntry *e; 422 |
423 assert(req->getAsi() == ASI_IMPLICIT); | 423 assert(req->getArchFlags() == ASI_IMPLICIT); |
424 425 DPRINTF(TLB, "TLB: ITB Request to translate va=%#x size=%d\n", 426 vaddr, req->getSize()); 427 428 // Be fast if we can! 429 if (cacheValid && cacheState == tlbdata) { 430 if (cacheEntry[0]) { 431 if (cacheEntry[0]->range.va < vaddr + sizeof(MachInst) && --- 99 unchanged lines hidden (view full) --- 531 /* 532 * @todo this could really use some profiling and fixing to make 533 * it faster! 534 */ 535 uint64_t tlbdata = tc->readMiscRegNoEffect(MISCREG_TLB_DATA); 536 Addr vaddr = req->getVaddr(); 537 Addr size = req->getSize(); 538 ASI asi; | 424 425 DPRINTF(TLB, "TLB: ITB Request to translate va=%#x size=%d\n", 426 vaddr, req->getSize()); 427 428 // Be fast if we can! 429 if (cacheValid && cacheState == tlbdata) { 430 if (cacheEntry[0]) { 431 if (cacheEntry[0]->range.va < vaddr + sizeof(MachInst) && --- 99 unchanged lines hidden (view full) --- 531 /* 532 * @todo this could really use some profiling and fixing to make 533 * it faster! 534 */ 535 uint64_t tlbdata = tc->readMiscRegNoEffect(MISCREG_TLB_DATA); 536 Addr vaddr = req->getVaddr(); 537 Addr size = req->getSize(); 538 ASI asi; |
539 asi = (ASI)req->getAsi(); | 539 asi = (ASI)req->getArchFlags(); |
540 bool implicit = false; 541 bool hpriv = bits(tlbdata,0,0); 542 bool unaligned = vaddr & (size - 1); 543 544 DPRINTF(TLB, "TLB: DTB Request to translate va=%#x size=%d asi=%#x\n", 545 vaddr, size, asi); 546 547 if (lookupTable.size() != 64 - freeList.size()) --- 305 unchanged lines hidden (view full) --- 853{ 854 return NoFault; 855} 856 857Cycles 858TLB::doMmuRegRead(ThreadContext *tc, Packet *pkt) 859{ 860 Addr va = pkt->getAddr(); | 540 bool implicit = false; 541 bool hpriv = bits(tlbdata,0,0); 542 bool unaligned = vaddr & (size - 1); 543 544 DPRINTF(TLB, "TLB: DTB Request to translate va=%#x size=%d asi=%#x\n", 545 vaddr, size, asi); 546 547 if (lookupTable.size() != 64 - freeList.size()) --- 305 unchanged lines hidden (view full) --- 853{ 854 return NoFault; 855} 856 857Cycles 858TLB::doMmuRegRead(ThreadContext *tc, Packet *pkt) 859{ 860 Addr va = pkt->getAddr(); |
861 ASI asi = (ASI)pkt->req->getAsi(); | 861 ASI asi = (ASI)pkt->req->getArchFlags(); |
862 uint64_t temp; 863 864 DPRINTF(IPR, "Memory Mapped IPR Read: asi=%#X a=%#x\n", | 862 uint64_t temp; 863 864 DPRINTF(IPR, "Memory Mapped IPR Read: asi=%#X a=%#x\n", |
865 (uint32_t)pkt->req->getAsi(), pkt->getAddr()); | 865 (uint32_t)pkt->req->getArchFlags(), pkt->getAddr()); |
866 867 TLB *itb = tc->getITBPtr(); 868 869 switch (asi) { 870 case ASI_LSU_CONTROL_REG: 871 assert(va == 0); 872 pkt->set(tc->readMiscReg(MISCREG_MMU_LSU_CTRL)); 873 break; --- 165 unchanged lines hidden (view full) --- 1039 return Cycles(1); 1040} 1041 1042Cycles 1043TLB::doMmuRegWrite(ThreadContext *tc, Packet *pkt) 1044{ 1045 uint64_t data = pkt->get<uint64_t>(); 1046 Addr va = pkt->getAddr(); | 866 867 TLB *itb = tc->getITBPtr(); 868 869 switch (asi) { 870 case ASI_LSU_CONTROL_REG: 871 assert(va == 0); 872 pkt->set(tc->readMiscReg(MISCREG_MMU_LSU_CTRL)); 873 break; --- 165 unchanged lines hidden (view full) --- 1039 return Cycles(1); 1040} 1041 1042Cycles 1043TLB::doMmuRegWrite(ThreadContext *tc, Packet *pkt) 1044{ 1045 uint64_t data = pkt->get<uint64_t>(); 1046 Addr va = pkt->getAddr(); |
1047 ASI asi = (ASI)pkt->req->getAsi(); | 1047 ASI asi = (ASI)pkt->req->getArchFlags(); |
1048 1049 Addr ta_insert; 1050 Addr va_insert; 1051 Addr ct_insert; 1052 int part_insert; 1053 int entry_insert = -1; 1054 bool real_insert; 1055 bool ignore; --- 225 unchanged lines hidden (view full) --- 1281 break; 1282 case ASI_SWVR_UDB_INTR_W: 1283 tc->getSystemPtr()->threadContexts[bits(data,12,8)]->getCpuPtr()-> 1284 postInterrupt(bits(data, 5, 0), 0); 1285 break; 1286 default: 1287doMmuWriteError: 1288 panic("need to impl DTB::doMmuRegWrite() got asi=%#x, va=%#x d=%#x\n", | 1048 1049 Addr ta_insert; 1050 Addr va_insert; 1051 Addr ct_insert; 1052 int part_insert; 1053 int entry_insert = -1; 1054 bool real_insert; 1055 bool ignore; --- 225 unchanged lines hidden (view full) --- 1281 break; 1282 case ASI_SWVR_UDB_INTR_W: 1283 tc->getSystemPtr()->threadContexts[bits(data,12,8)]->getCpuPtr()-> 1284 postInterrupt(bits(data, 5, 0), 0); 1285 break; 1286 default: 1287doMmuWriteError: 1288 panic("need to impl DTB::doMmuRegWrite() got asi=%#x, va=%#x d=%#x\n", |
1289 (uint32_t)pkt->req->getAsi(), pkt->getAddr(), data); | 1289 (uint32_t)pkt->req->getArchFlags(), pkt->getAddr(), data); |
1290 } 1291 pkt->makeAtomicResponse(); 1292 return Cycles(1); 1293} 1294 1295void 1296TLB::GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs) 1297{ --- 132 unchanged lines hidden --- | 1290 } 1291 pkt->makeAtomicResponse(); 1292 return Cycles(1); 1293} 1294 1295void 1296TLB::GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs) 1297{ --- 132 unchanged lines hidden --- |