tlb.cc (4918:3214e3694fb2) | tlb.cc (4989:3e9d532cf998) |
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1/* 2 * Copyright (c) 2001-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 586 unchanged lines hidden (view full) --- 595 return NoFault; 596 } 597 598 // Be fast if we can! 599 if (cacheValid && cacheState == tlbdata) { 600 601 602 | 1/* 2 * Copyright (c) 2001-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 586 unchanged lines hidden (view full) --- 595 return NoFault; 596 } 597 598 // Be fast if we can! 599 if (cacheValid && cacheState == tlbdata) { 600 601 602 |
603 if (cacheEntry[0]) { | 603 if (cacheEntry[0]) { |
604 TlbEntry *ce = cacheEntry[0]; | 604 TlbEntry *ce = cacheEntry[0]; |
605 Addr ce_va = ce->range.va; | 605 Addr ce_va = ce->range.va; |
606 if (cacheAsi[0] == asi && 607 ce_va < vaddr + size && ce_va + ce->range.size > vaddr && 608 (!write || ce->pte.writable())) { 609 req->setPaddr(ce->pte.paddrMask() | vaddr & ce->pte.sizeMask()); 610 if (ce->pte.sideffect() || (ce->pte.paddr() >> 39) & 1) 611 req->setFlags(req->getFlags() | UNCACHEABLE); 612 DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr()); 613 return NoFault; --- 69 unchanged lines hidden (view full) --- 683 ct = Primary; 684 context = pri_context; 685 } 686 } 687 688 if (!implicit && asi != ASI_P && asi != ASI_S) { 689 if (AsiIsLittle(asi)) 690 panic("Little Endian ASIs not supported\n"); | 606 if (cacheAsi[0] == asi && 607 ce_va < vaddr + size && ce_va + ce->range.size > vaddr && 608 (!write || ce->pte.writable())) { 609 req->setPaddr(ce->pte.paddrMask() | vaddr & ce->pte.sizeMask()); 610 if (ce->pte.sideffect() || (ce->pte.paddr() >> 39) & 1) 611 req->setFlags(req->getFlags() | UNCACHEABLE); 612 DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr()); 613 return NoFault; --- 69 unchanged lines hidden (view full) --- 683 ct = Primary; 684 context = pri_context; 685 } 686 } 687 688 if (!implicit && asi != ASI_P && asi != ASI_S) { 689 if (AsiIsLittle(asi)) 690 panic("Little Endian ASIs not supported\n"); |
691 if (AsiIsNoFault(asi)) 692 panic("No Fault ASIs not supported\n"); | |
693 | 691 |
692 //XXX It's unclear from looking at the documentation how a no fault 693 //load differs from a regular one, other than what happens concerning 694 //nfo and e bits in the TTE 695// if (AsiIsNoFault(asi)) 696// panic("No Fault ASIs not supported\n"); 697 |
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694 if (AsiIsPartialStore(asi)) 695 panic("Partial Store ASIs not supported\n"); 696 697 if (AsiIsCmt(asi)) 698 panic("Cmt ASI registers not implmented\n"); 699 700 if (AsiIsInterrupt(asi)) 701 goto handleIntRegAccess; 702 if (AsiIsMmu(asi)) 703 goto handleMmuRegAccess; 704 if (AsiIsScratchPad(asi)) 705 goto handleScratchRegAccess; 706 if (AsiIsQueue(asi)) 707 goto handleQueueRegAccess; 708 if (AsiIsSparcError(asi)) 709 goto handleSparcErrorRegAccess; 710 711 if (!AsiIsReal(asi) && !AsiIsNucleus(asi) && !AsiIsAsIfUser(asi) && | 698 if (AsiIsPartialStore(asi)) 699 panic("Partial Store ASIs not supported\n"); 700 701 if (AsiIsCmt(asi)) 702 panic("Cmt ASI registers not implmented\n"); 703 704 if (AsiIsInterrupt(asi)) 705 goto handleIntRegAccess; 706 if (AsiIsMmu(asi)) 707 goto handleMmuRegAccess; 708 if (AsiIsScratchPad(asi)) 709 goto handleScratchRegAccess; 710 if (AsiIsQueue(asi)) 711 goto handleQueueRegAccess; 712 if (AsiIsSparcError(asi)) 713 goto handleSparcErrorRegAccess; 714 715 if (!AsiIsReal(asi) && !AsiIsNucleus(asi) && !AsiIsAsIfUser(asi) && |
712 !AsiIsTwin(asi) && !AsiIsBlock(asi)) | 716 !AsiIsTwin(asi) && !AsiIsBlock(asi) && !AsiIsNoFault(asi)) |
713 panic("Accessing ASI %#X. Should we?\n", asi); 714 } 715 716 // If the asi is unaligned trap 717 if (vaddr & size-1) { 718 writeSfr(tc, vaddr, false, ct, false, OtherFault, asi); 719 return new MemAddressNotAligned; 720 } --- 680 unchanged lines hidden --- | 717 panic("Accessing ASI %#X. Should we?\n", asi); 718 } 719 720 // If the asi is unaligned trap 721 if (vaddr & size-1) { 722 writeSfr(tc, vaddr, false, ct, false, OtherFault, asi); 723 return new MemAddressNotAligned; 724 } --- 680 unchanged lines hidden --- |