tlb.cc (3881:f06ef65cd746) | tlb.cc (3899:389e4ea5f98e) |
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1/* 2 * Copyright (c) 2001-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 611 unchanged lines hidden (view full) --- 620 writeSfr(tc, vaddr, write, Nucleus, false, IllegalAsi, asi); 621 return new PrivilegedAction; 622 } 623 if (priv && AsiIsHPriv(asi)) { 624 writeSfr(tc, vaddr, write, Nucleus, false, IllegalAsi, asi); 625 return new DataAccessException; 626 } 627 | 1/* 2 * Copyright (c) 2001-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 611 unchanged lines hidden (view full) --- 620 writeSfr(tc, vaddr, write, Nucleus, false, IllegalAsi, asi); 621 return new PrivilegedAction; 622 } 623 if (priv && AsiIsHPriv(asi)) { 624 writeSfr(tc, vaddr, write, Nucleus, false, IllegalAsi, asi); 625 return new DataAccessException; 626 } 627 |
628 } else if (hpriv) { | 628 } /*else if (hpriv) {*/ |
629 if (asi == ASI_P) { 630 ct = Primary; 631 context = pri_context; 632 goto continueDtbFlow; 633 } | 629 if (asi == ASI_P) { 630 ct = Primary; 631 context = pri_context; 632 goto continueDtbFlow; 633 } |
634 } | 634 //} |
635 636 if (!implicit) { 637 if (AsiIsLittle(asi)) 638 panic("Little Endian ASIs not supported\n"); 639 if (AsiIsBlock(asi)) 640 panic("Block ASIs not supported\n"); 641 if (AsiIsNoFault(asi)) 642 panic("No Fault ASIs not supported\n"); --- 285 unchanged lines hidden (view full) --- 928 } 929 data = mbits(tsbtemp,63,13); 930 if (bits(tsbtemp,12,12)) 931 data |= ULL(1) << (13+bits(tsbtemp,3,0)); 932 data |= temp >> (9 + bits(cnftemp,2,0) * 3) & 933 mbits((uint64_t)-1ll,12+bits(tsbtemp,3,0), 4); 934 pkt->set(data); 935 break; | 635 636 if (!implicit) { 637 if (AsiIsLittle(asi)) 638 panic("Little Endian ASIs not supported\n"); 639 if (AsiIsBlock(asi)) 640 panic("Block ASIs not supported\n"); 641 if (AsiIsNoFault(asi)) 642 panic("No Fault ASIs not supported\n"); --- 285 unchanged lines hidden (view full) --- 928 } 929 data = mbits(tsbtemp,63,13); 930 if (bits(tsbtemp,12,12)) 931 data |= ULL(1) << (13+bits(tsbtemp,3,0)); 932 data |= temp >> (9 + bits(cnftemp,2,0) * 3) & 933 mbits((uint64_t)-1ll,12+bits(tsbtemp,3,0), 4); 934 pkt->set(data); 935 break; |
936 case ASI_IMMU_TSB_PS0_PTR_REG: 937 temp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS); 938 if (bits(temp,12,0) == 0) { 939 tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS0); 940 cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG); 941 } else { 942 tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS0); 943 cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG); 944 } 945 data = mbits(tsbtemp,63,13); 946 data |= temp >> (9 + bits(cnftemp,2,0) * 3) & 947 mbits((uint64_t)-1ll,12+bits(tsbtemp,3,0), 4); 948 pkt->set(data); 949 break; 950 case ASI_IMMU_TSB_PS1_PTR_REG: 951 temp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS); 952 if (bits(temp,12,0) == 0) { 953 tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS1); 954 cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG); 955 } else { 956 tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS1); 957 cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG); 958 } 959 data = mbits(tsbtemp,63,13); 960 if (bits(tsbtemp,12,12)) 961 data |= ULL(1) << (13+bits(tsbtemp,3,0)); 962 data |= temp >> (9 + bits(cnftemp,2,0) * 3) & 963 mbits((uint64_t)-1ll,12+bits(tsbtemp,3,0), 4); 964 pkt->set(data); 965 break; |
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936 937 default: 938doMmuReadError: 939 panic("need to impl DTB::doMmuRegRead() got asi=%#x, va=%#x\n", 940 (uint32_t)asi, va); 941 } 942 pkt->result = Packet::Success; 943 return tc->getCpuPtr()->cycles(1); --- 282 unchanged lines hidden --- | 966 967 default: 968doMmuReadError: 969 panic("need to impl DTB::doMmuRegRead() got asi=%#x, va=%#x\n", 970 (uint32_t)asi, va); 971 } 972 pkt->result = Packet::Success; 973 return tc->getCpuPtr()->cycles(1); --- 282 unchanged lines hidden --- |