tlb.cc (3833:b5faabcf350e) | tlb.cc (3836:659b8c627478) |
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1/* 2 * Copyright (c) 2001-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 31 unchanged lines hidden (view full) --- 40#include "sim/builder.hh" 41 42/* @todo remove some of the magic constants. -- ali 43 * */ 44namespace SparcISA 45{ 46 47TLB::TLB(const std::string &name, int s) | 1/* 2 * Copyright (c) 2001-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 31 unchanged lines hidden (view full) --- 40#include "sim/builder.hh" 41 42/* @todo remove some of the magic constants. -- ali 43 * */ 44namespace SparcISA 45{ 46 47TLB::TLB(const std::string &name, int s) |
48 : SimObject(name), size(s) | 48 : SimObject(name), size(s), usedEntries(0), cacheValid(false) |
49{ 50 // To make this work you'll have to change the hypervisor and OS 51 if (size > 64) 52 fatal("SPARC T1 TLB registers don't support more than 64 TLB entries."); 53 54 tlb = new TlbEntry[size]; 55 memset(tlb, 0, sizeof(TlbEntry) * size); 56} --- 17 unchanged lines hidden (view full) --- 74 const PageTableEntry& PTE, int entry) 75{ 76 77 78 MapIter i; 79 TlbEntry *new_entry = NULL; 80 int x; 81 | 49{ 50 // To make this work you'll have to change the hypervisor and OS 51 if (size > 64) 52 fatal("SPARC T1 TLB registers don't support more than 64 TLB entries."); 53 54 tlb = new TlbEntry[size]; 55 memset(tlb, 0, sizeof(TlbEntry) * size); 56} --- 17 unchanged lines hidden (view full) --- 74 const PageTableEntry& PTE, int entry) 75{ 76 77 78 MapIter i; 79 TlbEntry *new_entry = NULL; 80 int x; 81 |
82 cacheValid = false; 83 |
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82 DPRINTF(TLB, "TLB: Inserting TLB Entry; va=%#x pa=%#x pid=%d cid=%d r=%d\n", 83 va, PTE.paddr(), partition_id, context_id, (int)real); 84 85 if (entry != -1) { 86 assert(entry < size && entry >= 0); 87 new_entry = &tlb[entry]; 88 } else { 89 for (x = 0; x < size; x++) { --- 99 unchanged lines hidden (view full) --- 189} 190 191void 192TLB::demapPage(Addr va, int partition_id, bool real, int context_id) 193{ 194 TlbRange tr; 195 MapIter i; 196 | 84 DPRINTF(TLB, "TLB: Inserting TLB Entry; va=%#x pa=%#x pid=%d cid=%d r=%d\n", 85 va, PTE.paddr(), partition_id, context_id, (int)real); 86 87 if (entry != -1) { 88 assert(entry < size && entry >= 0); 89 new_entry = &tlb[entry]; 90 } else { 91 for (x = 0; x < size; x++) { --- 99 unchanged lines hidden (view full) --- 191} 192 193void 194TLB::demapPage(Addr va, int partition_id, bool real, int context_id) 195{ 196 TlbRange tr; 197 MapIter i; 198 |
199 cacheValid = false; 200 |
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197 // Assemble full address structure 198 tr.va = va; 199 tr.size = va + MachineBytes; 200 tr.contextId = context_id; 201 tr.partitionId = partition_id; 202 tr.real = real; 203 204 // Demap any entry that conflicts --- 7 unchanged lines hidden (view full) --- 212 lookupTable.erase(i); 213 } 214} 215 216void 217TLB::demapContext(int partition_id, int context_id) 218{ 219 int x; | 201 // Assemble full address structure 202 tr.va = va; 203 tr.size = va + MachineBytes; 204 tr.contextId = context_id; 205 tr.partitionId = partition_id; 206 tr.real = real; 207 208 // Demap any entry that conflicts --- 7 unchanged lines hidden (view full) --- 216 lookupTable.erase(i); 217 } 218} 219 220void 221TLB::demapContext(int partition_id, int context_id) 222{ 223 int x; |
224 cacheValid = false; |
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220 for (x = 0; x < size; x++) { 221 if (tlb[x].range.contextId == context_id && 222 tlb[x].range.partitionId == partition_id) { 223 tlb[x].valid = false; 224 if (tlb[x].used) { 225 tlb[x].used = false; 226 usedEntries--; 227 } 228 lookupTable.erase(tlb[x].range); 229 } 230 } 231} 232 233void 234TLB::demapAll(int partition_id) 235{ 236 int x; | 225 for (x = 0; x < size; x++) { 226 if (tlb[x].range.contextId == context_id && 227 tlb[x].range.partitionId == partition_id) { 228 tlb[x].valid = false; 229 if (tlb[x].used) { 230 tlb[x].used = false; 231 usedEntries--; 232 } 233 lookupTable.erase(tlb[x].range); 234 } 235 } 236} 237 238void 239TLB::demapAll(int partition_id) 240{ 241 int x; |
242 cacheValid = false; |
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237 for (x = 0; x < size; x++) { 238 if (!tlb[x].pte.locked() && tlb[x].range.partitionId == partition_id) { 239 tlb[x].valid = false; 240 if (tlb[x].used) { 241 tlb[x].used = false; 242 usedEntries--; 243 } 244 lookupTable.erase(tlb[x].range); 245 } 246 } 247} 248 249void 250TLB::invalidateAll() 251{ 252 int x; | 243 for (x = 0; x < size; x++) { 244 if (!tlb[x].pte.locked() && tlb[x].range.partitionId == partition_id) { 245 tlb[x].valid = false; 246 if (tlb[x].used) { 247 tlb[x].used = false; 248 usedEntries--; 249 } 250 lookupTable.erase(tlb[x].range); 251 } 252 } 253} 254 255void 256TLB::invalidateAll() 257{ 258 int x; |
259 cacheValid = false; 260 |
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253 for (x = 0; x < size; x++) { 254 tlb[x].valid = false; 255 } 256 usedEntries = 0; 257} 258 259uint64_t 260TLB::TteRead(int entry) { --- 71 unchanged lines hidden (view full) --- 332 bool se, FaultTypes ft, int asi) 333{ 334 DPRINTF(TLB, "TLB: DTB Fault: A=%#x w=%d ct=%d ft=%d asi=%d\n", 335 a, (int)write, ct, ft, asi); 336 TLB::writeSfsr(tc, MISCREG_MMU_DTLB_SFSR, write, ct, se, ft, asi); 337 tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_SFAR, a); 338} 339 | 261 for (x = 0; x < size; x++) { 262 tlb[x].valid = false; 263 } 264 usedEntries = 0; 265} 266 267uint64_t 268TLB::TteRead(int entry) { --- 71 unchanged lines hidden (view full) --- 340 bool se, FaultTypes ft, int asi) 341{ 342 DPRINTF(TLB, "TLB: DTB Fault: A=%#x w=%d ct=%d ft=%d asi=%d\n", 343 a, (int)write, ct, ft, asi); 344 TLB::writeSfsr(tc, MISCREG_MMU_DTLB_SFSR, write, ct, se, ft, asi); 345 tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_SFAR, a); 346} 347 |
340 void | 348void |
341DTB::writeTagAccess(ThreadContext *tc, Addr va, int context) 342{ 343 TLB::writeTagAccess(tc, MISCREG_MMU_DTLB_TAG_ACCESS, va, context); 344} 345 346 347 348Fault 349ITB::translate(RequestPtr &req, ThreadContext *tc) 350{ 351 uint64_t tlbdata = tc->readMiscReg(MISCREG_TLB_DATA); 352 | 349DTB::writeTagAccess(ThreadContext *tc, Addr va, int context) 350{ 351 TLB::writeTagAccess(tc, MISCREG_MMU_DTLB_TAG_ACCESS, va, context); 352} 353 354 355 356Fault 357ITB::translate(RequestPtr &req, ThreadContext *tc) 358{ 359 uint64_t tlbdata = tc->readMiscReg(MISCREG_TLB_DATA); 360 |
361 Addr vaddr = req->getVaddr(); 362 TlbEntry *e; 363 364 assert(req->getAsi() == ASI_IMPLICIT); 365 366 DPRINTF(TLB, "TLB: ITB Request to translate va=%#x size=%d\n", 367 vaddr, req->getSize()); 368 369 // Be fast if we can! 370 if (cacheValid && cacheState == tlbdata) { 371 if (cacheEntry) { 372 if (cacheEntry->range.va < vaddr + sizeof(MachInst) && 373 cacheEntry->range.va + cacheEntry->range.size >= vaddr) { 374 req->setPaddr(cacheEntry->pte.paddr() & ~(cacheEntry->pte.size()-1) | 375 vaddr & cacheEntry->pte.size()-1 ); 376 return NoFault; 377 } 378 } else { 379 req->setPaddr(vaddr & PAddrImplMask); 380 return NoFault; 381 } 382 } 383 |
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353 bool hpriv = bits(tlbdata,0,0); 354 bool red = bits(tlbdata,1,1); 355 bool priv = bits(tlbdata,2,2); 356 bool addr_mask = bits(tlbdata,3,3); 357 bool lsu_im = bits(tlbdata,4,4); 358 359 int part_id = bits(tlbdata,15,8); 360 int tl = bits(tlbdata,18,16); 361 int pri_context = bits(tlbdata,47,32); | 384 bool hpriv = bits(tlbdata,0,0); 385 bool red = bits(tlbdata,1,1); 386 bool priv = bits(tlbdata,2,2); 387 bool addr_mask = bits(tlbdata,3,3); 388 bool lsu_im = bits(tlbdata,4,4); 389 390 int part_id = bits(tlbdata,15,8); 391 int tl = bits(tlbdata,18,16); 392 int pri_context = bits(tlbdata,47,32); |
362 363 Addr vaddr = req->getVaddr(); | |
364 int context; 365 ContextType ct; 366 int asi; 367 bool real = false; | 393 int context; 394 ContextType ct; 395 int asi; 396 bool real = false; |
368 TlbEntry *e; | |
369 | 397 |
370 DPRINTF(TLB, "TLB: ITB Request to translate va=%#x size=%d\n", 371 vaddr, req->getSize()); | |
372 DPRINTF(TLB, "TLB: priv:%d hpriv:%d red:%d lsuim:%d part_id: %#X\n", 373 priv, hpriv, red, lsu_im, part_id); 374 | 398 DPRINTF(TLB, "TLB: priv:%d hpriv:%d red:%d lsuim:%d part_id: %#X\n", 399 priv, hpriv, red, lsu_im, part_id); 400 |
375 assert(req->getAsi() == ASI_IMPLICIT); 376 | |
377 if (tl > 0) { 378 asi = ASI_N; 379 ct = Nucleus; 380 context = 0; 381 } else { 382 asi = ASI_P; 383 ct = Primary; 384 context = pri_context; 385 } 386 387 if ( hpriv || red ) { | 401 if (tl > 0) { 402 asi = ASI_N; 403 ct = Nucleus; 404 context = 0; 405 } else { 406 asi = ASI_P; 407 ct = Primary; 408 context = pri_context; 409 } 410 411 if ( hpriv || red ) { |
388 req->setPaddr(req->getVaddr() & PAddrImplMask); | 412 cacheValid = true; 413 cacheState = tlbdata; 414 cacheEntry = NULL; 415 req->setPaddr(vaddr & PAddrImplMask); |
389 return NoFault; 390 } 391 | 416 return NoFault; 417 } 418 |
392 // If the asi is unaligned trap 393 if (vaddr & req->getSize()-1) { | 419 // If the access is unaligned trap 420 if (vaddr & 0x3) { |
394 writeSfsr(tc, false, ct, false, OtherFault, asi); 395 return new MemAddressNotAligned; 396 } 397 398 if (addr_mask) 399 vaddr = vaddr & VAddrAMask; 400 401 if (!validVirtualAddress(vaddr, addr_mask)) { 402 writeSfsr(tc, false, ct, false, VaOutOfRange, asi); 403 return new InstructionAccessException; 404 } 405 406 if (!lsu_im) { | 421 writeSfsr(tc, false, ct, false, OtherFault, asi); 422 return new MemAddressNotAligned; 423 } 424 425 if (addr_mask) 426 vaddr = vaddr & VAddrAMask; 427 428 if (!validVirtualAddress(vaddr, addr_mask)) { 429 writeSfsr(tc, false, ct, false, VaOutOfRange, asi); 430 return new InstructionAccessException; 431 } 432 433 if (!lsu_im) { |
407 e = lookup(req->getVaddr(), part_id, true); | 434 e = lookup(vaddr, part_id, true); |
408 real = true; 409 context = 0; 410 } else { 411 e = lookup(vaddr, part_id, false, context); 412 } 413 414 if (e == NULL || !e->valid) { 415 tc->setMiscReg(MISCREG_MMU_ITLB_TAG_ACCESS, --- 5 unchanged lines hidden (view full) --- 421 } 422 423 // were not priviledged accesing priv page 424 if (!priv && e->pte.priv()) { 425 writeSfsr(tc, false, ct, false, PrivViolation, asi); 426 return new InstructionAccessException; 427 } 428 | 435 real = true; 436 context = 0; 437 } else { 438 e = lookup(vaddr, part_id, false, context); 439 } 440 441 if (e == NULL || !e->valid) { 442 tc->setMiscReg(MISCREG_MMU_ITLB_TAG_ACCESS, --- 5 unchanged lines hidden (view full) --- 448 } 449 450 // were not priviledged accesing priv page 451 if (!priv && e->pte.priv()) { 452 writeSfsr(tc, false, ct, false, PrivViolation, asi); 453 return new InstructionAccessException; 454 } 455 |
456 // cache translation date for next translation 457 cacheValid = true; 458 cacheState = tlbdata; 459 cacheEntry = e; 460 |
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429 req->setPaddr(e->pte.paddr() & ~(e->pte.size()-1) | | 461 req->setPaddr(e->pte.paddr() & ~(e->pte.size()-1) | |
430 req->getVaddr() & e->pte.size()-1 ); 431 DPRINTF(TLB, "TLB: %#X -> %#X\n", req->getVaddr(), req->getPaddr()); | 462 vaddr & e->pte.size()-1 ); 463 DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr()); |
432 return NoFault; 433} 434 435 436 437Fault 438DTB::translate(RequestPtr &req, ThreadContext *tc, bool write) 439{ 440 /* @todo this could really use some profiling and fixing to make it faster! */ 441 uint64_t tlbdata = tc->readMiscReg(MISCREG_TLB_DATA); | 464 return NoFault; 465} 466 467 468 469Fault 470DTB::translate(RequestPtr &req, ThreadContext *tc, bool write) 471{ 472 /* @todo this could really use some profiling and fixing to make it faster! */ 473 uint64_t tlbdata = tc->readMiscReg(MISCREG_TLB_DATA); |
442 | 474 Addr vaddr = req->getVaddr(); 475 Addr size = req->getSize(); 476 ASI asi; 477 asi = (ASI)req->getAsi(); 478 bool implicit = false; |
443 bool hpriv = bits(tlbdata,0,0); | 479 bool hpriv = bits(tlbdata,0,0); |
480 481 DPRINTF(TLB, "TLB: DTB Request to translate va=%#x size=%d asi=%#x\n", 482 vaddr, size, asi); 483 484 if (asi == ASI_IMPLICIT) 485 implicit = true; 486 487 if (hpriv && implicit) { 488 req->setPaddr(vaddr & PAddrImplMask); 489 return NoFault; 490 } 491 492 // Be fast if we can! 493 if (cacheValid && cacheState == tlbdata) { 494 if (cacheEntry[0] && cacheAsi[0] == asi && cacheEntry[0]->range.va < vaddr + size && 495 cacheEntry[0]->range.va + cacheEntry[0]->range.size >= vaddr) { 496 req->setPaddr(cacheEntry[0]->pte.paddr() & ~(cacheEntry[0]->pte.size()-1) | 497 vaddr & cacheEntry[0]->pte.size()-1 ); 498 return NoFault; 499 } 500 if (cacheEntry[1] && cacheAsi[1] == asi && cacheEntry[1]->range.va < vaddr + size && 501 cacheEntry[1]->range.va + cacheEntry[1]->range.size >= vaddr) { 502 req->setPaddr(cacheEntry[1]->pte.paddr() & ~(cacheEntry[1]->pte.size()-1) | 503 vaddr & cacheEntry[1]->pte.size()-1 ); 504 return NoFault; 505 } 506 } 507 |
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444 bool red = bits(tlbdata,1,1); 445 bool priv = bits(tlbdata,2,2); 446 bool addr_mask = bits(tlbdata,3,3); 447 bool lsu_dm = bits(tlbdata,5,5); 448 449 int part_id = bits(tlbdata,15,8); 450 int tl = bits(tlbdata,18,16); 451 int pri_context = bits(tlbdata,47,32); 452 int sec_context = bits(tlbdata,47,32); 453 | 508 bool red = bits(tlbdata,1,1); 509 bool priv = bits(tlbdata,2,2); 510 bool addr_mask = bits(tlbdata,3,3); 511 bool lsu_dm = bits(tlbdata,5,5); 512 513 int part_id = bits(tlbdata,15,8); 514 int tl = bits(tlbdata,18,16); 515 int pri_context = bits(tlbdata,47,32); 516 int sec_context = bits(tlbdata,47,32); 517 |
454 bool implicit = false; | |
455 bool real = false; | 518 bool real = false; |
456 Addr vaddr = req->getVaddr(); 457 Addr size = req->getSize(); | |
458 ContextType ct = Primary; 459 int context = 0; | 519 ContextType ct = Primary; 520 int context = 0; |
460 ASI asi; | |
461 462 TlbEntry *e; 463 | 521 522 TlbEntry *e; 523 |
464 asi = (ASI)req->getAsi(); 465 DPRINTF(TLB, "TLB: DTB Request to translate va=%#x size=%d asi=%#x\n", 466 vaddr, size, asi); | |
467 DPRINTF(TLB, "TLB: priv:%d hpriv:%d red:%d lsudm:%d part_id: %#X\n", 468 priv, hpriv, red, lsu_dm, part_id); | 524 DPRINTF(TLB, "TLB: priv:%d hpriv:%d red:%d lsudm:%d part_id: %#X\n", 525 priv, hpriv, red, lsu_dm, part_id); |
469 if (asi == ASI_IMPLICIT) 470 implicit = true; | |
471 472 if (implicit) { 473 if (tl > 0) { 474 asi = ASI_N; 475 ct = Nucleus; 476 context = 0; 477 } else { 478 asi = ASI_P; --- 78 unchanged lines hidden (view full) --- 557 558 559 if ((!lsu_dm && !hpriv) || AsiIsReal(asi)) { 560 real = true; 561 context = 0; 562 }; 563 564 if (hpriv && (implicit || (!AsiIsAsIfUser(asi) && !AsiIsReal(asi)))) { | 526 527 if (implicit) { 528 if (tl > 0) { 529 asi = ASI_N; 530 ct = Nucleus; 531 context = 0; 532 } else { 533 asi = ASI_P; --- 78 unchanged lines hidden (view full) --- 612 613 614 if ((!lsu_dm && !hpriv) || AsiIsReal(asi)) { 615 real = true; 616 context = 0; 617 }; 618 619 if (hpriv && (implicit || (!AsiIsAsIfUser(asi) && !AsiIsReal(asi)))) { |
565 req->setPaddr(req->getVaddr() & PAddrImplMask); | 620 req->setPaddr(vaddr & PAddrImplMask); |
566 return NoFault; 567 } 568 | 621 return NoFault; 622 } 623 |
569 e = lookup(req->getVaddr(), part_id, real, context); | 624 e = lookup(vaddr, part_id, real, context); |
570 571 if (e == NULL || !e->valid) { 572 tc->setMiscReg(MISCREG_MMU_DTLB_TAG_ACCESS, 573 vaddr & ~BytesInPageMask | context); 574 DPRINTF(TLB, "TLB: DTB Failed to find matching TLB entry\n"); 575 if (real) 576 return new DataRealTranslationMiss; 577 else --- 16 unchanged lines hidden (view full) --- 594 req->setFlags(req->getFlags() | UNCACHEABLE); 595 596 597 if (!priv && e->pte.priv()) { 598 writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), PrivViolation, asi); 599 return new DataAccessException; 600 } 601 | 625 626 if (e == NULL || !e->valid) { 627 tc->setMiscReg(MISCREG_MMU_DTLB_TAG_ACCESS, 628 vaddr & ~BytesInPageMask | context); 629 DPRINTF(TLB, "TLB: DTB Failed to find matching TLB entry\n"); 630 if (real) 631 return new DataRealTranslationMiss; 632 else --- 16 unchanged lines hidden (view full) --- 649 req->setFlags(req->getFlags() | UNCACHEABLE); 650 651 652 if (!priv && e->pte.priv()) { 653 writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), PrivViolation, asi); 654 return new DataAccessException; 655 } 656 |
657 // cache translation date for next translation 658 cacheValid = true; 659 cacheState = tlbdata; 660 if (cacheEntry[0] != e && cacheEntry[1] != e) { 661 cacheEntry[1] = cacheEntry[0]; 662 cacheEntry[0] = e; 663 cacheAsi[1] = cacheAsi[0]; 664 cacheAsi[0] = asi; 665 if (implicit) 666 cacheAsi[0] = (ASI)0; 667 } 668 |
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602 req->setPaddr(e->pte.paddr() & ~(e->pte.size()-1) | | 669 req->setPaddr(e->pte.paddr() & ~(e->pte.size()-1) | |
603 req->getVaddr() & e->pte.size()-1); 604 DPRINTF(TLB, "TLB: %#X -> %#X\n", req->getVaddr(), req->getPaddr()); | 670 vaddr & e->pte.size()-1); 671 DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr()); |
605 return NoFault; 606 /** Normal flow ends here. */ 607 608handleScratchRegAccess: 609 if (vaddr > 0x38 || (vaddr >= 0x20 && vaddr < 0x30 && !hpriv)) { 610 writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi); 611 return new DataAccessException; 612 } --- 155 unchanged lines hidden (view full) --- 768 cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG); 769 } else { 770 tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS0); 771 cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG); 772 } 773 data = mbits(tsbtemp,63,13); 774 data |= temp >> (9 + bits(cnftemp,2,0) * 3) & 775 mbits((uint64_t)-1ll,12+bits(tsbtemp,3,0), 4); | 672 return NoFault; 673 /** Normal flow ends here. */ 674 675handleScratchRegAccess: 676 if (vaddr > 0x38 || (vaddr >= 0x20 && vaddr < 0x30 && !hpriv)) { 677 writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi); 678 return new DataAccessException; 679 } --- 155 unchanged lines hidden (view full) --- 835 cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG); 836 } else { 837 tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS0); 838 cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG); 839 } 840 data = mbits(tsbtemp,63,13); 841 data |= temp >> (9 + bits(cnftemp,2,0) * 3) & 842 mbits((uint64_t)-1ll,12+bits(tsbtemp,3,0), 4); |
776 warn("base addr: %#X tag access: %#X page size: %#X tsb size: %#X\n", 777 bits(tsbtemp,63,13), temp, bits(cnftemp,2,0), bits(tsbtemp,3,0)); | |
778 pkt->set(data); 779 break; 780 case ASI_DMMU_TSB_PS1_PTR_REG: 781 temp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS); 782 if (bits(temp,12,0) == 0) { 783 tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS1); 784 cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG); 785 } else { --- 228 unchanged lines hidden --- | 843 pkt->set(data); 844 break; 845 case ASI_DMMU_TSB_PS1_PTR_REG: 846 temp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS); 847 if (bits(temp,12,0) == 0) { 848 tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS1); 849 cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG); 850 } else { --- 228 unchanged lines hidden --- |