1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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126 tlb[x].used = false;
127 usedEntries--;
128 }
129 lookupTable.erase(tlb[x].range);
130 }
131 }
132 }
133
134/*
135 i = lookupTable.find(tr);
136 if (i != lookupTable.end()) {
137 i->second->valid = false;
138 if (i->second->used) {
139 i->second->used = false;
140 usedEntries--;
141 }
142 freeList.push_front(i->second);
143 DPRINTF(TLB, "TLB: Found conflicting entry %#X , deleting it\n",
144 i->second);
145 lookupTable.erase(i);
146 }
147*/
148
149 if (entry != -1) {
150 assert(entry < size && entry >= 0);
151 new_entry = &tlb[entry];
152 } else {
153 if (!freeList.empty()) {
154 new_entry = freeList.front();
155 } else {
156 x = lastReplaced;
157 do {
158 ++x;
159 if (x == size)
160 x = 0;
161 if (x == lastReplaced)
162 goto insertAllLocked;
163 } while (tlb[x].pte.locked());
164 lastReplaced = x;
165 new_entry = &tlb[x];
166 }
167 /*
168 for (x = 0; x < size; x++) {
169 if (!tlb[x].valid || !tlb[x].used) {
170 new_entry = &tlb[x];
171 break;
172 }
173 }*/
174 }
175
176insertAllLocked:
177 // Update the last ently if their all locked
178 if (!new_entry) {
179 new_entry = &tlb[size-1];
180 }
181

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637 context = 0;
638 } else {
639 asi = ASI_P;
640 ct = Primary;
641 context = pri_context;
642 }
643 } else {
644 // We need to check for priv level/asi priv
645 if (!priv && !hpriv && !AsiIsUnPriv(asi)) {
646 // It appears that context should be Nucleus in these cases?
647 writeSfsr(vaddr, write, Nucleus, false, IllegalAsi, asi);
648 return new PrivilegedAction;
649 }
650
651 if (!hpriv && AsiIsHPriv(asi)) {
652 writeSfsr(vaddr, write, Nucleus, false, IllegalAsi, asi);
653 return new DataAccessException;
654 }
655
656 if (AsiIsPrimary(asi)) {
657 context = pri_context;
658 ct = Primary;
659 } else if (AsiIsSecondary(asi)) {
660 context = sec_context;
661 ct = Secondary;
662 } else if (AsiIsNucleus(asi)) {
663 ct = Nucleus;
664 context = 0;
665 } else { // ????
666 ct = Primary;
667 context = pri_context;
668 }
669 }
670
671 if (!implicit && asi != ASI_P && asi != ASI_S) {
672 if (AsiIsLittle(asi))
673 panic("Little Endian ASIs not supported\n");
674
675 //XXX It's unclear from looking at the documentation how a no fault
676 //load differs from a regular one, other than what happens concerning
677 //nfo and e bits in the TTE
678// if (AsiIsNoFault(asi))
679// panic("No Fault ASIs not supported\n");
680
681 if (AsiIsPartialStore(asi))
682 panic("Partial Store ASIs not supported\n");
683
684 if (AsiIsCmt(asi))
685 panic("Cmt ASI registers not implmented\n");
686
687 if (AsiIsInterrupt(asi))
688 goto handleIntRegAccess;
689 if (AsiIsMmu(asi))
690 goto handleMmuRegAccess;
691 if (AsiIsScratchPad(asi))
692 goto handleScratchRegAccess;
693 if (AsiIsQueue(asi))
694 goto handleQueueRegAccess;
695 if (AsiIsSparcError(asi))
696 goto handleSparcErrorRegAccess;
697
698 if (!AsiIsReal(asi) && !AsiIsNucleus(asi) && !AsiIsAsIfUser(asi) &&
699 !AsiIsTwin(asi) && !AsiIsBlock(asi) && !AsiIsNoFault(asi))
700 panic("Accessing ASI %#X. Should we?\n", asi);
701 }
702
703 // If the asi is unaligned trap
704 if (unaligned) {
705 writeSfsr(vaddr, false, ct, false, OtherFault, asi);
706 return new MemAddressNotAligned;
707 }
708
709 if (addr_mask)
710 vaddr = vaddr & VAddrAMask;
711
712 if (!validVirtualAddress(vaddr, addr_mask)) {
713 writeSfsr(vaddr, false, ct, true, VaOutOfRange, asi);
714 return new DataAccessException;
715 }
716
717 if ((!lsu_dm && !hpriv && !red) || AsiIsReal(asi)) {
718 real = true;
719 context = 0;
720 }
721
722 if (hpriv && (implicit || (!AsiIsAsIfUser(asi) && !AsiIsReal(asi)))) {
723 req->setPaddr(vaddr & PAddrImplMask);
724 return NoFault;
725 }
726
727 e = lookup(vaddr, part_id, real, context);
728
729 if (e == NULL || !e->valid) {
730 writeTagAccess(vaddr, context);

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747 }
748
749 if (write && !e->pte.writable()) {
750 writeTagAccess(vaddr, context);
751 writeSfsr(vaddr, write, ct, e->pte.sideffect(), OtherFault, asi);
752 return new FastDataAccessProtection;
753 }
754
755 if (e->pte.nofault() && !AsiIsNoFault(asi)) {
756 writeTagAccess(vaddr, context);
757 writeSfsr(vaddr, write, ct, e->pte.sideffect(), LoadFromNfo, asi);
758 return new DataAccessException;
759 }
760
761 if (e->pte.sideffect() && AsiIsNoFault(asi)) {
762 writeTagAccess(vaddr, context);
763 writeSfsr(vaddr, write, ct, e->pte.sideffect(), SideEffect, asi);
764 return new DataAccessException;
765 }
766
767 if (e->pte.sideffect() || (e->pte.paddr() >> 39) & 1)
768 req->setFlags(Request::UNCACHEABLE);
769

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1202 break;
1203 case 3:
1204 ctx_id = 0;
1205 break;
1206 default:
1207 ignore = true;
1208 }
1209
1210 switch(bits(va,7,6)) {
1211 case 0: // demap page
1212 if (!ignore)
1213 tc->getITBPtr()->demapPage(mbits(va,63,13), part_id,
1214 bits(va,9,9), ctx_id);
1215 break;
1216 case 1: //demap context
1217 if (!ignore)
1218 tc->getITBPtr()->demapContext(part_id, ctx_id);
1219 break;
1220 case 2:
1221 tc->getITBPtr()->demapAll(part_id);
1222 break;
1223 default:
1224 panic("Invalid type for IMMU demap\n");

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1253 break;
1254 case 3:
1255 ctx_id = 0;
1256 break;
1257 default:
1258 ignore = true;
1259 }
1260
1261 switch(bits(va,7,6)) {
1262 case 0: // demap page
1263 if (!ignore)
1264 demapPage(mbits(va,63,13), part_id, bits(va,9,9), ctx_id);
1265 break;
1266 case 1: //demap context
1267 if (!ignore)
1268 demapContext(part_id, ctx_id);
1269 break;
1270 case 2:
1271 demapAll(part_id);
1272 break;
1273 default:
1274 panic("Invalid type for IMMU demap\n");

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