1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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38#include "cpu/thread_context.hh"
39#include "cpu/base.hh"
40#include "mem/packet_access.hh"
41#include "mem/request.hh"
42#include "sim/builder.hh"
43
44/* @todo remove some of the magic constants. -- ali
45 * */
46namespace SparcISA {
47
48TLB::TLB(const std::string &name, int s)
49 : SimObject(name), size(s), usedEntries(0), lastReplaced(0),
50 cacheValid(false)
51{
52 // To make this work you'll have to change the hypervisor and OS
53 if (size > 64)
54 fatal("SPARC T1 TLB registers don't support more than 64 TLB entries.");

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590
591 if (hpriv && implicit) {
592 req->setPaddr(vaddr & PAddrImplMask);
593 return NoFault;
594 }
595
596 // Be fast if we can!
597 if (cacheValid && cacheState == tlbdata) {
598 if (cacheEntry[0] && cacheAsi[0] == asi && cacheEntry[0]->range.va < vaddr + size &&
599 cacheEntry[0]->range.va + cacheEntry[0]->range.size > vaddr &&
600 (!write || cacheEntry[0]->pte.writable())) {
601 req->setPaddr(cacheEntry[0]->pte.paddr() & ~(cacheEntry[0]->pte.size()-1) |
602 vaddr & cacheEntry[0]->pte.size()-1 );
603 return NoFault;
604 }
605 if (cacheEntry[1] && cacheAsi[1] == asi && cacheEntry[1]->range.va < vaddr + size &&
606 cacheEntry[1]->range.va + cacheEntry[1]->range.size > vaddr &&
607 (!write || cacheEntry[1]->pte.writable())) {
608 req->setPaddr(cacheEntry[1]->pte.paddr() & ~(cacheEntry[1]->pte.size()-1) |
609 vaddr & cacheEntry[1]->pte.size()-1 );
610 return NoFault;
611 }
612 }
613
614 bool red = bits(tlbdata,1,1);
615 bool priv = bits(tlbdata,2,2);
616 bool addr_mask = bits(tlbdata,3,3);
617 bool lsu_dm = bits(tlbdata,5,5);
618
619 int part_id = bits(tlbdata,15,8);
620 int tl = bits(tlbdata,18,16);
621 int pri_context = bits(tlbdata,47,32);

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750
751 if (e->pte.sideffect() && AsiIsNoFault(asi)) {
752 writeTagAccess(tc, vaddr, context);
753 writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), SideEffect, asi);
754 return new DataAccessException;
755 }
756
757
758 if (e->pte.sideffect())
759 req->setFlags(req->getFlags() | UNCACHEABLE);
760
761 // cache translation date for next translation
762 cacheState = tlbdata;
763 if (!cacheValid) {
764 cacheEntry[1] = NULL;
765 cacheEntry[0] = NULL;
766 }

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1323 for (int x = 0; x < size; x++) {
1324 tlb[x].unserialize(cp, csprintf("%s.PTE%d", section, x));
1325 if (tlb[x].valid)
1326 lookupTable.insert(tlb[x].range, &tlb[x]);
1327
1328 }
1329}
1330
1331/* end namespace SparcISA */ }
1332
1333using namespace SparcISA;
1334
1335DEFINE_SIM_OBJECT_CLASS_NAME("SparcTLB", TLB)
1336
1337BEGIN_DECLARE_SIM_OBJECT_PARAMS(ITB)
1338
1339 Param<int> size;
1340
1341END_DECLARE_SIM_OBJECT_PARAMS(ITB)
1342

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1368
1369
1370CREATE_SIM_OBJECT(DTB)
1371{
1372 return new DTB(getInstanceName(), size);
1373}
1374
1375REGISTER_SIM_OBJECT("SparcDTB", DTB)